From 65edced76b8e1a3fdccb136fb33288b0ed150477 Mon Sep 17 00:00:00 2001 From: Quentin Colombet Date: Thu, 18 Sep 2014 21:17:50 +0000 Subject: [PATCH] [ARM] Do not perform a tail call when the caller returns several values. The fix is slightly different then x86 (see r216117) because the number of values attached to a return can vary even for a single returned value (e.g., f64 yields two returned values). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218076 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMISelLowering.cpp | 12 ++++- test/CodeGen/ARM/no-tail-call.ll | 84 ++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/ARM/no-tail-call.ll diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 14cd7d7bd85..ca6b614ce2e 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -2313,9 +2313,15 @@ bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const { if (Copies.count(UseChain.getNode())) // Second CopyToReg Copy = *UI; - else + else { + // We are at the top of this chain. + // If the copy has a glue operand, we conservatively assume it + // isn't safe to perform a tail call. + if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue) + return false; // First CopyToReg TCChain = UseChain; + } } } else if (Copy->getOpcode() == ISD::BITCAST) { // f32 returned in a single GPR. @@ -2324,6 +2330,10 @@ bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const { Copy = *Copy->use_begin(); if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0)) return false; + // If the copy has a glue operand, we conservatively assume it isn't safe to + // perform a tail call. + if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) + return false; TCChain = Copy->getOperand(0); } else { return false; diff --git a/test/CodeGen/ARM/no-tail-call.ll b/test/CodeGen/ARM/no-tail-call.ll new file mode 100644 index 00000000000..3a8cb21bee9 --- /dev/null +++ b/test/CodeGen/ARM/no-tail-call.ll @@ -0,0 +1,84 @@ +; RUN: llc < %s -O0 -o - | FileCheck %s +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "armv7s-apple-ios7" + +%foo = type <{ %Sf }> +%Sf = type <{ float }> + +declare float @llvm.ceil.f32(float) + +; Check that we are not emitting a tail call for the last call to ceil. +; This function returns three different results. +; CHECK-LABEL: func1: +; CHECK-NOT: b _ceilf +; CHECK: pop +define { float, float, float } @func1() { +entry: + %0 = alloca %foo, align 4 + %1 = alloca %foo, align 4 + %2 = alloca %foo, align 4 + %.native = getelementptr inbounds %foo* %0, i32 0, i32 0 + %.native.value = getelementptr inbounds %Sf* %.native, i32 0, i32 0 + store float 0.000000e+00, float* %.native.value, align 4 + %.native1 = getelementptr inbounds %foo* %1, i32 0, i32 0 + %.native1.value = getelementptr inbounds %Sf* %.native1, i32 0, i32 0 + store float 1.000000e+00, float* %.native1.value, align 4 + %.native2 = getelementptr inbounds %foo* %2, i32 0, i32 0 + %.native2.value = getelementptr inbounds %Sf* %.native2, i32 0, i32 0 + store float 5.000000e+00, float* %.native2.value, align 4 + br i1 true, label %3, label %4 + +;