From 663291e4e678b0e23cba9858842f03eae79c199e Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Tue, 5 Nov 2013 14:51:41 +0800 Subject: [PATCH] rk319x: add initial support --- arch/arm/Kconfig | 17 + arch/arm/Makefile | 1 + arch/arm/configs/rk3190_fpga_defconfig | 130 ++ arch/arm/mach-rk30/common.c | 2 +- arch/arm/mach-rk30/devices.c | 110 +- arch/arm/mach-rk30/include/mach/gpio.h | 4 + arch/arm/mach-rk30/pm.c | 4 +- arch/arm/mach-rk319x/Kconfig | 22 + arch/arm/mach-rk319x/Makefile | 23 + arch/arm/mach-rk319x/Makefile.boot | 3 + arch/arm/mach-rk319x/board-rk3190-fpga.c | 1052 +++++++++++++++++ arch/arm/mach-rk319x/include/mach/board.h | 1 + arch/arm/mach-rk319x/include/mach/clkdev.h | 1 + arch/arm/mach-rk319x/include/mach/clock.h | 1 + arch/arm/mach-rk319x/include/mach/cpu_axi.h | 8 + arch/arm/mach-rk319x/include/mach/ddr.h | 1 + .../mach-rk319x/include/mach/debug-macro.S | 1 + .../arm/mach-rk319x/include/mach/debug_uart.h | 1 + arch/arm/mach-rk319x/include/mach/dma-pl330.h | 1 + arch/arm/mach-rk319x/include/mach/dvfs.h | 14 + .../mach-rk319x/include/mach/entry-macro.S | 1 + arch/arm/mach-rk319x/include/mach/fiq.h | 1 + arch/arm/mach-rk319x/include/mach/gpio.h | 1 + arch/arm/mach-rk319x/include/mach/grf.h | 196 +++ arch/arm/mach-rk319x/include/mach/hardware.h | 4 + arch/arm/mach-rk319x/include/mach/io.h | 393 ++++++ arch/arm/mach-rk319x/include/mach/iomux.h | 202 ++++ arch/arm/mach-rk319x/include/mach/irqs.h | 101 ++ arch/arm/mach-rk319x/include/mach/loader.h | 1 + arch/arm/mach-rk319x/include/mach/memory.h | 15 + arch/arm/mach-rk319x/include/mach/pmu.h | 50 + arch/arm/mach-rk319x/include/mach/sram.h | 1 + arch/arm/mach-rk319x/include/mach/system.h | 1 + arch/arm/mach-rk319x/include/mach/timex.h | 1 + .../arm/mach-rk319x/include/mach/uncompress.h | 1 + arch/arm/mach-rk319x/include/mach/vmalloc.h | 1 + arch/arm/mach-rk319x/io.c | 62 + arch/arm/mach-rk319x/rk_timer.c | 108 ++ arch/arm/plat-rk/Kconfig | 12 +- arch/arm/plat-rk/include/plat/memory.h | 4 + arch/arm/plat-rk/iomux.c | 10 + arch/arm/plat-rk/sram.c | 2 + drivers/adc/plat/Kconfig | 4 +- drivers/base/cpu.c | 2 +- drivers/gpio/Makefile | 1 + drivers/gpio/gpio-rk30.c | 20 +- drivers/i2c/busses/Kconfig | 10 +- drivers/i2c/busses/i2c-rk30.c | 3 + drivers/mmc/host/Kconfig | 2 +- drivers/mmc/host/rk29_sdmmc.c | 2 +- drivers/rtc/rtc-HYM8563.c | 2 +- drivers/tty/serial/Kconfig | 5 +- sound/soc/rk29/Kconfig | 2 +- 53 files changed, 2589 insertions(+), 29 deletions(-) create mode 100644 arch/arm/configs/rk3190_fpga_defconfig create mode 100644 arch/arm/mach-rk319x/Kconfig create mode 100644 arch/arm/mach-rk319x/Makefile create mode 100644 arch/arm/mach-rk319x/Makefile.boot create mode 100644 arch/arm/mach-rk319x/board-rk3190-fpga.c create mode 100644 arch/arm/mach-rk319x/include/mach/board.h create mode 100644 arch/arm/mach-rk319x/include/mach/clkdev.h create mode 100644 arch/arm/mach-rk319x/include/mach/clock.h create mode 100644 arch/arm/mach-rk319x/include/mach/cpu_axi.h create mode 100644 arch/arm/mach-rk319x/include/mach/ddr.h create mode 100644 arch/arm/mach-rk319x/include/mach/debug-macro.S create mode 100644 arch/arm/mach-rk319x/include/mach/debug_uart.h create mode 100644 arch/arm/mach-rk319x/include/mach/dma-pl330.h create mode 100644 arch/arm/mach-rk319x/include/mach/dvfs.h create mode 100644 arch/arm/mach-rk319x/include/mach/entry-macro.S create mode 100644 arch/arm/mach-rk319x/include/mach/fiq.h create mode 100644 arch/arm/mach-rk319x/include/mach/gpio.h create mode 100644 arch/arm/mach-rk319x/include/mach/grf.h create mode 100644 arch/arm/mach-rk319x/include/mach/hardware.h create mode 100644 arch/arm/mach-rk319x/include/mach/io.h create mode 100644 arch/arm/mach-rk319x/include/mach/iomux.h create mode 100644 arch/arm/mach-rk319x/include/mach/irqs.h create mode 100644 arch/arm/mach-rk319x/include/mach/loader.h create mode 100644 arch/arm/mach-rk319x/include/mach/memory.h create mode 100644 arch/arm/mach-rk319x/include/mach/pmu.h create mode 100644 arch/arm/mach-rk319x/include/mach/sram.h create mode 100644 arch/arm/mach-rk319x/include/mach/system.h create mode 100644 arch/arm/mach-rk319x/include/mach/timex.h create mode 100644 arch/arm/mach-rk319x/include/mach/uncompress.h create mode 100644 arch/arm/mach-rk319x/include/mach/vmalloc.h create mode 100644 arch/arm/mach-rk319x/io.c create mode 100644 arch/arm/mach-rk319x/rk_timer.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 00b8b80a80a7..99490bb1bc09 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -928,6 +928,22 @@ config ARCH_RK3188 help Support for Rockchip's RK3188 SoCs. +config ARCH_RK319X + bool "Rockchip RK319X" + select PLAT_RK + select CPU_V7 + select ARM_GIC + select RK_PL330_DMA + select RK_TIMER + select HAVE_SMP + select MIGHT_HAVE_CACHE_L2X0 + select ARM_ERRATA_761320 if SMP + select ARM_ERRATA_764369 if SMP + select ARM_ERRATA_754322 + select ARM_ERRATA_775420 + help + Support for Rockchip's RK319X SoCs. + config PLAT_SPEAR bool "ST SPEAr" select ARM_AMBA @@ -1034,6 +1050,7 @@ source "arch/arm/mach-rk2928/Kconfig" source "arch/arm/mach-rk3026/Kconfig" source "arch/arm/mach-rk30/Kconfig" source "arch/arm/mach-rk3188/Kconfig" +source "arch/arm/mach-rk319x/Kconfig" source "arch/arm/mach-sa1100/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index a3c9b34c864d..1d341858dca0 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -176,6 +176,7 @@ machine-$(CONFIG_ARCH_RK2928) := rk2928 machine-$(CONFIG_ARCH_RK3026) := rk3026 machine-$(CONFIG_ARCH_RK30) := rk30 machine-$(CONFIG_ARCH_RK3188) := rk3188 +machine-$(CONFIG_ARCH_RK319X) := rk319x machine-$(CONFIG_ARCH_RPC) := rpc machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443 machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 diff --git a/arch/arm/configs/rk3190_fpga_defconfig b/arch/arm/configs/rk3190_fpga_defconfig new file mode 100644 index 000000000000..37c41f4b2c28 --- /dev/null +++ b/arch/arm/configs/rk3190_fpga_defconfig @@ -0,0 +1,130 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_LZO=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="root" +# CONFIG_RD_GZIP is not set +CONFIG_RD_LZO=y +CONFIG_INITRAMFS_COMPRESSION_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_PANIC_TIMEOUT=1 +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_ELF_CORE is not set +CONFIG_ASHMEM=y +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_ARCH_RK319X=y +# CONFIG_DDR_FREQ is not set +# CONFIG_DDR_TEST is not set +# CONFIG_RK29_LAST_LOG is not set +CONFIG_RK_DEBUG_UART=0 +CONFIG_MACH_RK3190_FPGA=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_FIQ_DEBUGGER=y +CONFIG_FIQ_DEBUGGER_NO_SLEEP=y +CONFIG_FIQ_DEBUGGER_CONSOLE=y +CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_COMPACTION=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init debug" +CONFIG_WAKELOCK=y +CONFIG_PM_RUNTIME=y +CONFIG_SUSPEND_TIME=y +CONFIG_NET=y +CONFIG_UNIX=y +# CONFIG_NET_ACTIVITY_STATS is not set +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_MTD=y +CONFIG_MISC_DEVICES=y +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_CONSOLE_TRANSLATIONS is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C3_RK30 is not set +# CONFIG_ADC is not set +CONFIG_EXPANDED_GPIO_NUM=0 +CONFIG_EXPANDED_GPIO_IRQ_NUM=0 +CONFIG_SPI_FPGA_GPIO_NUM=0 +CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0 +# CONFIG_HWMON is not set +# CONFIG_MFD_SUPPORT is not set +CONFIG_MEDIA_SUPPORT=y +CONFIG_VIDEO_DEV=y +CONFIG_SOC_CAMERA=y +CONFIG_ION=y +CONFIG_ION_ROCKCHIP=y +CONFIG_FB=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_RK29_BL is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_VERBOSE_PROCFS is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +CONFIG_SND_SOC=y +CONFIG_SND_RK29_SOC=y +CONFIG_SND_RK29_SOC_I2S_2CH=y +CONFIG_SND_I2S_DMA_EVENT_STATIC=y +CONFIG_SND_RK29_SOC_RK1000=y +CONFIG_SND_RK29_CODEC_SOC_SLAVE=y +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_RTC_CLASS=y +# CONFIG_CMMB is not set +# CONFIG_DNOTIFY is not set +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +CONFIG_SLUB_DEBUG_ON=y +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set diff --git a/arch/arm/mach-rk30/common.c b/arch/arm/mach-rk30/common.c index b2ae61f88646..a9d8c52a2f2b 100755 --- a/arch/arm/mach-rk30/common.c +++ b/arch/arm/mach-rk30/common.c @@ -61,7 +61,7 @@ static void __init rk30_l2_cache_init(void) { #ifdef CONFIG_CACHE_L2X0 u32 aux_ctrl, aux_ctrl_mask, data_latency_ctrl; -#if defined(CONFIG_ARCH_RK3188) +#if defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK319X) data_latency_ctrl = L2_LATENCY(2, 3, 1); #else unsigned int max_cpu_freq = 1608000; // kHz diff --git a/arch/arm/mach-rk30/devices.c b/arch/arm/mach-rk30/devices.c index 24083f58a31f..11fc965bfc4b 100755 --- a/arch/arm/mach-rk30/devices.c +++ b/arch/arm/mach-rk30/devices.c @@ -143,6 +143,45 @@ static struct rk29_pl330_platdata dmac1_pdata = { }, }; +#elif defined(CONFIG_ARCH_RK319X) + +static struct rk29_pl330_platdata dmac1_pdata = { + .peri = { + [0] = DMACH_MAX, + [1] = DMACH_MAX, + [2] = DMACH_MAX, + [3] = DMACH_MAX, + [4] = DMACH_I2S1_2CH_TX, + [5] = DMACH_I2S1_2CH_RX, + [6] = DMACH_SPDIF_TX, + [7] = DMACH_DMAC0_MEMTOMEM, + [8] = DMACH_MAX, + [9] = DMACH_MAX, + [10] = DMACH_MAX, + [11] = DMACH_MAX, + [12] = DMACH_MAX, + [13] = DMACH_MAX, + [14] = DMACH_MAX, + [15] = DMACH_MAX, + [16] = DMACH_MAX, + [17] = DMACH_MAX, + [18] = DMACH_MAX, + [19] = DMACH_MAX, + [20] = DMACH_MAX, + [21] = DMACH_MAX, + [22] = DMACH_MAX, + [23] = DMACH_MAX, + [24] = DMACH_MAX, + [25] = DMACH_MAX, + [26] = DMACH_MAX, + [27] = DMACH_MAX, + [28] = DMACH_MAX, + [29] = DMACH_MAX, + [30] = DMACH_MAX, + [31] = DMACH_MAX, + }, +}; + #else static struct rk29_pl330_platdata dmac1_pdata = { @@ -209,6 +248,47 @@ static struct resource resource_dmac2[] = { }, }; +#if defined(CONFIG_ARCH_RK319X) + +static struct rk29_pl330_platdata dmac2_pdata = { + .peri = { + [0] = DMACH_HSADC, + [1] = DMACH_SDMMC, + [2] = DMACH_SDIO, + [3] = DMACH_EMMC, + [4] = DMACH_UART0_TX, + [5] = DMACH_UART0_RX, + [6] = DMACH_UART1_TX, + [7] = DMACH_UART1_RX, + [8] = DMACH_UART2_TX, + [9] = DMACH_UART2_RX, + [10] = DMACH_UART3_TX, + [11] = DMACH_UART3_RX, + [12] = DMACH_SPI0_TX, + [13] = DMACH_SPI0_RX, + [14] = DMACH_SPI1_TX, + [15] = DMACH_SPI1_RX, + [16] = DMACH_DMAC1_MEMTOMEM, + [17] = DMACH_MAX, + [18] = DMACH_MAX, + [19] = DMACH_MAX, + [20] = DMACH_MAX, + [21] = DMACH_MAX, + [22] = DMACH_MAX, + [23] = DMACH_MAX, + [24] = DMACH_MAX, + [25] = DMACH_MAX, + [26] = DMACH_MAX, + [27] = DMACH_MAX, + [28] = DMACH_MAX, + [29] = DMACH_MAX, + [30] = DMACH_MAX, + [31] = DMACH_MAX, + }, +}; + +#else + static struct rk29_pl330_platdata dmac2_pdata = { .peri = { [0] = DMACH_HSADC, @@ -246,6 +326,8 @@ static struct rk29_pl330_platdata dmac2_pdata = { }, }; +#endif + static struct platform_device device_dmac2 = { .name = "rk29-pl330", .id = 2, @@ -427,10 +509,28 @@ static void __init rk30_init_uart(void) #define I2C4_END RK30_I2C4_PHYS + SZ_16K - 1 #endif +#if defined(CONFIG_ARCH_RK319X) +#define I2C0_ADAP_TYPE I2C_RK30_ADAP +#define I2C0_START RK319X_I2C0_PHYS +#define I2C0_END RK319X_I2C0_PHYS + RK319X_I2C0_SIZE - 1 +#define I2C1_ADAP_TYPE I2C_RK30_ADAP +#define I2C1_START RK319X_I2C1_PHYS +#define I2C1_END RK319X_I2C1_PHYS + RK319X_I2C1_SIZE - 1 +#define I2C2_ADAP_TYPE I2C_RK30_ADAP +#define I2C2_START RK319X_I2C2_PHYS +#define I2C2_END RK319X_I2C2_PHYS + RK319X_I2C2_SIZE - 1 +#define I2C3_ADAP_TYPE I2C_RK30_ADAP +#define I2C3_START RK319X_I2C3_PHYS +#define I2C3_END RK319X_I2C3_PHYS + RK319X_I2C3_SIZE - 1 +#define I2C4_ADAP_TYPE I2C_RK30_ADAP +#define I2C4_START RK319X_I2C4_PHYS +#define I2C4_END RK319X_I2C4_PHYS + RK319X_I2C4_SIZE - 1 +#endif + #ifdef CONFIG_I2C0_RK30 static struct rk30_i2c_platform_data default_i2c0_data = { .bus_num = 0, -#if defined(CONFIG_ARCH_RK3066B) +#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK319X) .is_div_from_arm = 0, #else .is_div_from_arm = 1, @@ -467,7 +567,7 @@ static struct platform_device device_i2c0 = { #ifdef CONFIG_I2C1_RK30 static struct rk30_i2c_platform_data default_i2c1_data = { .bus_num = 1, -#if defined(CONFIG_ARCH_RK3066B) +#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK319X) .is_div_from_arm = 0, #else .is_div_from_arm = 1, @@ -904,6 +1004,7 @@ static struct platform_device device_rga = { }; #endif +#ifdef IRQ_IPP static struct resource resource_ipp[] = { [0] = { .start = RK30_IPP_PHYS, @@ -923,6 +1024,7 @@ static struct platform_device device_ipp = { .num_resources = ARRAY_SIZE(resource_ipp), .resource = resource_ipp, }; +#endif #ifdef CONFIG_SND_RK29_SOC_I2S #ifdef CONFIG_SND_RK29_SOC_I2S_8CH @@ -1230,7 +1332,7 @@ static struct resource resource_arm_pmu[] = { .end = IRQ_ARM_PMU + 1, .flags = IORESOURCE_IRQ, }, -#if defined(CONFIG_ARCH_RK3188) +#if defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK319X) { .start = IRQ_ARM_PMU + 2, .end = IRQ_ARM_PMU + 2, @@ -1260,7 +1362,9 @@ static int __init rk30_init_devices(void) #ifdef CONFIG_RGA_RK30 platform_device_register(&device_rga); #endif +#ifdef IRQ_IPP platform_device_register(&device_ipp); +#endif #ifdef CONFIG_HDMI_RK30 platform_device_register(&device_hdmi); diff --git a/arch/arm/mach-rk30/include/mach/gpio.h b/arch/arm/mach-rk30/include/mach/gpio.h index 0dd2bdb987f2..343dfffe3d22 100755 --- a/arch/arm/mach-rk30/include/mach/gpio.h +++ b/arch/arm/mach-rk30/include/mach/gpio.h @@ -6,6 +6,8 @@ #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188) #define GPIO_BANKS 4 +#elif defined(CONFIG_ARCH_RK319X) +#define GPIO_BANKS 5 #else #define GPIO_BANKS 7 #endif @@ -175,7 +177,9 @@ #define RK30_PIN4_PD5 (4*NUM_GROUP + PIN_BASE + 29) #define RK30_PIN4_PD6 (4*NUM_GROUP + PIN_BASE + 30) #define RK30_PIN4_PD7 (4*NUM_GROUP + PIN_BASE + 31) +#endif +#if GPIO_BANKS > 5 #define RK30_PIN6_PA0 (6*NUM_GROUP + PIN_BASE + 0) #define RK30_PIN6_PA1 (6*NUM_GROUP + PIN_BASE + 1) #define RK30_PIN6_PA2 (6*NUM_GROUP + PIN_BASE + 2) diff --git a/arch/arm/mach-rk30/pm.c b/arch/arm/mach-rk30/pm.c index 5f01c666f151..59ba71e1c7fa 100755 --- a/arch/arm/mach-rk30/pm.c +++ b/arch/arm/mach-rk30/pm.c @@ -231,8 +231,10 @@ static noinline void rk30_pm_dump_irq(void) DUMP_GPIO_INT_STATUS(1); DUMP_GPIO_INT_STATUS(2); DUMP_GPIO_INT_STATUS(3); -#if !(defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)) +#if GPIO_BANKS > 4 DUMP_GPIO_INT_STATUS(4); +#endif +#if GPIO_BANKS > 5 DUMP_GPIO_INT_STATUS(6); #endif } diff --git a/arch/arm/mach-rk319x/Kconfig b/arch/arm/mach-rk319x/Kconfig new file mode 100644 index 000000000000..1eb6bceb17f2 --- /dev/null +++ b/arch/arm/mach-rk319x/Kconfig @@ -0,0 +1,22 @@ +choice + prompt "Rockchip SoC Type" + depends on ARCH_RK319X + +config SOC_RK3190 + bool "RK3190" + select USB_ARCH_HAS_EHCI if USB_SUPPORT + +endchoice + +choice + prompt "RK3190 Board Type" + depends on SOC_RK3190 + +config MACH_RK3190_TB + bool "RK3190 Top Board" + +config MACH_RK3190_FPGA + bool "RK3188 FPGA board" + select RK_FPGA + +endchoice diff --git a/arch/arm/mach-rk319x/Makefile b/arch/arm/mach-rk319x/Makefile new file mode 100644 index 000000000000..4264df4316f1 --- /dev/null +++ b/arch/arm/mach-rk319x/Makefile @@ -0,0 +1,23 @@ +EXTRA_CFLAGS += -Os +ifneq ($(CONFIG_RK_FPGA),y) +obj-y += ../plat-rk/clock.o +obj-y += clock_data.o +obj-y += ../mach-rk30/ddr.o +obj-y += ../mach-rk30/pmu.o +obj-y += ../mach-rk30/reset.o +obj-$(CONFIG_PM) += ../mach-rk30/pm.o +obj-y += ../mach-rk30/common.o +CFLAGS_common.o += -DTEXT_OFFSET=$(TEXT_OFFSET) +endif +obj-y += ../mach-rk30/devices.o +obj-y += io.o +obj-y += rk_timer.o +obj-$(CONFIG_SMP) += ../mach-rk30/platsmp.o ../mach-rk30/headsmp.o +obj-$(CONFIG_HOTPLUG_CPU) += ../mach-rk30/hotplug.o +obj-$(CONFIG_CPU_IDLE) += ../mach-rk30/cpuidle.o +obj-$(CONFIG_CPU_FREQ) += cpufreq.o +obj-$(CONFIG_DVFS) += dvfs.o +obj-y += board.o + +board-$(CONFIG_MACH_RK3190_FPGA) += board-rk3190-fpga.o +board-$(CONFIG_MACH_RK3190_TB) += board-rk3190-tb.o diff --git a/arch/arm/mach-rk319x/Makefile.boot b/arch/arm/mach-rk319x/Makefile.boot new file mode 100644 index 000000000000..85101fbb7ae8 --- /dev/null +++ b/arch/arm/mach-rk319x/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00408000 +params_phys-y := 0x00088000 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-rk319x/board-rk3190-fpga.c b/arch/arm/mach-rk319x/board-rk3190-fpga.c new file mode 100644 index 000000000000..2e5c17d12b9d --- /dev/null +++ b/arch/arm/mach-rk319x/board-rk3190-fpga.c @@ -0,0 +1,1052 @@ +/* + * Copyright (C) 2013 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + + +#ifdef CONFIG_VIDEO_RK29 +/*---------------- Camera Sensor Macro Define Begin ------------------------*/ +/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/ +#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */ +#define CONFIG_SENSOR_IIC_ADDR_0 0 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 4 +#define CONFIG_SENSOR_ORIENTATION_0 90 +#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_0 INVALID_GPIO +#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000 + +#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */ +#define CONFIG_SENSOR_IIC_ADDR_01 0x00 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4 +#define CONFIG_SENSOR_ORIENTATION_01 90 +#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_01 INVALID_GPIO +#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000 + +#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */ +#define CONFIG_SENSOR_IIC_ADDR_02 0x00 +#define CONFIG_SENSOR_CIF_INDEX_02 0 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4 +#define CONFIG_SENSOR_ORIENTATION_02 90 +#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO +#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000 + +#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */ +#define CONFIG_SENSOR_IIC_ADDR_1 0x60 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1 +#define CONFIG_SENSOR_ORIENTATION_1 270 +#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_1 INVALID_GPIO +#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000 + +#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */ +#define CONFIG_SENSOR_IIC_ADDR_11 0x00 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3 +#define CONFIG_SENSOR_ORIENTATION_11 270 +#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO +#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000 + +#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */ +#define CONFIG_SENSOR_IIC_ADDR_12 0x00 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3 +#define CONFIG_SENSOR_ORIENTATION_12 270 +#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO +#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000 + + +/*---------------- Camera Sensor Configuration Macro End------------------------*/ +#include "../../../drivers/media/video/rk30_camera.c" +/*---------------- Camera Sensor Macro Define End ---------*/ + +#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY +/***************************************************************************************** + * camera devices + * author: ddl@rock-chips.com + *****************************************************************************************/ +#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout +#define CONFIG_SENSOR_RESET_IOCTL_USR 0 +#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0 +#define CONFIG_SENSOR_FLASH_IOCTL_USR 0 + +static void rk_cif_power(int on) +{ + struct regulator *ldo_18,*ldo_28; + + ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif + ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif + if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)) { + printk("get cif ldo failed!\n"); + return; + } + if(on == 0) { + regulator_disable(ldo_28); + regulator_put(ldo_28); + regulator_disable(ldo_18); + regulator_put(ldo_18); + mdelay(500); + } else { + regulator_set_voltage(ldo_28, 2800000, 2800000); + regulator_enable(ldo_28); + // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28)); + regulator_put(ldo_28); + + regulator_set_voltage(ldo_18, 1800000, 1800000); + // regulator_set_suspend_voltage(ldo, 1800000); + regulator_enable(ldo_18); + // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18)); + regulator_put(ldo_18); + } +} + +#if CONFIG_SENSOR_POWER_IOCTL_USR +static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on) +{ + //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!"; + rk_cif_power(on); +} +#endif + +#if CONFIG_SENSOR_RESET_IOCTL_USR +static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on) +{ + #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!"; +} +#endif + +#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR +static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on) +{ + #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!"; +} +#endif + +#if CONFIG_SENSOR_FLASH_IOCTL_USR +static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on) +{ + #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!"; +} +#endif + +static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = { + #if CONFIG_SENSOR_POWER_IOCTL_USR + .sensor_power_cb = sensor_power_usr_cb, + #else + .sensor_power_cb = NULL, + #endif + + #if CONFIG_SENSOR_RESET_IOCTL_USR + .sensor_reset_cb = sensor_reset_usr_cb, + #else + .sensor_reset_cb = NULL, + #endif + + #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR + .sensor_powerdown_cb = sensor_powerdown_usr_cb, + #else + .sensor_powerdown_cb = NULL, + #endif + + #if CONFIG_SENSOR_FLASH_IOCTL_USR + .sensor_flash_cb = sensor_flash_usr_cb, + #else + .sensor_flash_cb = NULL, + #endif +}; + +#if CONFIG_SENSOR_IIC_ADDR_0 +static struct reginfo_t rk_init_data_sensor_reg_0[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_0[] = +{ + {0x0000, 0x00,0,0} +}; +#endif + +#if CONFIG_SENSOR_IIC_ADDR_1 +static struct reginfo_t rk_init_data_sensor_reg_1[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_1[] = +{ + {0x0000, 0x00,0,0} +}; +#endif +#if CONFIG_SENSOR_IIC_ADDR_01 +static struct reginfo_t rk_init_data_sensor_reg_01[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_01[] = +{ + {0x0000, 0x00,0,0} +}; +#endif +#if CONFIG_SENSOR_IIC_ADDR_02 +static struct reginfo_t rk_init_data_sensor_reg_02[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_02[] = +{ + {0x0000, 0x00,0,0} +}; +#endif +#if CONFIG_SENSOR_IIC_ADDR_11 +static struct reginfo_t rk_init_data_sensor_reg_11[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_11[] = +{ + {0x0000, 0x00,0,0} +}; +#endif +#if CONFIG_SENSOR_IIC_ADDR_12 +static struct reginfo_t rk_init_data_sensor_reg_12[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_12[] = +{ + {0x0000, 0x00,0,0} +}; +#endif +static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] = +{ + #if CONFIG_SENSOR_IIC_ADDR_0 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_0, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + #if CONFIG_SENSOR_IIC_ADDR_1 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_1, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + #if CONFIG_SENSOR_IIC_ADDR_01 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_01, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + #if CONFIG_SENSOR_IIC_ADDR_02 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_02, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + #if CONFIG_SENSOR_IIC_ADDR_11 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_11, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + #if CONFIG_SENSOR_IIC_ADDR_12 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_12, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + + }; +#include "../../../drivers/media/video/rk30_camera.c" + +#endif /* CONFIG_VIDEO_RK29 */ + +#ifdef CONFIG_FB_ROCKCHIP + +#define RK_FB_MEM_SIZE 3*SZ_1M + +#define LCD_CS_PIN INVALID_GPIO +#define LCD_CS_VALUE GPIO_HIGH + +#define LCD_EN_PIN INVALID_GPIO +#define LCD_EN_VALUE GPIO_LOW + +static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting) +{ + int ret = 0; + + if(LCD_CS_PIN != INVALID_GPIO) + { + ret = gpio_request(LCD_CS_PIN, NULL); + if (ret != 0) + { + gpio_free(LCD_CS_PIN); + printk(KERN_ERR "request lcd cs pin fail!\n"); + return -1; + } + else + { + gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE); + } + } + + if(LCD_EN_PIN != INVALID_GPIO) + { + ret = gpio_request(LCD_EN_PIN, NULL); + if (ret != 0) + { + gpio_free(LCD_EN_PIN); + printk(KERN_ERR "request lcd en pin fail!\n"); + return -1; + } + else + { + gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE); + } + } + return 0; +} +static int rk_fb_io_disable(void) +{ + if(LCD_CS_PIN != INVALID_GPIO) + { + gpio_set_value(LCD_CS_PIN, !LCD_CS_VALUE); + } + + if(LCD_EN_PIN != INVALID_GPIO) + { + gpio_set_value(LCD_EN_PIN, !LCD_EN_VALUE); + } + return 0; +} +static int rk_fb_io_enable(void) +{ + if(LCD_CS_PIN != INVALID_GPIO) + { + gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE); + } + + if(LCD_EN_PIN != INVALID_GPIO) + { + gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE); + } + return 0; +} + +struct rk29fb_info lcdc0_screen_info = { + .prop = PRMRY, //primary display device + .io_init = rk_fb_io_init, + .io_disable = rk_fb_io_disable, + .io_enable = rk_fb_io_enable, + .set_screen_info = set_lcd_info, +}; + +struct rk29fb_info lcdc1_screen_info = { + .prop = EXTEND, //extend display device + .lcd_info = NULL, + .set_screen_info = NULL, +}; + +static struct resource resource_fb[] = { + [0] = { + .name = "fb0 buf", + .start = 0, + .end = 0,//RK30_FB0_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "ipp buf", //for rotate + .start = 0, + .end = 0,//RK30_FB0_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .name = "fb2 buf", + .start = 0, + .end = 0,//RK30_FB0_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device device_fb = { + .name = "rk-fb", + .id = -1, + .num_resources = ARRAY_SIZE(resource_fb), + .resource = resource_fb, +}; +#endif + +#if defined(CONFIG_LCDC0_RK3188) +static struct resource resource_lcdc0[] = { + [0] = { + .name = "lcdc0 reg", + .start = RK30_LCDC0_PHYS, + .end = RK30_LCDC0_PHYS + RK30_LCDC0_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + + [1] = { + .name = "lcdc0 irq", + .start = IRQ_LCDC0, + .end = IRQ_LCDC0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device device_lcdc0 = { + .name = "rk3188-lcdc", + .id = 0, + .num_resources = ARRAY_SIZE(resource_lcdc0), + .resource = resource_lcdc0, + .dev = { + .platform_data = &lcdc0_screen_info, + }, +}; +#endif +#if defined(CONFIG_LCDC1_RK3188) +extern struct rk29fb_info lcdc1_screen_info; +static struct resource resource_lcdc1[] = { + [0] = { + .name = "lcdc1 reg", + .start = RK30_LCDC1_PHYS, + .end = RK30_LCDC1_PHYS + RK30_LCDC1_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "lcdc1 irq", + .start = IRQ_LCDC1, + .end = IRQ_LCDC1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device device_lcdc1 = { + .name = "rk3188-lcdc", + .id = 1, + .num_resources = ARRAY_SIZE(resource_lcdc1), + .resource = resource_lcdc1, + .dev = { + .platform_data = &lcdc1_screen_info, + }, +}; +#endif + +static struct i2c_board_info __initdata i2c0_info[] = { +#if defined (CONFIG_SND_SOC_RK1000) + { + .type = "rk1000_i2c_codec", + .addr = 0x60, + .flags = 0, + }, + { + .type = "rk1000_control", + .addr = 0x40, + .flags = 0, + }, +#endif +}; + +static struct i2c_board_info __initdata i2c1_info[] = { +}; + +static struct i2c_board_info __initdata i2c2_info[] = { +}; + +static struct i2c_board_info __initdata i2c3_info[] = { +}; + +static struct i2c_board_info __initdata i2c_gpio_info[] = { +}; + +static void __init rk30_i2c_register_board_info(void) +{ + i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info)); + i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info)); + i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info)); + i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info)); +} +//end of i2c + +static struct spi_board_info board_spi_devices[] = { +}; + +/*********************************************************** +* rk30 backlight +************************************************************/ +#define PWM_ID 1 +#define PWM_MUX_NAME GPIO0A3_PWM0_NAME +#define PWM_MUX_MODE GPIO0A_PWM0 +#define PWM_MUX_MODE_GPIO GPIO0A_GPIO0A3 +#define PWM_GPIO RK30_PIN0_PA3 +#define PWM_EFFECT_VALUE 1 + +#define LCD_DISP_ON_PIN + +#ifdef LCD_DISP_ON_PIN + +#define BL_EN_PIN RK30_PIN6_PB3 +#define BL_EN_VALUE GPIO_HIGH +#endif +static int rk29_backlight_io_init(void) +{ + int ret = 0; + return ret; +} + +static int rk29_backlight_io_deinit(void) +{ + int ret = 0; + return ret; +} + +static int rk29_backlight_pwm_suspend(void) +{ + int ret = 0; + return ret; +} + +static int rk29_backlight_pwm_resume(void) +{ + return 0; +} + +static struct rk29_bl_info rk29_bl_info = { + .pwm_id = PWM_ID, + .bl_ref = PWM_EFFECT_VALUE, + .io_init = rk29_backlight_io_init, + .io_deinit = rk29_backlight_io_deinit, + .pwm_suspend = rk29_backlight_pwm_suspend, + .pwm_resume = rk29_backlight_pwm_resume, +}; + +static struct platform_device rk29_device_backlight = { + .name = "rk29_backlight", + .id = -1, + .dev = { + .platform_data = &rk29_bl_info, + } +}; + +/*********************************************************** +* rk30 ion device +************************************************************/ +#define ION_RESERVE_SIZE (8 * SZ_1M) +static struct ion_platform_data rk30_ion_pdata = { + .nr = 1, + .heaps = { + { + .type = ION_HEAP_TYPE_CARVEOUT, + .id = ION_NOR_HEAP_ID, + .name = "norheap", + .size = ION_RESERVE_SIZE, + } + }, +}; + +static struct platform_device device_ion = { + .name = "ion-rockchip", + .id = 0, + .dev = { + .platform_data = &rk30_ion_pdata, + }, +}; + +static struct platform_device *devices[] __initdata = { +#ifdef CONFIG_FB_ROCKCHIP + &device_fb, +#endif +#if defined(CONFIG_LCDC0_RK3188) + &device_lcdc0, +#endif +#if defined(CONFIG_LCDC1_RK3188) + &device_lcdc1, +#endif + +#ifdef CONFIG_BACKLIGHT_RK29_BL + &rk29_device_backlight, +#endif + &device_ion, +}; + +static void __init fpga_board_init(void) +{ + rk30_i2c_register_board_info(); + spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices)); + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +static void __init fpga_reserve(void) +{ +#if defined(CONFIG_FB_ROCKCHIP) + resource_fb[0].start = board_mem_reserve_add("fb0", RK_FB_MEM_SIZE); + resource_fb[0].end = resource_fb[0].start + RK_FB_MEM_SIZE - 1; +#endif +#ifdef CONFIG_ION + rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE); +#endif +#ifdef CONFIG_VIDEO_RK29 + rk30_camera_request_reserve_mem(); +#endif + board_mem_reserved(); +} + +#include + +static struct rk29_keys_button key_button[] = { + { + .desc = "menu", + .code = EV_MENU, + .gpio = RK30_PIN3_PB2, + .active_low = PRESS_LEV_LOW, + }, + { + .desc = "vol+", + .code = KEY_VOLUMEUP, + .gpio = RK30_PIN3_PB1, + .active_low = PRESS_LEV_LOW, + }, + { + .desc = "vol-", + .code = KEY_VOLUMEDOWN, + .gpio = RK30_PIN3_PB0, + .active_low = PRESS_LEV_LOW, + }, + { + .desc = "home", + .code = KEY_HOME, + .gpio = RK30_PIN3_PB3, + .active_low = PRESS_LEV_LOW, + }, + { + .desc = "esc", + .code = KEY_BACK, + .gpio = RK30_PIN3_PB4, + .active_low = PRESS_LEV_LOW, + }, + { + .desc = "key6", + .code = KEY_CAMERA, + .gpio = RK30_PIN3_PB5, + .active_low = PRESS_LEV_LOW, + }, +}; + +struct rk29_keys_platform_data rk29_keys_pdata = { + .buttons = key_button, + .nbuttons = ARRAY_SIZE(key_button), + .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1 +}; + +static void __init fpga_fixup(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mi->nr_banks = 1; + mi->bank[0].start = PLAT_PHYS_OFFSET; + mi->bank[0].size = ddr_get_cap(); +} + +static void __init fpga_map_io(void) +{ + rk30_map_common_io(); + rk29_setup_early_printk(); + rk29_sram_init(); + board_clock_init(); +} + +static void __init fpga_init_irq(void) +{ + gic_init(0, IRQ_LOCALTIMER, GIC_DIST_BASE, GIC_CPU_BASE); +#ifdef CONFIG_FIQ + rk_fiq_init(); +#endif +} + +MACHINE_START(RK30, "RK30board") + .boot_params = PLAT_PHYS_OFFSET + 0x800, + .fixup = fpga_fixup, + .reserve = &fpga_reserve, + .map_io = fpga_map_io, + .init_irq = fpga_init_irq, + .timer = &rk30_timer, + .init_machine = fpga_board_init, +MACHINE_END + +#include +static void fpga_reset(char mode, const char *cmd) +{ + sram_printascii("\nfpga reset\n"); + while (1); +} +void (*arch_reset)(char, const char *) = fpga_reset; + +int ddr_init(uint32_t dram_type, uint32_t freq) +{ + return 0; +} + +uint32_t ddr_get_cap(void) +{ + return SZ_128M; +} + +struct cpufreq_frequency_table *dvfs_get_freq_volt_table(struct clk *clk) +{ + return NULL; +} + +#include + +struct clk { + const char *name; + unsigned long rate; +}; + +static struct clk xin24m = { + .name = "xin24m", + .rate = 24000000, +}; + +static struct clk xin12m = { + .name = "xin12m", + .rate = 12000000, +}; + +#define CLK(dev, con, ck) \ + { \ + .dev_id = dev, \ + .con_id = con, \ + .clk = ck, \ + } + +static struct clk_lookup clks[] = { + CLK("rk30_i2c.0", "i2c", &xin24m), + CLK("rk30_i2c.1", "i2c", &xin24m), + CLK("rk30_i2c.2", "i2c", &xin24m), + CLK("rk30_i2c.3", "i2c", &xin24m), + CLK("rk30_i2c.4", "i2c", &xin24m), + CLK("rk29xx_spim.0", "spi", &xin24m), + CLK("rk29xx_spim.1", "spi", &xin24m), + + CLK("rk_serial.0", "uart_div", &xin24m), + CLK("rk_serial.0", "uart_frac_div", &xin24m), + CLK("rk_serial.0", "uart", &xin24m), + CLK("rk_serial.0", "pclk_uart", &xin24m), + CLK("rk_serial.1", "uart_div", &xin24m), + CLK("rk_serial.1", "uart_frac_div", &xin24m), + CLK("rk_serial.1", "uart", &xin24m), + CLK("rk_serial.1", "pclk_uart", &xin24m), + CLK("rk_serial.2", "uart_div", &xin24m), + CLK("rk_serial.2", "uart_frac_div", &xin24m), + CLK("rk_serial.2", "uart", &xin24m), + CLK("rk_serial.2", "pclk_uart", &xin24m), + + CLK("rk29_i2s.1", "i2s_div", &xin24m), + CLK("rk29_i2s.1", "i2s_frac_div", &xin24m), + CLK("rk29_i2s.1", "i2s", &xin12m), + CLK("rk29_i2s.1", "hclk_i2s", &xin24m), + + CLK("rk29_sdmmc.0","mmc",&xin24m), + CLK("rk29_sdmmc.0","hclk_mmc",&xin24m), + CLK("rk29_sdmmc.1","mmc",&xin24m), + CLK("rk29_sdmmc.1","hclk_mmc",&xin24m), + + CLK(NULL,"pd_lcdc0",&xin24m), + CLK(NULL,"hclk_lcdc0",&xin24m), + CLK(NULL,"aclk_lcdc0",&xin24m), + CLK(NULL,"dclk_lcdc0",&xin24m), + CLK(NULL,"pd_lcdc1",&xin24m), + CLK(NULL,"hclk_lcdc1",&xin24m), + CLK(NULL,"aclk_lcdc1",&xin24m), + CLK(NULL,"dclk_lcdc1",&xin24m), + + CLK(NULL,"pd_cif0",&xin24m), + CLK(NULL,"aclk_cif0",&xin24m), + CLK(NULL,"hclk_cif0",&xin24m), + CLK(NULL,"cif0_in",&xin24m), + CLK(NULL,"cif0_out",&xin24m), + + CLK(NULL,"pwm01",&xin24m), +}; + +static void __init fpga_clock_init(void) +{ + struct clk_lookup *lk; + + for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) { + clkdev_add(lk); + } +} + +void __init board_clock_init(void) +{ + fpga_clock_init(); +} + +int __init clk_disable_unused(void) +{ + return 0; +} + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + if (clk) + return clk->rate; + else + return 24000000; +} +EXPORT_SYMBOL(clk_get_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + return 0; +} +EXPORT_SYMBOL(clk_set_rate); + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + return 0; +} +EXPORT_SYMBOL(clk_set_parent); + diff --git a/arch/arm/mach-rk319x/include/mach/board.h b/arch/arm/mach-rk319x/include/mach/board.h new file mode 100644 index 000000000000..1ec8d1c882b2 --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/board.h @@ -0,0 +1 @@ +#include <../../mach-rk3188/include/mach/board.h> diff --git a/arch/arm/mach-rk319x/include/mach/clkdev.h b/arch/arm/mach-rk319x/include/mach/clkdev.h new file mode 100644 index 000000000000..c0cf3286a662 --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/clkdev.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk319x/include/mach/clock.h b/arch/arm/mach-rk319x/include/mach/clock.h new file mode 100644 index 000000000000..94b35428fd3c --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/clock.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk319x/include/mach/cpu_axi.h b/arch/arm/mach-rk319x/include/mach/cpu_axi.h new file mode 100644 index 000000000000..c9977109fe62 --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/cpu_axi.h @@ -0,0 +1,8 @@ +#ifndef __MACH_CPU_AXI_H +#define __MACH_CPU_AXI_H + +#include + +#define CPU_AXI_BUS_BASE RK319X_CPU_AXI_BUS_BASE + +#endif diff --git a/arch/arm/mach-rk319x/include/mach/ddr.h b/arch/arm/mach-rk319x/include/mach/ddr.h new file mode 100644 index 000000000000..865e1f7d88a8 --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/ddr.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk319x/include/mach/debug-macro.S b/arch/arm/mach-rk319x/include/mach/debug-macro.S new file mode 100644 index 000000000000..00d5467951fe --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/debug-macro.S @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk319x/include/mach/debug_uart.h b/arch/arm/mach-rk319x/include/mach/debug_uart.h new file mode 100644 index 000000000000..82ac931c9c4e --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/debug_uart.h @@ -0,0 +1 @@ +#include <../../mach-rk30/include/mach/debug_uart.h> diff --git a/arch/arm/mach-rk319x/include/mach/dma-pl330.h b/arch/arm/mach-rk319x/include/mach/dma-pl330.h new file mode 100644 index 000000000000..9afde6529658 --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/dma-pl330.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk319x/include/mach/dvfs.h b/arch/arm/mach-rk319x/include/mach/dvfs.h new file mode 100644 index 000000000000..77d5949e6928 --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/dvfs.h @@ -0,0 +1,14 @@ +#ifndef RK_MACH_DVFS_H +#define RK_MACH_DVFS_H + +#include + +#ifdef CONFIG_DVFS +int rk3188_dvfs_init(void); +void dvfs_adjust_table_lmtvolt(struct clk *clk, struct cpufreq_frequency_table *table); +#else +static inline int rk3188_dvfs_init(void){ return 0; } +static inline void dvfs_adjust_table_lmtvolt(struct clk *clk, struct cpufreq_frequency_table *table){} +#endif + +#endif diff --git a/arch/arm/mach-rk319x/include/mach/entry-macro.S b/arch/arm/mach-rk319x/include/mach/entry-macro.S new file mode 100644 index 000000000000..d5136aa47385 --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/entry-macro.S @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk319x/include/mach/fiq.h b/arch/arm/mach-rk319x/include/mach/fiq.h new file mode 100644 index 000000000000..31e146e6f1f4 --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/fiq.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk319x/include/mach/gpio.h b/arch/arm/mach-rk319x/include/mach/gpio.h new file mode 100644 index 000000000000..27ba63d457c1 --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/gpio.h @@ -0,0 +1 @@ +#include <../../mach-rk30/include/mach/gpio.h> diff --git a/arch/arm/mach-rk319x/include/mach/grf.h b/arch/arm/mach-rk319x/include/mach/grf.h new file mode 100644 index 000000000000..86e4fd6581bb --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/grf.h @@ -0,0 +1,196 @@ +#ifndef __MACH_GRF_H +#define __MACH_GRF_H + +#include + +#define GRF_GPIO1A_IOMUX 0x0010 +#define GRF_GPIO1B_IOMUX 0x0014 +#define GRF_GPIO1C_IOMUX 0x0018 +#define GRF_GPIO1D_IOMUX 0x001c +#define GRF_GPIO2A_IOMUX 0x0020 +#define GRF_GPIO2B_IOMUX 0x0024 +#define GRF_GPIO2C_IOMUX 0x0028 +#define GRF_GPIO2D_IOMUX 0x002c +#define GRF_GPIO3A_IOMUX 0x0030 +#define GRF_GPIO3B_IOMUX 0x0034 +#define GRF_GPIO3C_IOMUX 0x0038 +#define GRF_GPIO3D_IOMUX 0x003c +#define GRF_GPIO4A_IOMUX 0x0040 +#define GRF_GPIO4B_IOMUX 0x0044 +#define GRF_GPIO4C_IOMUX 0x0048 +#define GRF_GPIO4D_IOMUX 0x004c + +#define GRF_SOC_CON0 0x0060 +#define GRF_SOC_CON1 0x0064 +#define GRF_SOC_CON2 0x0068 +#define GRF_SOC_CON3 0x006c +#define GRF_SOC_CON4 0x0070 +#define GRF_SOC_STATUS0 0x0074 +#define GRF_SOC_STATUS1 0x0078 +#define GRF_SOC_STATUS2 0x007c +#define GRF_DMAC1_CON0 0x0080 +#define GRF_DMAC1_CON1 0x0084 +#define GRF_DMAC1_CON2 0x0088 +#define GRF_DMAC2_CON0 0x008c +#define GRF_DMAC2_CON1 0x0090 +#define GRF_DMAC2_CON2 0x0094 +#define GRF_DMAC2_CON3 0x0098 +#define GRF_CPU_CON0 0x009c +#define GRF_CPU_CON1 0x00a0 +#define GRF_CPU_CON2 0x00a4 +#define GRF_CPU_CON3 0x00a8 +#define GRF_CPU_CON4 0x00ac +#define GRF_CPU_CON5 0x00b0 +#define GRF_CPU_STATUS0 0x00b4 +#define GRF_CPU_STATUS1 0x00b8 +#define GRF_DDRC_CON0 0x00bc +#define GRF_DDRC_STAT 0x00c0 +#define GRF_UOC0_CON0 0x00c4 +#define GRF_UOC0_CON1 0x00c8 +#define GRF_UOC0_CON2 0x00cc +#define GRF_UOC0_CON3 0x00d0 +#define GRF_UOC1_CON0 0x00d4 +#define GRF_UOC1_CON1 0x00d8 +#define GRF_UOC2_CON0 0x00e4 +#define GRF_UOC2_CON1 0x00e8 +#define GRF_UOC3_CON0 0x00ec +#define GRF_UOC3_CON1 0x00f0 +#define GRF_PVTM_CON0 0x00f4 +#define GRF_PVTM_CON1 0x00f8 +#define GRF_PVTM_CON2 0x00fc +#define GRF_PVTM_STATUS0 0x0100 +#define GRF_PVTM_STATUS1 0x0104 +#define GRF_PVTM_STATUS2 0x0108 + +#define GRF_NIF_FIFO0 0x0110 +#define GRF_NIF_FIFO1 0x0114 +#define GRF_NIF_FIFO2 0x0118 +#define GRF_NIF_FIFO3 0x011c +#define GRF_OS_REG0 0x0120 +#define GRF_OS_REG1 0x0124 +#define GRF_OS_REG2 0x0128 +#define GRF_OS_REG3 0x012c +#define GRF_SOC_CON5 0x0130 +#define GRF_SOC_CON6 0x0134 +#define GRF_SOC_CON7 0x0138 +#define GRF_SOC_CON8 0x013c + +#define GRF_GPIO1A_PULL 0x0144 +#define GRF_GPIO1B_PULL 0x0148 +#define GRF_GPIO1C_PULL 0x014c +#define GRF_GPIO1D_PULL 0x0150 +#define GRF_GPIO2A_PULL 0x0154 +#define GRF_GPIO2B_PULL 0x0158 +#define GRF_GPIO2C_PULL 0x015c +#define GRF_GPIO2D_PULL 0x0160 +#define GRF_GPIO3A_PULL 0x0164 +#define GRF_GPIO3B_PULL 0x0168 +#define GRF_GPIO3C_PULL 0x016c +#define GRF_GPIO3D_PULL 0x0170 +#define GRF_GPIO4A_PULL 0x0174 +#define GRF_GPIO4B_PULL 0x0178 +#define GRF_GPIO4C_PULL 0x017c +#define GRF_GPIO4D_PULL 0x0180 + +#define GRF_IO_VSEL 0x018c + +#define GRF_GPIO1L_SR 0x0198 +#define GRF_GPIO1H_SR 0x019c +#define GRF_GPIO2L_SR 0x01a0 +#define GRF_GPIO2H_SR 0x01a4 +#define GRF_GPIO3L_SR 0x01a8 +#define GRF_GPIO3H_SR 0x01ac +#define GRF_GPIO4L_SR 0x01b0 +#define GRF_GPIO4H_SR 0x01b4 + +#define GRF_GPIO1A_E 0x01c8 +#define GRF_GPIO1B_E 0x01cc +#define GRF_GPIO1C_E 0x01d0 +#define GRF_GPIO1D_E 0x01d4 +#define GRF_GPIO2A_E 0x01d8 +#define GRF_GPIO2B_E 0x01dc +#define GRF_GPIO2C_E 0x01e0 +#define GRF_GPIO2D_E 0x01e4 +#define GRF_GPIO3A_E 0x01e8 +#define GRF_GPIO3B_E 0x01ec +#define GRF_GPIO3C_E 0x01f0 +#define GRF_GPIO3D_E 0x01f4 +#define GRF_GPIO4A_E 0x01f8 +#define GRF_GPIO4B_E 0x01fc +#define GRF_GPIO4C_E 0x0200 +#define GRF_GPIO4D_E 0x0204 + +#define GRF_FLASH_DATA_PULL 0x0210 +#define GRF_FLASH_DATA_E 0x0214 +#define GRF_FLASH_DATA_SR 0x0218 + +#define GRF_USBPHY_CON0 0x0220 +#define GRF_USBPHY_CON1 0x0224 +#define GRF_USBPHY_CON2 0x0228 +#define GRF_USBPHY_CON3 0x022c +#define GRF_USBPHY_CON4 0x0230 +#define GRF_USBPHY_CON5 0x0234 +#define GRF_USBPHY_CON6 0x0238 +#define GRF_USBPHY_CON7 0x023c +#define GRF_USBPHY_CON8 0x0240 +#define GRF_USBPHY_CON9 0x0244 +#define GRF_USBPHY_CON10 0x0248 +#define GRF_USBPHY_CON11 0x024c +#define GRF_DFI_STAT0 0x0250 +#define GRF_DFI_STAT1 0x0254 +#define GRF_DFI_STAT2 0x0258 +#define GRF_DFI_STAT3 0x025c + +#define GRF_SECURE_BOOT_STATUS 0x0300 + +#define BB_GRF_GPIO0A_IOMUX 0x0000 +#define BB_GRF_GPIO0B_IOMUX 0x0004 +#define BB_GRF_GPIO0C_IOMUX 0x0008 +#define BB_GRF_GPIO0D_IOMUX 0x000c +#define BB_GRF_GPIO0A_DRV 0x0010 +#define BB_GRF_GPIO0B_DRV 0x0014 +#define BB_GRF_GPIO0C_DRV 0x0018 +#define BB_GRF_GPIO0D_DRV 0x001c +#define BB_GRF_GPIO0A_PULL 0x0020 +#define BB_GRF_GPIO0B_PULL 0x0024 +#define BB_GRF_GPIO0C_PULL 0x0028 +#define BB_GRF_GPIO0D_PULL 0x002c +#define BB_GRF_GPIO0L_SR 0x0030 +#define BB_GRF_GPIO0H_SR 0x0034 + +#define BB_GRF_GLB_CON0 0x0040 +#define BB_GRF_GLB_CON1 0x0044 +#define BB_GRF_GLB_CON2 0x0048 +#define BB_GRF_GLB_CON3 0x004c +#define BB_GRF_GLB_CON4 0x0050 + +#define BB_GRF_GLB_STS0 0x0060 + +enum grf_io_power_domain_voltage { + IO_PD_VOLTAGE_3_3V = 0, + IO_PD_VOLTAGE_2_5V = IO_PD_VOLTAGE_3_3V, + IO_PD_VOLTAGE_1_8V = 1, +}; + +enum grf_io_power_domain { + IO_PD_LCDC = 0, + IO_PD_CIF, + IO_PD_FLASH, + IO_PD_WIFI_BT, + IO_PD_AUDIO, + IO_PD_GPIO0, + IO_PD_GPIO1, +}; + +static inline void grf_set_io_power_domain_voltage(enum grf_io_power_domain pd, enum grf_io_power_domain_voltage volt) +{ + writel_relaxed((0x10000 + volt) << pd, RK30_GRF_BASE + GRF_IO_VSEL); + dsb(); +} + +static inline enum grf_io_power_domain_voltage grf_get_io_power_domain_voltage(enum grf_io_power_domain pd) +{ + return (readl_relaxed(RK30_GRF_BASE + GRF_IO_VSEL) >> pd) & 1; +} + +#endif diff --git a/arch/arm/mach-rk319x/include/mach/hardware.h b/arch/arm/mach-rk319x/include/mach/hardware.h new file mode 100644 index 000000000000..9e84f2395d97 --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/hardware.h @@ -0,0 +1,4 @@ +#ifndef __MACH_HARDWARE_H +#define __MACH_HARDWARE_H + +#endif diff --git a/arch/arm/mach-rk319x/include/mach/io.h b/arch/arm/mach-rk319x/include/mach/io.h new file mode 100644 index 000000000000..2394749e2578 --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/io.h @@ -0,0 +1,393 @@ +#ifndef __MACH_IO_H +#define __MACH_IO_H + +#include + +/* + * RK319X IO memory map: + * + * Virt Phys Size What + * --------------------------------------------------------------------------- + * FDFF0000 + * FE900000 FE600000 1M BB + * FEA00000 FFA00000 1M + * FFB00000 1M Peri AXI BUS + * FEB00000 FFC00000 4M + * FEC00000 FFD00000 + * FED00000 FFE00000 + * FEE00000 FFF00000 + * FEF00000 FFCD0000 32K SRAM + */ + +#define RK319X_IO_TO_VIRT0(pa) IOMEM((pa) - 0xFE600000 + 0xFE900000) +#define RK319X_IO_TO_VIRT1(pa) IOMEM((pa) - 0xFFA00000 + 0xFEA00000) +#define RK319X_IO_TO_VIRT2(pa) IOMEM((pa) - 0xFFC00000 + 0xFEB00000) + +#define IO_ADDRESS(pa) IOMEM( \ + ((pa) >= 0xFE600000 && (pa) < 0xFE700000) ? RK319X_IO_TO_VIRT0(pa) : \ + ((pa) >= 0xFFA00000 && (pa) < 0xFFB00000) ? RK319X_IO_TO_VIRT1(pa) : \ + ((pa) >= 0xFFC00000 && (pa) <= 0xFFFFFFFF) ? RK319X_IO_TO_VIRT2(pa) : \ + 0) + +#define RK319X_BOOT_RAM_PHYS 0xFDFF0000 +#define RK319X_BOOT_RAM_SIZE SZ_4K + +#define RK319X_PMU_PHYS 0xFE600000 +#define RK319X_PMU_BASE IO_ADDRESS(RK319X_PMU_PHYS) +#define RK319X_PMU_SIZE SZ_64K + +#define RK319X_BB_GRF_PHYS 0xFE620000 +#define RK319X_BB_GRF_BASE IO_ADDRESS(RK319X_BB_GRF_PHYS) +#define RK319X_BB_GRF_SIZE SZ_64K + +#define RK319X_MAILBOX_PHYS 0xFE650000 +#define RK319X_MAILBOX_SIZE SZ_64K + +#define RK319X_GPIO0_PHYS 0xFE680000 +#define RK319X_GPIO0_BASE IO_ADDRESS(RK319X_GPIO0_PHYS) +#define RK319X_GPIO0_SIZE SZ_8K + +#define RK319X_SMC_BANK0_PHYS 0xFE800000 +#define RK319X_SMC_BANK0_SIZE SZ_8M +#define RK319X_SMC_BANK1_PHYS 0xFF000000 +#define RK319X_SMC_BANK1_SIZE SZ_8M +#define RK319X_USBOTG20_PHYS 0xFF800000 +#define RK319X_USBOTG20_SIZE SZ_256K +#define RK319X_USBHOST20_PHYS 0xFF840000 +#define RK319X_USBHOST20_SIZE SZ_256K +#define RK319X_HSIC_PHYS 0xFF880000 +#define RK319X_HSIC_SIZE SZ_256K +#define RK319X_NANDC_PHYS 0xFF8C0000 +#define RK319X_NANDC_SIZE SZ_32K +#define RK319X_CRYPTO_PHYS 0xFF8C8000 +#define RK319X_CRYPTO_SIZE SZ_32K + +#define RK319X_EMMC_PHYS 0xFF900000 +#define RK319X_EMMC_SIZE SZ_64K +#define RK319X_SDIO_PHYS 0xFF910000 +#define RK319X_SDIO_SIZE SZ_64K +#define RK319X_SDMMC0_PHYS 0xFF920000 +#define RK319X_SDMMC0_SIZE SZ_64K + +#define RK319X_HSADC_PHYS 0xFF980000 +#define RK319X_HSADC_SIZE SZ_64K +#define RK319X_GPS_PHYS 0xFF990000 +#define RK319X_GPS_SIZE SZ_64K + +#define RK319X_SARADC_PHYS 0xFFA00000 +#define RK319X_SARADC_SIZE SZ_64K + +#define RK319X_SPI0_PHYS 0xFFA10000 +#define RK319X_SPI0_SIZE SZ_64K +#define RK319X_SPI1_PHYS 0xFFA20000 +#define RK319X_SPI1_SIZE SZ_64K +#define RK319X_I2C2_PHYS 0xFFA30000 +#define RK319X_I2C2_SIZE SZ_64K +#define RK319X_I2C3_PHYS 0xFFA40000 +#define RK319X_I2C3_SIZE SZ_64K +#define RK319X_I2C4_PHYS 0xFFA50000 +#define RK319X_I2C4_SIZE SZ_64K +#define RK319X_UART0_PHYS 0xFFA60000 +#define RK319X_UART0_BASE RK319X_IO_TO_VIRT1(RK319X_UART0_PHYS) +#define RK319X_UART0_SIZE SZ_64K +#define RK319X_UART1_PHYS 0xFFA70000 +#define RK319X_UART1_BASE RK319X_IO_TO_VIRT1(RK319X_UART1_PHYS) +#define RK319X_UART1_SIZE SZ_64K +#define RK319X_UART2_PHYS 0xFFA80000 +#define RK319X_UART2_BASE RK319X_IO_TO_VIRT1(RK319X_UART2_PHYS) +#define RK319X_UART2_SIZE SZ_64K +#define RK319X_UART3_PHYS 0xFFA90000 +#define RK319X_UART3_BASE RK319X_IO_TO_VIRT1(RK319X_UART3_PHYS) +#define RK319X_UART3_SIZE SZ_64K +#define RK319X_WDT_PHYS 0xFFAA0000 +#define RK319X_WDT_SIZE SZ_64K + +#define RK319X_DMAC2_PHYS 0xFFAD0000 +#define RK319X_DMAC2_SIZE SZ_64K +#define RK319X_SMC_PHYS 0xFFAE0000 +#define RK319X_SMC_SIZE SZ_64K +#define RK319X_TSADC_PHYS 0xFFAF0000 +#define RK319X_TSADC_SIZE SZ_64K +#define RK319X_PERI_AXI_BUS_PHYS 0xFFB00000 +#define RK319X_PERI_AXI_BUS_SIZE SZ_1M +#define RK319X_ROM_PHYS 0xFFC00000 +#define RK319X_ROM_BASE IO_ADDRESS(RK319X_ROM_PHYS) +#define RK319X_ROM_SIZE SZ_64K +#define RK319X_I2S1_2CH_PHYS 0xFFC10000 +#define RK319X_I2S1_2CH_SIZE SZ_64K +#define RK319X_SPDIF_PHYS 0xFFC20000 +#define RK319X_SPDIF_SIZE SZ_64K + +#define RK319X_LCDC0_PHYS 0xFFC40000 +#define RK319X_LCDC0_SIZE SZ_64K +#define RK319X_LCDC1_PHYS 0xFFC50000 +#define RK319X_LCDC1_SIZE SZ_64K +#define RK319X_CIF0_PHYS 0xFFC60000 +#define RK319X_CIF0_SIZE SZ_64K +#define RK319X_RGA_PHYS 0xFFC70000 +#define RK319X_RGA_SIZE SZ_64K +#define RK319X_IEP_PHYS 0xFFC80000 +#define RK319X_IEP_SIZE SZ_64K +#define RK319X_MIPI_DSI_HOST_PHYS 0xFFC90000 +#define RK319X_MIPI_DSI_HOST_SIZE SZ_64K +#define RK319X_ISP_PHYS 0xFFCA0000 +#define RK319X_ISP_SIZE SZ_64K +#define RK319X_VCODEC_PHYS 0xFFCB0000 +#define RK319X_VCODEC_SIZE SZ_64K +#define RK319X_CPU_AXI_BUS_PHYS 0xFFCC0000 +#define RK319X_CPU_AXI_BUS_BASE IO_ADDRESS(RK319X_CPU_AXI_BUS_PHYS) +#define RK319X_CPU_AXI_BUS_SIZE SZ_64K +#define RK319X_IMEM_PHYS 0xFFCD0000 +#define RK319X_IMEM_BASE IOMEM(0xFEF00000) +#define RK319X_IMEM_NONCACHED IO_ADDRESS(RK319X_IMEM_PHYS) +#define RK319X_IMEM_SIZE SZ_32K + +#define RK319X_GPU_PHYS 0xFFD00000 +#define RK319X_GPU_SIZE SZ_64K + +#define RK319X_TZPC_PHYS 0xFFD20000 +#define RK319X_TZPC_SIZE SZ_64K +#define RK319X_EFUSE_PHYS 0xFFD30000 +#define RK319X_EFUSE_BASE IO_ADDRESS(RK319X_EFUSE_PHYS) +#define RK319X_EFUSE_SIZE SZ_64K +#define RK319X_DMACS1_PHYS 0xFFD40000 +#define RK319X_DMACS1_SIZE SZ_64K + +#define RK319X_PWM_PHYS 0xFFD60000 +#define RK319X_PWM_BASE IO_ADDRESS(RK319X_PWM_PHYS) +#define RK319X_PWM_SIZE SZ_64K + +#define RK319X_I2C0_PHYS 0xFFD80000 +#define RK319X_I2C0_SIZE SZ_64K +#define RK319X_I2C1_PHYS 0xFFD90000 +#define RK319X_I2C1_BASE IO_ADDRESS(RK319X_I2C1_PHYS) +#define RK319X_I2C1_SIZE SZ_64K +#define RK319X_DMAC1_PHYS 0xFFDA0000 +#define RK319X_DMAC1_SIZE SZ_64K +#define RK319X_DDR_PCTL_PHYS 0xFFDB0000 +#define RK319X_DDR_PCTL_BASE IO_ADDRESS(RK319X_DDR_PCTL_PHYS) +#define RK319X_DDR_PCTL_SIZE SZ_64K +#define RK319X_DDR_PUBL_PHYS 0xFFDC0000 +#define RK319X_DDR_PUBL_BASE IO_ADDRESS(RK319X_DDR_PUBL_PHYS) +#define RK319X_DDR_PUBL_SIZE SZ_64K + +#define RK319X_CPU_DEBUG_PHYS 0xFFDE0000 +#define RK319X_CPU_DEBUG_SIZE SZ_128K +#define RK319X_CRU_PHYS 0xFFE00000 +#define RK319X_CRU_BASE IO_ADDRESS(RK319X_CRU_PHYS) +#define RK319X_CRU_SIZE SZ_64K +#define RK319X_GRF_PHYS 0xFFE10000 +#define RK319X_GRF_BASE IO_ADDRESS(RK319X_GRF_PHYS) +#define RK319X_GRF_SIZE SZ_64K +#define RK319X_TIMER_PHYS 0xFFE20000 +#define RK319X_TIMER_BASE IO_ADDRESS(RK319X_TIMER_PHYS) +#define RK319X_TIMER_SIZE SZ_64K +#define RK319X_ACODEC_PHYS 0xFFE30000 +#define RK319X_ACODEC_SIZE SZ_16K +#define RK319X_HDMI_PHYS 0xFFE34000 +#define RK319X_HDMI_SIZE SZ_16K +#define RK319X_MIPI_DSI_PHY_PHYS 0xFFE38000 +#define RK319X_MIPI_DSI_PHY_SIZE SZ_16K + +#define RK319X_GPIO1_PHYS 0xFFE40000 +#define RK319X_GPIO1_BASE IO_ADDRESS(RK319X_GPIO1_PHYS) +#define RK319X_GPIO1_SIZE SZ_64K +#define RK319X_GPIO2_PHYS 0xFFE50000 +#define RK319X_GPIO2_BASE IO_ADDRESS(RK319X_GPIO2_PHYS) +#define RK319X_GPIO2_SIZE SZ_64K +#define RK319X_GPIO3_PHYS 0xFFE60000 +#define RK319X_GPIO3_BASE IO_ADDRESS(RK319X_GPIO3_PHYS) +#define RK319X_GPIO3_SIZE SZ_64K +#define RK319X_GPIO4_PHYS 0xFFE70000 +#define RK319X_GPIO4_BASE IO_ADDRESS(RK319X_GPIO4_PHYS) +#define RK319X_GPIO4_SIZE SZ_64K + +#define RK319X_L2C_PHYS 0xFFF00000 +#define RK319X_L2C_BASE IO_ADDRESS(RK319X_L2C_PHYS) +#define RK319X_L2C_SIZE SZ_16K +#define RK319X_SCU_PHYS 0xFFF04000 +#define RK319X_SCU_BASE IO_ADDRESS(RK319X_SCU_PHYS) +#define RK319X_SCU_SIZE SZ_256 +#define RK319X_GICC_PHYS 0xFFF04100 +#define RK319X_GICC_BASE RK319X_IO_TO_VIRT2(RK319X_GICC_PHYS) +#define RK319X_GICC_SIZE SZ_256 +#define RK319X_GTIMER_PHYS 0xFFF04200 +#define RK319X_GTIMER_BASE IO_ADDRESS(RK319X_GTIMER_PHYS) +#define RK319X_GTIMER_SIZE SZ_1K +#define RK319X_PTIMER_PHYS 0xFFF04600 +#define RK319X_PTIMER_BASE IO_ADDRESS(RK319X_PTIMER_PHYS) +#define RK319X_PTIMER_SIZE (SZ_2K + SZ_512) +#define RK319X_GICD_PHYS 0xFFF05000 +#define RK319X_GICD_BASE IO_ADDRESS(RK319X_GICD_PHYS) +#define RK319X_GICD_SIZE SZ_2K + +#define RK319X_BOOT_PHYS 0xFFFF0000 +#define RK319X_BOOT_BASE IO_ADDRESS(RK319X_BOOT_PHYS) + +#define RK319X_CORE_PHYS RK319X_L2C_PHYS +#define RK319X_CORE_BASE RK319X_L2C_BASE +#define RK319X_CORE_SIZE (RK319X_L2C_SIZE + SZ_8K) +#define GIC_DIST_BASE RK319X_GICD_BASE +#define GIC_CPU_BASE RK319X_GICC_BASE +#define SRAM_NONCACHED RK319X_IMEM_NONCACHED +#define SRAM_CACHED RK319X_IMEM_BASE +#define SRAM_PHYS RK319X_IMEM_PHYS +#define SRAM_SIZE RK319X_IMEM_SIZE + +#define RK30_PMU_PHYS RK319X_PMU_PHYS +#define RK30_PMU_BASE RK319X_PMU_BASE +#define RK30_PMU_SIZE RK319X_PMU_SIZE +#define RK30_GPIO0_PHYS RK319X_GPIO0_PHYS +#define RK30_GPIO0_BASE RK319X_GPIO0_BASE +#define RK30_GPIO0_SIZE RK319X_GPIO0_SIZE +#define RK30_GPIO1_PHYS RK319X_GPIO1_PHYS +#define RK30_GPIO1_BASE RK319X_GPIO1_BASE +#define RK30_GPIO1_SIZE RK319X_GPIO1_SIZE +#define RK30_GPIO2_PHYS RK319X_GPIO2_PHYS +#define RK30_GPIO2_BASE RK319X_GPIO2_BASE +#define RK30_GPIO2_SIZE RK319X_GPIO2_SIZE +#define RK30_GPIO3_PHYS RK319X_GPIO3_PHYS +#define RK30_GPIO3_BASE RK319X_GPIO3_BASE +#define RK30_GPIO3_SIZE RK319X_GPIO3_SIZE +#define RK30_GPIO4_PHYS RK319X_GPIO4_PHYS +#define RK30_GPIO4_BASE RK319X_GPIO4_BASE +#define RK30_GPIO4_SIZE RK319X_GPIO4_SIZE +#define RK30_SMC_BANK0_PHYS RK319X_SMC_BANK0_PHYS +#define RK30_SMC_BANK0_SIZE RK319X_SMC_BANK0_SIZE +#define RK30_SMC_BANK1_PHYS RK319X_SMC_BANK1_PHYS +#define RK30_SMC_BANK1_SIZE RK319X_SMC_BANK1_SIZE +#define RK30_USBOTG20_PHYS RK319X_USBOTG20_PHYS +#define RK30_USBOTG20_SIZE RK319X_USBOTG20_SIZE +#define RK30_USBHOST20_PHYS RK319X_USBHOST20_PHYS +#define RK30_USBHOST20_SIZE RK319X_USBHOST20_SIZE +#define RK30_HSIC_PHYS RK319X_HSIC_PHYS +#define RK30_HSIC_SIZE RK319X_HSIC_SIZE +#define RK30_NANDC_PHYS RK319X_NANDC_PHYS +#define RK30_NANDC_SIZE RK319X_NANDC_SIZE +#define RK30_EMMC_PHYS RK319X_EMMC_PHYS +#define RK30_EMMC_SIZE RK319X_EMMC_SIZE +#define RK30_SDIO_PHYS RK319X_SDIO_PHYS +#define RK30_SDIO_SIZE RK319X_SDIO_SIZE +#define RK30_SDMMC0_PHYS RK319X_SDMMC0_PHYS +#define RK30_SDMMC0_SIZE RK319X_SDMMC0_SIZE +#define RK30_HSADC_PHYS RK319X_HSADC_PHYS +#define RK30_HSADC_SIZE RK319X_HSADC_SIZE +#define RK30_GPS_PHYS RK319X_GPS_PHYS +#define RK30_GPS_SIZE RK319X_GPS_SIZE +#define RK30_SARADC_PHYS RK319X_SARADC_PHYS +#define RK30_SARADC_SIZE RK319X_SARADC_SIZE +#define RK30_SPI0_PHYS RK319X_SPI0_PHYS +#define RK30_SPI0_SIZE RK319X_SPI0_SIZE +#define RK30_SPI1_PHYS RK319X_SPI1_PHYS +#define RK30_SPI1_SIZE RK319X_SPI1_SIZE +#define RK30_I2C0_PHYS RK319X_I2C0_PHYS +#define RK30_I2C0_SIZE RK319X_I2C0_SIZE +#define RK30_I2C1_PHYS RK319X_I2C1_PHYS +#define RK30_I2C1_BASE RK319X_I2C1_BASE +#define RK30_I2C1_SIZE RK319X_I2C1_SIZE +#define RK30_I2C2_PHYS RK319X_I2C2_PHYS +#define RK30_I2C2_SIZE RK319X_I2C2_SIZE +#define RK30_I2C3_PHYS RK319X_I2C3_PHYS +#define RK30_I2C3_SIZE RK319X_I2C3_SIZE +#define RK30_I2C4_PHYS RK319X_I2C4_PHYS +#define RK30_I2C4_SIZE RK319X_I2C4_SIZE +#define RK30_UART0_PHYS RK319X_UART0_PHYS +#define RK30_UART0_BASE RK319X_UART0_BASE +#define RK30_UART0_SIZE RK319X_UART0_SIZE +#define RK30_UART1_PHYS RK319X_UART1_PHYS +#define RK30_UART1_BASE RK319X_UART1_BASE +#define RK30_UART1_SIZE RK319X_UART1_SIZE +#define RK30_UART2_PHYS RK319X_UART2_PHYS +#define RK30_UART2_BASE RK319X_UART2_BASE +#define RK30_UART2_SIZE RK319X_UART2_SIZE +#define RK30_UART3_PHYS RK319X_UART3_PHYS +#define RK30_UART3_BASE RK319X_UART3_BASE +#define RK30_UART3_SIZE RK319X_UART3_SIZE +#define RK30_WDT_PHYS RK319X_WDT_PHYS +#define RK30_WDT_SIZE RK319X_WDT_SIZE +#define RK30_DMAC2_PHYS RK319X_DMAC2_PHYS +#define RK30_DMAC2_SIZE RK319X_DMAC2_SIZE +#define RK30_SMC_PHYS RK319X_SMC_PHYS +#define RK30_SMC_SIZE RK319X_SMC_SIZE +#define RK30_TSADC_PHYS RK319X_TSADC_PHYS +#define RK30_TSADC_SIZE RK319X_TSADC_SIZE +#define RK30_PERI_AXI_BUS_PHYS RK319X_PERI_AXI_BUS_PHYS +#define RK30_PERI_AXI_BUS_SIZE RK319X_PERI_AXI_BUS_SIZE +#define RK30_ROM_PHYS RK319X_ROM_PHYS +#define RK30_ROM_BASE RK319X_ROM_BASE +#define RK30_ROM_SIZE RK319X_ROM_SIZE +#define RK30_I2S1_2CH_PHYS RK319X_I2S1_2CH_PHYS +#define RK30_I2S1_2CH_SIZE RK319X_I2S1_2CH_SIZE +#define RK30_SPDIF_PHYS RK319X_SPDIF_PHYS +#define RK30_SPDIF_SIZE RK319X_SPDIF_SIZE +#define RK30_LCDC0_PHYS RK319X_LCDC0_PHYS +#define RK30_LCDC0_SIZE RK319X_LCDC0_SIZE +#define RK30_LCDC1_PHYS RK319X_LCDC1_PHYS +#define RK30_LCDC1_SIZE RK319X_LCDC1_SIZE +#define RK30_CIF0_PHYS RK319X_CIF0_PHYS +#define RK30_CIF0_SIZE RK319X_CIF0_SIZE +#define RK30_RGA_PHYS RK319X_RGA_PHYS +#define RK30_RGA_SIZE RK319X_RGA_SIZE +#define RK30_VCODEC_PHYS RK319X_VCODEC_PHYS +#define RK30_VCODEC_SIZE RK319X_VCODEC_SIZE +#define RK30_CPU_AXI_BUS_PHYS RK319X_CPU_AXI_BUS_PHYS +#define RK30_CPU_AXI_BUS_BASE RK319X_CPU_AXI_BUS_BASE +#define RK30_CPU_AXI_BUS_SIZE RK319X_CPU_AXI_BUS_SIZE +#define RK30_IMEM_PHYS RK319X_IMEM_PHYS +#define RK30_IMEM_BASE RK319X_IMEM_BASE +#define RK30_IMEM_NONCACHED RK319X_IMEM_NONCACHED +#define RK30_IMEM_SIZE RK319X_IMEM_SIZE +#define RK3188_IMEM_SIZE RK319X_IMEM_SIZE +#define RK30_GPU_PHYS RK319X_GPU_PHYS +#define RK30_GPU_SIZE RK319X_GPU_SIZE +#define RK30_TZPC_PHYS RK319X_TZPC_PHYS +#define RK30_TZPC_SIZE RK319X_TZPC_SIZE +#define RK30_EFUSE_PHYS RK319X_EFUSE_PHYS +#define RK30_EFUSE_BASE RK319X_EFUSE_BASE +#define RK30_EFUSE_SIZE RK319X_EFUSE_SIZE +#define RK30_DMACS1_PHYS RK319X_DMACS1_PHYS +#define RK30_DMACS1_SIZE RK319X_DMACS1_SIZE +#define RK30_PWM_PHYS RK319X_PWM_PHYS +#define RK30_PWM_BASE RK319X_PWM_BASE +#define RK30_PWM_SIZE RK319X_PWM_SIZE +#define RK30_DMAC1_PHYS RK319X_DMAC1_PHYS +#define RK30_DMAC1_SIZE RK319X_DMAC1_SIZE +#define RK30_DDR_PCTL_PHYS RK319X_DDR_PCTL_PHYS +#define RK30_DDR_PCTL_BASE RK319X_DDR_PCTL_BASE +#define RK30_DDR_PCTL_SIZE RK319X_DDR_PCTL_SIZE +#define RK30_DDR_PUBL_PHYS RK319X_DDR_PUBL_PHYS +#define RK30_DDR_PUBL_BASE RK319X_DDR_PUBL_BASE +#define RK30_DDR_PUBL_SIZE RK319X_DDR_PUBL_SIZE +#define RK30_CPU_DEBUG_PHYS RK319X_CPU_DEBUG_PHYS +#define RK30_CPU_DEBUG_SIZE RK319X_CPU_DEBUG_SIZE +#define RK30_CRU_PHYS RK319X_CRU_PHYS +#define RK30_CRU_BASE RK319X_CRU_BASE +#define RK30_CRU_SIZE RK319X_CRU_SIZE +#define RK30_GRF_PHYS RK319X_GRF_PHYS +#define RK30_GRF_BASE RK319X_GRF_BASE +#define RK30_GRF_SIZE RK319X_GRF_SIZE +#define RK30_HDMI_PHYS RK319X_HDMI_PHYS +#define RK30_HDMI_SIZE RK319X_HDMI_SIZE +#define RK30_L2C_PHYS RK319X_L2C_PHYS +#define RK30_L2C_BASE RK319X_L2C_BASE +#define RK30_L2C_SIZE RK319X_L2C_SIZE +#define RK30_SCU_PHYS RK319X_SCU_PHYS +#define RK30_SCU_BASE RK319X_SCU_BASE +#define RK30_SCU_SIZE RK319X_SCU_SIZE +#define RK30_GICC_PHYS RK319X_GICC_PHYS +#define RK30_GICC_BASE RK319X_GICC_BASE +#define RK30_GICC_SIZE RK319X_GICC_SIZE +#define RK30_GTIMER_PHYS RK319X_GTIMER_PHYS +#define RK30_GTIMER_BASE RK319X_GTIMER_BASE +#define RK30_GTIMER_SIZE RK319X_GTIMER_SIZE +#define RK30_PTIMER_PHYS RK319X_PTIMER_PHYS +#define RK30_PTIMER_BASE RK319X_PTIMER_BASE +#define RK30_PTIMER_SIZE RK319X_PTIMER_SIZE +#define RK30_GICD_PHYS RK319X_GICD_PHYS +#define RK30_GICD_BASE RK319X_GICD_BASE +#define RK30_GICD_SIZE RK319X_GICD_SIZE +#define RK30_CORE_PHYS RK319X_CORE_PHYS +#define RK30_CORE_BASE RK319X_CORE_BASE +#define RK30_CORE_SIZE RK319X_CORE_SIZE + +#endif diff --git a/arch/arm/mach-rk319x/include/mach/iomux.h b/arch/arm/mach-rk319x/include/mach/iomux.h new file mode 100644 index 000000000000..5d322006a09f --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/iomux.h @@ -0,0 +1,202 @@ +#ifndef __MACH_IOMUX_H +#define __MACH_IOMUX_H + +#include +#include +#include + +#define GRF_IOMUX_BASE RK319X_GRF_BASE + +enum{ + /* GPIO0_A */ + GPIO0_A0 = 0x0a00, TSADC_TSHUT, + GPIO0_A5 = 0x0a50, BB_TCO4, SIM0_DET, + GPIO0_A7 = 0x0a70, PMU_SLEEP, + + /* GPIO0_B */ + GPIO0_B0 = 0x0b00, I2C4_SDA_T0, SIM1_DET, + GPIO0_B1 = 0x0b10, I2C4_SCL_T0, /*BB_TCO4,*/ + GPIO0_B3 = 0x0b30, BB_TCO5 = GPIO0_B3 + 2, + GPIO0_B4 = 0x0b40, BB_TCO6 = GPIO0_B4 + 2, SIM1_VCCSEL, + GPIO0_B5 = 0x0b50, I2C0_SDA, + GPIO0_B6 = 0x0b60, I2C0_SCL, + GPIO0_B7 = 0x0b70, TEST_CLK_OUT, BB_TCO7, SIM0_VCCSEL, + + /* GPIO0_C */ + GPIO0_C2 = 0x0c20, SIM0_CLK, + GPIO0_C3 = 0x0c30, SIM0_RSTN, + GPIO0_C4 = 0x0c40, SIM0_DATA, + GPIO0_C5 = 0x0c50, SIM1_CLK, BB_LPC0, BB_TCO0, + GPIO0_C6 = 0x0c60, SIM1_RSTN, BB_LPC1, BB_TCO1, + GPIO0_C7 = 0x0c70, SIM1_DATA, BB_LPC2, BB_TCO2, + + /* GPIO0_D */ + GPIO0_D0 = 0x0d00, RF_XCV_PDN, SPI0_RXD, UART1_SIN, + GPIO0_D1 = 0x0d10, RF_XON, SPI0_TXD, UART1_SOUT, + GPIO0_D2 = 0x0d20, RF_DATAEN, SPI0_CLK, UART1_CTSN, + GPIO0_D3 = 0x0d30, RF_DATA, SPI0_CS0, UART1_RTSN, + GPIO0_D4 = 0x0d40, RF_CTRLDATA, SPI0_CS1, + GPIO0_D5 = 0x0d50, RF_CTRLEN, + GPIO0_D6 = 0x0d60, RF_CTRLCLK, + GPIO0_D7 = 0x0d70, RF_STROBE, + + /* GPIO1_A */ + GPIO1_A0 = 0x1a00, LCDC_DCLK, SMC_D0, + GPIO1_A1 = 0x1a10, LCDC_VSYNC, SMC_D1, + GPIO1_A2 = 0x1a20, LCDC_HSYNC, SMC_D2, + GPIO1_A3 = 0x1a30, LCDC_DEN, SMC_D3, + GPIO1_A4 = 0x1a40, LCDC_D0, SMC_D4, ARM9_JTAG_TCK, + GPIO1_A5 = 0x1a50, LCDC_D1, SMC_D5, ARM9_JTAG_TRSTN, + GPIO1_A6 = 0x1a60, LCDC_D2, SMC_D6, ARM9_JTAG_TMS, + GPIO1_A7 = 0x1a70, LCDC_D3, SMC_D7, ARM9_JTAG_TDO, + + /* GPIO1_B */ + GPIO1_B0 = 0x1b00, LCDC_D4, SMC_R0, ARM9_JTAG_TDI, + GPIO1_B1 = 0x1b10, LCDC_D5, SMC_R1, ARM9_JTAG_SEL, + GPIO1_B2 = 0x1b20, LCDC_D6, SMC_R2, CEVA_JTAG_TCK, + GPIO1_B3 = 0x1b30, LCDC_D7, SMC_R3, CEVA_JTAG_TRSTN, + GPIO1_B4 = 0x1b40, LCDC_D8, SMC_R4, CEVA_JTAG_TMS, + GPIO1_B5 = 0x1b50, LCDC_D9, SMC_R5, CEVA_JTAG_TDO, + GPIO1_B6 = 0x1b60, LCDC_D10, SMC_R6, CEVA_JTAG_TDI, + GPIO1_B7 = 0x1b70, LCDC_D11, SMC_R7, CEVA_JTAG_SEL, + + /* GPIO1_C */ + GPIO1_C0 = 0x1c00, LCDC_D12, SMC_CS0, + GPIO1_C1 = 0x1c10, LCDC_D13, SMC_WEN, + GPIO1_C2 = 0x1c20, LCDC_D14, SMC_OEN, + GPIO1_C3 = 0x1c30, LCDC_D15, SMC_ADVN, + GPIO1_C4 = 0x1c40, LCDC_D16, SMC_BLSN0, + GPIO1_C5 = 0x1c50, LCDC_D17, SMC_BLSN1, + GPIO1_C6 = 0x1c60, LCDC_D18, SMC_CS1, + GPIO1_C7 = 0x1c70, LCDC_D19, + + /* GPIO1_D */ + GPIO1_D0 = 0x1d00, LCDC_D20, UART3_CTSN, I2S2_SCLK_T0, + GPIO1_D1 = 0x1d10, LCDC_D21, UART3_RTSN, I2S2_LRCK_T0, + GPIO1_D2 = 0x1d20, LCDC_D22, UART3_SIN, I2S2_SDI_T0, + GPIO1_D3 = 0x1d30, LCDC_D23, UART3_SOUT, I2S2_SDO_T0, + GPIO1_D4 = 0x1d40, CIF0_D0, I2C3_SCL, HDMI_DDC_SCL, + GPIO1_D5 = 0x1d50, CIF0_D1, I2C3_SDA, HDMI_DDC_SDA, + GPIO1_D6 = 0x1d60, CIF0_D10, + GPIO1_D7 = 0x1d70, CIF0_D11, + + /* GPIO2_A */ + GPIO2_A0 = 0x2a00, CIF0_D2, HSADC_D0, BB_DEBUG0, + GPIO2_A1 = 0x2a10, CIF0_D3, HSADC_D1, BB_DEBUG1, + GPIO2_A2 = 0x2a20, CIF0_D4, HSADC_D2, BB_DEBUG2, + GPIO2_A3 = 0x2a30, CIF0_D5, HSADC_D3, BB_DEBUG3, + GPIO2_A4 = 0x2a40, CIF0_D6, HSADC_D4, BB_DEBUG4, + GPIO2_A5 = 0x2a50, CIF0_D7, HSADC_D5, BB_DEBUG5, + GPIO2_A6 = 0x2a60, CIF0_D8, HSADC_D6, BB_DEBUG6, + GPIO2_A7 = 0x2a70, CIF0_D9, HSADC_D7, BB_DEBUG7, + + /* GPIO2_B */ + GPIO2_B0 = 0x2b00, CIF0_CLKOUT, HSADC_CLKIN, HSADC_CLKOUT, + GPIO2_B1 = 0x2b10, CIF0_VSYNC, + GPIO2_B2 = 0x2b20, CIF0_HREF, + GPIO2_B3 = 0x2b30, CIF0_CLKIN, + GPIO2_B4 = 0x2b40, ISP_FL_TRIG, + GPIO2_B5 = 0x2b50, ISP_FLASH_TRIG, + GPIO2_B6 = 0x2b60, ISP_PRELIGHT_TRIG, + GPIO2_B7 = 0x2b70, ISP_SHUTTER_TRIG, + + /* GPIO2_C */ + GPIO2_C0 = 0x2c00, ISP_SHUTTER_OPEN, + GPIO2_C4 = 0x2c40, NAND_RDY, + GPIO2_C5 = 0x2c50, NAND_WP, EMMC_PWREN, + GPIO2_C6 = 0x2c60, NAND_RDN, + GPIO2_C7 = 0x2c70, NAND_ALE, + + /* GPIO2_D */ + GPIO2_D0 = 0x2d00, NAND_CLE, + GPIO2_D1 = 0x2d10, NAND_WRN, I2C4_SDA_T1, + GPIO2_D2 = 0x2d20, NAND_CS0, I2C4_SCL_T1, + GPIO2_D3 = 0x2d30, NAND_CS1, + GPIO2_D4 = 0x2d40, NAND_CS2, EMMC_CMD, I2C2_SDA_T0, + GPIO2_D5 = 0x2d50, NAND_CS3, EMMC_RSTNOUT, I2C2_SCL_T0, + GPIO2_D6 = 0x2d60, NAND_DQS, EMMC_CLKOUT, + GPIO2_D7 = 0x2d70, PWM0_T1, + + /* GPIO3_A */ + GPIO3_A0 = 0x3a00, UART0_SIN, TRACE_D0, BB_UART0_SIN, + GPIO3_A1 = 0x3a10, UART0_SOUT, TRACE_D1, BB_UART0_SOUT, + GPIO3_A2 = 0x3a20, UART0_CTSN, TRACE_D2, BB_UART0_CTSN, + GPIO3_A3 = 0x3a30, UART0_RTSN, TRACE_D3, BB_UART0_RTSN, + GPIO3_A4 = 0x3a40, MMC1_D0, TRACE_D4, + GPIO3_A5 = 0x3a50, MMC1_D1, TRACE_D5, + GPIO3_A6 = 0x3a60, MMC1_D2, TRACE_D6, + GPIO3_A7 = 0x3a70, MMC1_D3, TRACE_D7, + + /* GPIO3_B */ + GPIO3_B0 = 0x3b00, MMC1_CMD, TRACE_D8, + GPIO3_B1 = 0x3b10, MMC1_CLKOUT, TRACE_D9, + GPIO3_B2 = 0x3b20, MMC1_DETN, TRACE_D10, I2S2_SCLK_T1, + GPIO3_B3 = 0x3b30, MMC1_WRPRT, TRACE_D11, I2S2_LRCK_T1, + GPIO3_B4 = 0x3b40, MMC1_PWREN, TRACE_D12, I2S2_SDI_T1, + GPIO3_B5 = 0x3b50, MMC1_BKEPWR, TRACE_D13, I2S2_SDO_T1, + GPIO3_B6 = 0x3b60, MMC1_INTN, TRACE_D14, + GPIO3_B7 = 0x3b70, TRACE_D15 = GPIO3_B7 + 2, + + /* GPIO3_C */ + GPIO3_C0 = 0x3c00, I2S0_MCLK, + GPIO3_C1 = 0x3c10, I2S0_SCLK, + GPIO3_C2 = 0x3c20, I2S0_LRCKRX, + GPIO3_C3 = 0x3c30, I2S0_LRCKTX, + GPIO3_C4 = 0x3c40, I2S0_SDI, + GPIO3_C5 = 0x3c50, I2S0_SDO, + GPIO3_C6 = 0x3c60, I2S1_SCLK, TRACE_CLK, SMC_D8, + GPIO3_C7 = 0x3c70, I2S1_LRCKRX, TRACE_CTL, SMC_D9, + + /* GPIO3_D */ + GPIO3_D0 = 0x3d00, I2S1_SDI, SMC_D11 = GPIO3_D0 + 3, + GPIO3_D1 = 0x3d10, I2S1_SDO, SMC_D12 = GPIO3_D1 + 3, + GPIO3_D2 = 0x3d20, SMC_D13 = GPIO3_D2 + 3, + GPIO3_D3 = 0x3d30, SMC_D14 = GPIO3_D3 + 3, + GPIO3_D4 = 0x3d40, SMC_D15 = GPIO3_D4 + 3, + GPIO3_D5 = 0x3d50, I2C4_SDA, + GPIO3_D6 = 0x3d60, I2C4_SCL, + GPIO3_D7 = 0x3d70, I2S1_LRCKTX, SMC_D10 = GPIO3_D7 + 3, + + /* GPIO4_A */ + GPIO4_A0 = 0x4a00, MMC0_D0, + GPIO4_A1 = 0x4a10, MMC0_D1, + GPIO4_A2 = 0x4a20, MMC0_D2, + GPIO4_A3 = 0x4a30, MMC0_D3, + GPIO4_A4 = 0x4a40, MMC0_RSTNOUT, + GPIO4_A5 = 0x4a50, MMC0_PWREN, + GPIO4_A6 = 0x4a60, MMC0_CLKOUT, + GPIO4_A7 = 0x4a70, MMC0_CMD, + + /* GPIO4_B */ + GPIO4_B0 = 0x4b00, MMC0_DETN, + GPIO4_B1 = 0x4b10, MMC0_WRPRT, + GPIO4_B2 = 0x4b20, UART3_SOUT_T0, GPS_SIG_T0, HDMI_CECSDA, + GPIO4_B3 = 0x4b30, UART3_SIN_T0, GPS_MAG_T0, HDMI_HOTPLUGIN, + GPIO4_B4 = 0x4b40, UART3_CTSN_T0, GPS_RFCLK_T0, + GPIO4_B5 = 0x4b50, UART3_RTSN_T0, + GPIO4_B6 = 0x4b60, PWM0_T0, BB_UART1_RTSN = GPIO4_B6 + 3, + GPIO4_B7 = 0x4b70, PWM1_T0, JTAG_TRSTN, BB_UART1_CTSN, + + /* GPIO4_C */ + GPIO4_C0 = 0x4c00, UART2_SIN, JTAG_TDI, BB_UART1_SIN, + GPIO4_C1 = 0x4c10, UART2_SOUT, JTAG_TDO, BB_UART1_SOUT, + GPIO4_C2 = 0x4c20, I2C2_SDA_T1, I2C2_SDA = I2C2_SDA_T1, + GPIO4_C3 = 0x4c30, I2C2_SCL_T1, I2C2_SCL = I2C2_SCL_T1, + GPIO4_C4 = 0x4c40, PWM2_T0, JTAG_TCK, OTG_DRV_VBUS, + GPIO4_C5 = 0x4c50, PWM3_T0, JTAG_TMS, HOST_DRV_VBUS, + GPIO4_C7 = 0x4c70, I2C1_SDA, + + /* GPIO4_D */ + GPIO4_D0 = 0x4d00, I2C1_SCL, + GPIO4_D1 = 0x4d10, PWM1_T1, SPI1_CS1, SPDIF_TX, + GPIO4_D2 = 0x4d20, PWM3_T1, SPI1_CLK, + GPIO4_D3 = 0x4d30, PWM2_T1, SPI1_CS0, + GPIO4_D4 = 0x4d40, UART3_SIN_T1, SPI1_TXD, GPS_MAG_T1, + GPIO4_D5 = 0x4d50, UART3_SOUT_T1, SPI1_RXD, GPS_SIG_T1, + GPIO4_D6 = 0x4d60, UART3_CTSN_T1, GPS_RFCLK_T1 = GPIO4_D6 + 3, + GPIO4_D7 = 0x4d70, UART3_RTSN_T1, +}; + +#define rk30_iomux_init() iomux_init() + +#endif diff --git a/arch/arm/mach-rk319x/include/mach/irqs.h b/arch/arm/mach-rk319x/include/mach/irqs.h new file mode 100644 index 000000000000..575506996aeb --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/irqs.h @@ -0,0 +1,101 @@ +#ifndef __MACH_IRQS_H +#define __MACH_IRQS_H + +#define FIQ_START 0 + +#define IRQ_LOCALTIMER 29 + +#define IRQ_DMAC1_0 32 +#define IRQ_DMAC1_1 33 +#define IRQ_DMAC2_0 34 +#define IRQ_DMAC2_1 35 +#define IRQ_DDR_PCTL 36 +#define IRQ_GPU_PP 37 +#define IRQ_GPU_MMU 38 +#define IRQ_GPU_GP 39 +#define IRQ_RGA 40 +#define IRQ_VEPU 41 +#define IRQ_VDPU 42 +#define IRQ_VPU_MMU 43 +#define IRQ_CIF0 44 +#define IRQ_LCDC0 45 +#define IRQ_LCDC1 46 +#define IRQ_PMU 47 +#define IRQ_USB_OTG 48 +#define IRQ_USB_HOST 49 +#define IRQ_HSIC 50 +#define IRQ_GPS 51 +#define IRQ_HSADC 52 +#define IRQ_SDMMC 53 +#define IRQ_SDIO 54 +#define IRQ_EMMC 55 +#define IRQ_SDMMC_DETECT 56 +#define IRQ_SDIO_DETECT 57 +#define IRQ_SARADC 58 +#define IRQ_NANDC 59 +#define IRQ_SMC 60 +#define IRQ_I2S1_2CH 61 +#define IRQ_TSADC 62 +#define IRQ_GPS_TIMER 63 +#define IRQ_SPDIF 64 +#define IRQ_UART0 65 +#define IRQ_UART1 66 +#define IRQ_UART2 67 +#define IRQ_UART3 68 +#define IRQ_SPI0 69 +#define IRQ_SPI1 70 +#define IRQ_I2C0 71 +#define IRQ_I2C1 72 +#define IRQ_I2C2 73 +#define IRQ_I2C3 74 +#define IRQ_I2C4 75 +#define IRQ_TIMER0 76 +#define IRQ_TIMER1 77 +#define IRQ_TIMER2 78 +#define IRQ_WDT 79 +#define IRQ_PWM0 80 +#define IRQ_PWM1 81 +#define IRQ_PWM2 82 +#define IRQ_PWM3 83 +#define IRQ_TIMER3 84 +#define IRQ_TIMER4 85 +#define IRQ_GPIO0 86 +#define IRQ_GPIO1 87 +#define IRQ_GPIO2 88 +#define IRQ_GPIO3 89 +#define IRQ_GPIO4 90 +#define IRQ_PERI_AHB_USB_ARBITER 91 +#define IRQ_IEP 92 +#define IRQ_OTG_BVALID 93 +#define IRQ_OTG0_ID 94 +#define IRQ_OTG0_LINESTATE 95 +#define IRQ_OTG1_LINESTATE 96 +#define IRQ_NOC_OBSRV 97 +#define IRQ_MIPI_DSI_CONTROLLER 98 +#define IRQ_HDMI 99 +#define IRQ_CRYPTO 100 +#define IRQ_ISP 101 +#define IRQ_RK_PWM 102 +#define IRQ_MAILBOX0 103 +#define IRQ_MAILBOX1 104 +#define IRQ_MAILBOX2 105 +#define IRQ_MAILBOX3 106 +#define IRQ_BB_DMA 107 +#define IRQ_BB_WDT 108 +#define IRQ_BB_I2S0 109 +#define IRQ_BB_I2S1 110 +#define IRQ_BB_PMU 111 +#define IRQ_SD_DETECT_DOUBLE_EDGE 112 + +#define IRQ_UART_SIGNAL 115 + +#define IRQ_ARM_PMU 156 + +#define NR_GIC_IRQS (5 * 32) +#define NR_GPIO_IRQS (5 * 32) +#define NR_BOARD_IRQS 64 +#define NR_IRQS (NR_GIC_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS) + +#define IRQ_BOARD_BASE (NR_GIC_IRQS + NR_GPIO_IRQS) + +#endif diff --git a/arch/arm/mach-rk319x/include/mach/loader.h b/arch/arm/mach-rk319x/include/mach/loader.h new file mode 100644 index 000000000000..6549ed217341 --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/loader.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk319x/include/mach/memory.h b/arch/arm/mach-rk319x/include/mach/memory.h new file mode 100644 index 000000000000..04e56fa7f4c2 --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/memory.h @@ -0,0 +1,15 @@ +#ifndef __MACH_MEMORY_H +#define __MACH_MEMORY_H + +#include +#include + +/* + * SRAM memory whereabouts + */ +#define SRAM_CODE_OFFSET (RK30_IMEM_BASE + 0x0000) +#define SRAM_CODE_END (RK30_IMEM_BASE + 0x0FFF) +#define SRAM_DATA_OFFSET (RK30_IMEM_BASE + 0x1000) +#define SRAM_DATA_END (RK30_IMEM_BASE + 0x2FFF) + +#endif diff --git a/arch/arm/mach-rk319x/include/mach/pmu.h b/arch/arm/mach-rk319x/include/mach/pmu.h new file mode 100644 index 000000000000..77d48083154c --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/pmu.h @@ -0,0 +1,50 @@ +#ifndef __MACH_PMU_H +#define __MACH_PMU_H + +#include + +#define PMU_WAKEUP_CFG0 0x0000 +#define PMU_WAKEUP_CFG1 0x0004 +#define PMU_WAKEUP_CFG2 0x0008 +#define PMU_PWRDN_CON 0x000C +#define PMU_PWRDN_ST 0x0010 +#define PMU_PWRMODE_CON 0x0014 +#define PMU_SFT_CON 0x0018 +#define PMU_INT_CON 0x001C +#define PMU_INT_ST 0x0020 +#define PMU_GPIO_INT_ST 0x0024 +#define PMU_GPIO_2EDGE_INT_ST 0x0028 +#define PMU_NOC_REQ 0x002C +#define PMU_NOC_ST 0x0030 +#define PMU_POWER_ST 0x0034 +#define PMU_OSC_CNT 0x0040 +#define PMU_PLLLOCK_CNT 0x0044 +#define PMU_PLLRST_CNT 0x0048 +#define PMU_STABLE_CNT 0x004C +#define PMU_DDRIO_PWRON_CNT 0x0050 +#define PMU_WAKEUP_RST_CLR_CNT 0x005C +#define PMU_DDR_SREF_ST 0x0064 +#define PMU_SYS_REG0 0x0070 +#define PMU_SYS_REG1 0x0074 +#define PMU_SYS_REG2 0x0078 +#define PMU_SYS_REG3 0x007C + +#define PMU_WAKEUP_CFG_BP 0x0120 +#define PMU_PWRDN_CON_BP 0x0124 +#define PMU_PWRMODE_CON_BP 0x0128 +#define PMU_SFT_CON_BP 0x012C +#define PMU_INT_CON_BP 0x0130 +#define PMU_INT_ST_BP 0x0134 +#define PMU_PWRDN_ST_BP 0x0138 +#define PMU_NOC_REQ_BP 0x0140 +#define PMU_NOC_ST_BP 0x0144 +#define PMU_POWER_ST_BP 0x0148 +#define PMU_OSC_CNT_BP 0x014C +#define PMU_PLLLOCK_CNT_BP 0x0150 +#define PMU_PLLRST_CNT_BP 0x0154 +#define PMU_SYS_REG0_BP 0x0170 +#define PMU_SYS_REG1_BP 0x0174 +#define PMU_SYS_REG2_BP 0x0178 +#define PMU_SYS_REG3_BP 0x017C + +#endif diff --git a/arch/arm/mach-rk319x/include/mach/sram.h b/arch/arm/mach-rk319x/include/mach/sram.h new file mode 100644 index 000000000000..976d8d78409b --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/sram.h @@ -0,0 +1 @@ +#include <../../mach-rk30/include/mach/sram.h> diff --git a/arch/arm/mach-rk319x/include/mach/system.h b/arch/arm/mach-rk319x/include/mach/system.h new file mode 100644 index 000000000000..e68cfe7e31ed --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/system.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk319x/include/mach/timex.h b/arch/arm/mach-rk319x/include/mach/timex.h new file mode 100644 index 000000000000..d2a02f98c397 --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/timex.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk319x/include/mach/uncompress.h b/arch/arm/mach-rk319x/include/mach/uncompress.h new file mode 100644 index 000000000000..a4acb7198e1c --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/uncompress.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk319x/include/mach/vmalloc.h b/arch/arm/mach-rk319x/include/mach/vmalloc.h new file mode 100644 index 000000000000..399af61e190b --- /dev/null +++ b/arch/arm/mach-rk319x/include/mach/vmalloc.h @@ -0,0 +1 @@ +#include <../../mach-rk30/include/mach/vmalloc.h> diff --git a/arch/arm/mach-rk319x/io.c b/arch/arm/mach-rk319x/io.c new file mode 100644 index 000000000000..fbcecdc999bd --- /dev/null +++ b/arch/arm/mach-rk319x/io.c @@ -0,0 +1,62 @@ +/* + * + * Copyright (C) 2013 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#define RK319X_DEVICE(name) { \ + .virtual = (unsigned long) RK319X_##name##_BASE, \ + .pfn = __phys_to_pfn(RK319X_##name##_PHYS), \ + .length = RK319X_##name##_SIZE, \ + .type = MT_DEVICE, \ + } + +static struct map_desc rk319x_io_desc[] __initdata = { + RK319X_DEVICE(ROM), + RK319X_DEVICE(CORE), + RK319X_DEVICE(CPU_AXI_BUS), +#if CONFIG_RK_DEBUG_UART == 0 + RK319X_DEVICE(UART0), +#elif CONFIG_RK_DEBUG_UART == 1 + RK319X_DEVICE(UART1), +#elif CONFIG_RK_DEBUG_UART == 2 + RK319X_DEVICE(UART2), +#elif CONFIG_RK_DEBUG_UART == 3 + RK319X_DEVICE(UART3), +#endif + RK319X_DEVICE(GRF), + RK319X_DEVICE(BB_GRF), + RK319X_DEVICE(CRU), + RK319X_DEVICE(PMU), + RK319X_DEVICE(GPIO0), + RK319X_DEVICE(GPIO1), + RK319X_DEVICE(GPIO2), + RK319X_DEVICE(GPIO3), + RK319X_DEVICE(GPIO4), + RK319X_DEVICE(TIMER), + RK319X_DEVICE(EFUSE), + RK319X_DEVICE(PWM), + RK319X_DEVICE(DDR_PCTL), + RK319X_DEVICE(DDR_PUBL), +}; + +void __init rk30_map_common_io(void) +{ + iotable_init(rk319x_io_desc, ARRAY_SIZE(rk319x_io_desc)); +} diff --git a/arch/arm/mach-rk319x/rk_timer.c b/arch/arm/mach-rk319x/rk_timer.c new file mode 100644 index 000000000000..a7df1ab5d07c --- /dev/null +++ b/arch/arm/mach-rk319x/rk_timer.c @@ -0,0 +1,108 @@ +#include +#include +#include +#include + +#define TIMER_NAME "rk_timer" +#define BASE RK319X_TIMER_BASE +#define OFFSET 0x20 + +static struct resource rk_timer_resources[] __initdata = { + { + .name = "cs_base", + .start = (unsigned long) BASE + 4 * OFFSET, + .flags = IORESOURCE_MEM, + }, { + .name = "cs_clk", + .start = (unsigned long) "timer4", + }, { + .name = "cs_pclk", + .start = (unsigned long) "pclk_timer", + }, + + { + .name = "ce_base0", + .start = (unsigned long) BASE + 0 * OFFSET, + .flags = IORESOURCE_MEM, + }, { + .name = "ce_irq0", + .start = (unsigned long) IRQ_TIMER0, + .flags = IORESOURCE_IRQ, + }, { + .name = "ce_clk0", + .start = (unsigned long) "timer0", + }, { + .name = "ce_pclk0", + .start = (unsigned long) "pclk_timer", + }, + + { + .name = "ce_base1", + .start = (unsigned long) BASE + 1 * OFFSET, + .flags = IORESOURCE_MEM, + }, { + .name = "ce_irq1", + .start = (unsigned long) IRQ_TIMER1, + .flags = IORESOURCE_IRQ, + }, { + .name = "ce_clk1", + .start = (unsigned long) "timer1", + }, { + .name = "ce_pclk1", + .start = (unsigned long) "pclk_timer", + }, + + { + .name = "ce_base2", + .start = (unsigned long) BASE + 2 * OFFSET, + .flags = IORESOURCE_MEM, + }, { + .name = "ce_irq2", + .start = (unsigned long) IRQ_TIMER2, + .flags = IORESOURCE_IRQ, + }, { + .name = "ce_clk2", + .start = (unsigned long) "timer2", + }, { + .name = "ce_pclk2", + .start = (unsigned long) "pclk_timer", + }, + + { + .name = "ce_base3", + .start = (unsigned long) BASE + 3 * OFFSET, + .flags = IORESOURCE_MEM, + }, { + .name = "ce_irq3", + .start = (unsigned long) IRQ_TIMER3, + .flags = IORESOURCE_IRQ, + }, { + .name = "ce_clk3", + .start = (unsigned long) "timer3", + }, { + .name = "ce_pclk3", + .start = (unsigned long) "pclk_timer", + }, +}; + +static struct platform_device rk_timer_device __initdata = { + .name = TIMER_NAME, + .id = 0, + .resource = rk_timer_resources, + .num_resources = ARRAY_SIZE(rk_timer_resources), +}; + +static struct platform_device *rk_timer_devices[] __initdata = { + &rk_timer_device, +}; + +static void __init rk_timer_init(void) +{ + early_platform_add_devices(rk_timer_devices, ARRAY_SIZE(rk_timer_devices)); + early_platform_driver_register_all(TIMER_NAME); + early_platform_driver_probe(TIMER_NAME, 1, 0); +} + +struct sys_timer rk30_timer = { + .init = rk_timer_init +}; diff --git a/arch/arm/plat-rk/Kconfig b/arch/arm/plat-rk/Kconfig index 2e12de51e2ef..5fcf32b7a2b3 100755 --- a/arch/arm/plat-rk/Kconfig +++ b/arch/arm/plat-rk/Kconfig @@ -84,7 +84,7 @@ endchoice config EMMC_IO_3_3V bool "Emmc io domain voltage select 3.3v" - depends on ARCH_RK3066B || ARCH_RK3188 + depends on ARCH_RK3066B || ARCH_RK3188 || ARCH_RK319X config DDR_INIT_CHANGE_FREQ bool "Enable change DDR frequence when ddr_init" @@ -99,7 +99,7 @@ config DDR_SDRAM_FREQ config DDR_FREQ bool "Enable DDR frequency scaling" - default y if ARCH_RK3066B || ARCH_RK3188 + default y if ARCH_RK3066B || ARCH_RK3188 || ARCH_RK319X select RK_SRAM_DMA if ARCH_RK30XX config DDR_TEST @@ -179,13 +179,13 @@ config RK_EARLY_PRINTK config RK_DEBUG_UART int "Debug UART" default 1 if ARCH_RK29 - default 2 if ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026 + default 2 if ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026 || ARCH_RK319X help Select a UART for debugging. -1 disable. config RK_USB_UART bool "Support USB UART Bypass Function" - depends on (ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026) && (RK_DEBUG_UART = 2) + depends on (ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026 || ARCH_RK319X) && (RK_DEBUG_UART = 2) config RK_CONSOLE_THREAD bool "Console write by thread" @@ -196,7 +196,7 @@ config RK_CONSOLE_THREAD config RK_SRAM_DMA bool "Sound DMA buffer in internal SRAM" - depends on ARCH_RK30 || ARCH_RK3188 + depends on ARCH_RK30 || ARCH_RK3188 || ARCH_RK319X config RK_PL330_DMA bool @@ -222,7 +222,7 @@ config RK_TIMER config RK_USB_DETECT_BY_OTG_BVALID bool "Wakeup system by OTG BVALID interrupt when USB OTG conneted" - depends on USB_GADGET && (ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026) + depends on USB_GADGET && (ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026 || ARCH_RK319X) default y endif diff --git a/arch/arm/plat-rk/include/plat/memory.h b/arch/arm/plat-rk/include/plat/memory.h index 1b55a3902a90..4772263484f6 100644 --- a/arch/arm/plat-rk/include/plat/memory.h +++ b/arch/arm/plat-rk/include/plat/memory.h @@ -6,7 +6,11 @@ /* * Physical DRAM offset. */ +#if defined(CONFIG_ARCH_RK319X) +#define PLAT_PHYS_OFFSET UL(0x00000000) +#else #define PLAT_PHYS_OFFSET UL(0x60000000) +#endif #define CONSISTENT_DMA_SIZE SZ_8M diff --git a/arch/arm/plat-rk/iomux.c b/arch/arm/plat-rk/iomux.c index 93e40ea0f862..6cb00a43e1e0 100644 --- a/arch/arm/plat-rk/iomux.c +++ b/arch/arm/plat-rk/iomux.c @@ -90,6 +90,11 @@ void iomux_set(unsigned int mode) //mask = (m.mux.mode < 2)?1:3; mask = 3; v = (m.mux.mode << (m.mux.off * 2)) + (mask << (m.mux.off * 2 + 16)); +#if defined(CONFIG_ARCH_RK319X) + if (m.mux.bank == 0) + addr = (unsigned int)RK319X_BB_GRF_BASE + BB_GRF_GPIO0A_IOMUX + 4 * (m.mux.goff - 0x0A); + else +#endif addr = (unsigned int)GRF_IOMUX_BASE + 16 * m.mux.bank + 4 * (m.mux.goff - 0x0A); DBG("<%s> mode(0x%04x), reg_addr(0x%08x), set_value(0x%08x)\n", __func__, mode, addr, v); @@ -108,6 +113,11 @@ int iomux_is_set(unsigned int mode) } mask = 3; v = (m.mux.mode << (m.mux.off * 2)) + (mask << (m.mux.off * 2 + 16)); +#if defined(CONFIG_ARCH_RK319X) + if (m.mux.bank == 0) + addr = (unsigned int)RK319X_BB_GRF_BASE + BB_GRF_GPIO0A_IOMUX + 4 * (m.mux.goff - 0x0A); + else +#endif addr = (unsigned int)GRF_IOMUX_BASE + 16 * m.mux.bank + 4 * (m.mux.goff - 0x0A); if((readl_relaxed((void *)addr) & v) != 0) diff --git a/arch/arm/plat-rk/sram.c b/arch/arm/plat-rk/sram.c index b72906706657..25857f849461 100755 --- a/arch/arm/plat-rk/sram.c +++ b/arch/arm/plat-rk/sram.c @@ -186,6 +186,8 @@ static void __iomem *gpio_base[] = {RK30_GPIO0_BASE, RK30_GPIO1_BASE, RK30_GPIO2 #elif defined(CONFIG_ARCH_RK30) static void __iomem *gpio_base[] = {RK30_GPIO0_BASE, RK30_GPIO1_BASE, RK30_GPIO2_BASE, RK30_GPIO3_BASE, RK30_GPIO4_BASE, 0, RK30_GPIO6_BASE}; +#elif defined(CONFIG_ARCH_RK319X) +static void __iomem *gpio_base[] = {RK319X_GPIO0_BASE, RK319X_GPIO1_BASE, RK319X_GPIO2_BASE, RK319X_GPIO3_BASE, RK319X_GPIO4_BASE}; #endif int sram_gpio_init(int gpio, struct sram_gpio_data *data) diff --git a/drivers/adc/plat/Kconfig b/drivers/adc/plat/Kconfig index 4ad572d464ed..915d50c0bd6d 100644 --- a/drivers/adc/plat/Kconfig +++ b/drivers/adc/plat/Kconfig @@ -5,7 +5,7 @@ choice prompt "ADC hardware drivers" default ADC_RK29 if ARCH_RK29 - default ADC_RK30 if ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026 + default ADC_RK30 if ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026 || ARCH_RK319X config ADC_NULL bool "NULL" @@ -24,7 +24,7 @@ config ADC_RK29 config ADC_RK30 bool "RK30 adc interface" - depends on ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026 + depends on ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026 || ARCH_RK319X help This supports the use of the ADC interface on rk30 processors. endchoice diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c index b63ff9943650..5775b99ceeaf 100755 --- a/drivers/base/cpu.c +++ b/drivers/base/cpu.c @@ -149,7 +149,7 @@ static ssize_t show_cpus_attr(struct sysdev_class *class, struct cpu_attr *ca = container_of(attr, struct cpu_attr, attr); int n = cpulist_scnprintf(buf, PAGE_SIZE-2, *(ca->map)); -#if defined(CONFIG_ARCH_RK3188) && defined(CONFIG_CRC32) +#if (defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK319X)) && defined(CONFIG_CRC32) if( !strcmp(attr->attr.name, "present") && crc32(0, current->comm, strlen(current->comm))==0xe7b53cc5 ) { diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 9b3e7d407e0a..a3a3515f5c4a 100755 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_ARCH_RK2928) += gpio-rk30.o obj-$(CONFIG_ARCH_RK30) += gpio-rk30.o obj-$(CONFIG_ARCH_RK3188) += gpio-rk30.o obj-$(CONFIG_ARCH_RK3026) += gpio-rk30.o +obj-$(CONFIG_ARCH_RK319X) += gpio-rk30.o obj-$(CONFIG_GPIO_JANZ_TTL) += janz-ttl.o obj-$(CONFIG_GPIO_SX150X) += sx150x.o obj-$(CONFIG_GPIO_VX855) += vx855_gpio.o diff --git a/drivers/gpio/gpio-rk30.c b/drivers/gpio/gpio-rk30.c index fe56ea9dbca3..2a170ce574ef 100755 --- a/drivers/gpio/gpio-rk30.c +++ b/drivers/gpio/gpio-rk30.c @@ -35,6 +35,8 @@ #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188) #define MAX_PIN RK30_PIN3_PD7 +#elif defined(CONFIG_ARCH_RK319X) +#define MAX_PIN RK30_PIN4_PD7 #elif defined(CONFIG_ARCH_RK30) #define MAX_PIN RK30_PIN6_PB7 #elif defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026) @@ -103,8 +105,10 @@ static struct rk30_gpio_bank rk30_gpio_banks[] = { RK30_GPIO_BANK(1), RK30_GPIO_BANK(2), RK30_GPIO_BANK(3), -#if defined(CONFIG_ARCH_RK30) && !defined(CONFIG_ARCH_RK3066B) +#if GPIO_BANKS > 4 RK30_GPIO_BANK(4), +#endif +#if GPIO_BANKS > 5 RK30_GPIO_BANK(6), #endif }; @@ -334,7 +338,7 @@ static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, enu void __iomem *base; u32 val; -#if defined(CONFIG_ARCH_RK3188) +#if defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK319X) /* * pull setting * 2'b00: Z(Noraml operaton) @@ -357,6 +361,17 @@ static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, enu return -EINVAL; } +#if defined(CONFIG_ARCH_RK319X) + if (bank->id == 0) { + base = RK319X_BB_GRF_BASE + BB_GRF_GPIO0A_PULL + ((offset / 8) * 4); + offset = (offset % 8) * 2; + __raw_writel((0x3 << (16 + offset)) | (val << offset), base); + } else { + base = RK319X_GRF_BASE + GRF_GPIO1A_PULL + (bank->id - 1) * 16 + ((offset / 8) * 4); + offset = (7 - (offset % 8)) * 2; + __raw_writel((0x3 << (16 + offset)) | (val << offset), base); + } +#else if (bank->id == 0 && offset < 12) { base = RK30_PMU_BASE + PMU_GPIO0A_PULL + ((offset / 8) * 4); offset = (offset % 8) * 2; @@ -366,6 +381,7 @@ static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, enu offset = (7 - (offset % 8)) * 2; __raw_writel((0x3 << (16 + offset)) | (val << offset), base); } +#endif #else /* RK30XX && RK292X */ /* diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 3bab67c9b39c..3ffeaf82c288 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -854,7 +854,7 @@ if I2C_RK30 default y help This supports the use of the I2C0 channel on RK Soc. - if I2C0_RK30 + if I2C0_RK30 && (ARCH_RK30 || ARCH_RK3188 || ARCH_RK2928 || ARCH_RK3026) choice prompt "I2C Controller Select" config I2C0_CONTROLLER_RK29 @@ -868,7 +868,7 @@ if I2C_RK30 default y help This supports the use of the I2C1 channel on RK Soc. - if I2C1_RK30 + if I2C1_RK30 && (ARCH_RK30 || ARCH_RK3188 || ARCH_RK2928 || ARCH_RK3026) choice prompt "I2C Controller Select" config I2C1_CONTROLLER_RK29 @@ -882,7 +882,7 @@ if I2C_RK30 default y help This supports the use of the I2C2 channel on RK Soc. - if I2C2_RK30 + if I2C2_RK30 && (ARCH_RK30 || ARCH_RK3188 || ARCH_RK2928 || ARCH_RK3026) choice prompt "I2C Controller Select" config I2C2_CONTROLLER_RK29 @@ -897,7 +897,7 @@ if I2C_RK30 default y help This supports the use of the I2C3 channel on RK Soc. - if I2C3_RK30 + if I2C3_RK30 && (ARCH_RK30 || ARCH_RK3188 || ARCH_RK2928 || ARCH_RK3026) choice prompt "I2C Controller Select" config I2C3_CONTROLLER_RK29 @@ -912,7 +912,7 @@ if I2C_RK30 default y help This supports the use of the I2C4 channel on RK Soc. - if I2C4_RK30 + if I2C4_RK30 && (ARCH_RK30 || ARCH_RK3188 || ARCH_RK2928 || ARCH_RK3026) choice prompt "I2C Controller Select" config I2C4_CONTROLLER_RK29 diff --git a/drivers/i2c/busses/i2c-rk30.c b/drivers/i2c/busses/i2c-rk30.c index eb26047d2543..146b9cc21802 100755 --- a/drivers/i2c/busses/i2c-rk30.c +++ b/drivers/i2c/busses/i2c-rk30.c @@ -96,8 +96,11 @@ static int rk30_i2c_probe(struct platform_device *pdev) dev_err(&pdev->dev, "no memory for state\n"); return -ENOMEM; } + +#if !defined(CONFIG_ARCH_RK319X) i2c->con_base = (void __iomem *)GRF_I2C_CON_BASE; i2c_adap_sel(i2c, pdata->bus_num, pdata->adap_type); +#endif if(pdata->io_init) pdata->io_init(); diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 6418ad298cd1..e0d6d9e1bd32 100755 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -6,7 +6,7 @@ comment "MMC/SD/SDIO Host Controller Drivers" config EMMC_RK tristate "RK emmc controller suppport" - depends on ARCH_RK3188 || ARCH_RK3066B || ARCH_RK3026 + depends on ARCH_RK3188 || ARCH_RK3066B || ARCH_RK3026 || ARCH_RK319X default y help This selects the RK EMMC controller diff --git a/drivers/mmc/host/rk29_sdmmc.c b/drivers/mmc/host/rk29_sdmmc.c index 60e3f0824bf2..eb9f8327aa8f 100755 --- a/drivers/mmc/host/rk29_sdmmc.c +++ b/drivers/mmc/host/rk29_sdmmc.c @@ -74,7 +74,7 @@ int debug_level = 5; #endif //use the new iomux-API -#if defined(CONFIG_ARCH_RK3066B)||defined(CONFIG_ARCH_RK3168)||defined(CONFIG_ARCH_RK3188)||defined(CONFIG_ARCH_RK3026) +#if defined(CONFIG_ARCH_RK3066B)||defined(CONFIG_ARCH_RK3168)||defined(CONFIG_ARCH_RK3188)||defined(CONFIG_ARCH_RK3026)||defined(CONFIG_ARCH_RK319X) #define DRIVER_SDMMC_USE_NEW_IOMUX_API 1 #else #define DRIVER_SDMMC_USE_NEW_IOMUX_API 0 diff --git a/drivers/rtc/rtc-HYM8563.c b/drivers/rtc/rtc-HYM8563.c index d6d8fc6bb30d..8288f95d4216 100755 --- a/drivers/rtc/rtc-HYM8563.c +++ b/drivers/rtc/rtc-HYM8563.c @@ -625,7 +625,7 @@ static struct i2c_driver hym8563_driver = { }, .probe = hym8563_probe, .remove = __devexit_p(hym8563_remove), -#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188) +#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK319X) //.shutdown=hym8563_shutdown, #else .shutdown=hym8563_shutdown, diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 40dba2f27516..559b95cf55f4 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1557,7 +1557,6 @@ config UART1_DMA_RK29 config UART1_WAKEUP_RK29 bool "Serial port 1 WAKEUP support (EXPERIMENTAL)" depends on UART1_RK29 - default 0 config UART2_RK29 bool "Serial port 2 support" @@ -1565,7 +1564,7 @@ config UART2_RK29 config UART2_CTS_RTS_RK29 bool "Serial port 2 CTS/RTS support" - depends on UART2_RK29 && !ARCH_RK30 && !ARCH_RK3188 + depends on UART2_RK29 && !ARCH_RK30 && !ARCH_RK3188 && !ARCH_RK319X config UART2_DMA_RK29 int "Serial port 2 DMA support (EXPERIMENTAL)" @@ -1578,7 +1577,6 @@ config UART2_DMA_RK29 config UART2_WAKEUP_RK29 bool "Serial port 2 WAKEUP support (EXPERIMENTAL)" depends on UART2_RK29 - default 0 config UART3_RK29 bool "Serial port 3 support" @@ -1599,7 +1597,6 @@ config UART3_DMA_RK29 config UART3_WAKEUP_RK29 bool "Serial port 3 WAKEUP support (EXPERIMENTAL)" depends on UART3_RK29 - default 0 config SERIAL_RK29_CONSOLE bool "Serial console support" diff --git a/sound/soc/rk29/Kconfig b/sound/soc/rk29/Kconfig index 2966744847bf..8a5ce5fd32e4 100755 --- a/sound/soc/rk29/Kconfig +++ b/sound/soc/rk29/Kconfig @@ -15,7 +15,7 @@ config SND_RK_SOC_SPDIF config SND_RK29_SOC_I2S_8CH bool "Soc RK29 I2S 8 Channel support(I2S0)" default y - depends on SND_RK29_SOC_I2S && !ARCH_RK3066B && !ARCH_RK3188 + depends on SND_RK29_SOC_I2S && !ARCH_RK3066B && !ARCH_RK3188 && !ARCH_RK319X help This supports the use of the 8 Channel I2S interface on rk29 processors. -- 2.34.1