From 66413b61f0fee8f8177aeadb27d16e8eb7d30472 Mon Sep 17 00:00:00 2001 From: Preston Gurd Date: Tue, 1 May 2012 19:50:22 +0000 Subject: [PATCH] =?utf8?q?This=20patch=20marks=20the=20X86=20floating=20po?= =?utf8?q?int=20stack=20registers=20ST0-ST7=20as=20reserved=20in=20order?= =?utf8?q?=20to=20avoid=20assertion=20failures=20in=20the=20register=20sca?= =?utf8?q?venger.=20The=20assertion=20failures=20were=20=E2=80=9CBad=20mac?= =?utf8?q?hine=20code:=20Using=20an=20undefined=20physical=20register?= =?utf8?q?=E2=80=9D=20and=20=E2=80=9CBad=20machine=20code:=20MBB=20exits?= =?utf8?q?=20via=20unconditional=20fall-through=20but=20its=20successor=20?= =?utf8?q?differs=20from=20its=20CFG=20successor!=E2=80=9D.?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155930 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86RegisterInfo.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 6e00a552b60..402c54cadca 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -299,6 +299,16 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const { Reserved.set(X86::FS); Reserved.set(X86::GS); + // Mark the floating point stack registers as reserved. + Reserved.set(X86::ST0); + Reserved.set(X86::ST1); + Reserved.set(X86::ST2); + Reserved.set(X86::ST3); + Reserved.set(X86::ST4); + Reserved.set(X86::ST5); + Reserved.set(X86::ST6); + Reserved.set(X86::ST7); + // Reserve the registers that only exist in 64-bit mode. if (!Is64Bit) { // These 8-bit registers are part of the x86-64 extension even though their -- 2.34.1