From 6a82fbc29ff24a77361b5f25fa19e9131926b8c2 Mon Sep 17 00:00:00 2001 From: Bradley Smith Date: Wed, 9 Apr 2014 14:44:31 +0000 Subject: [PATCH] [ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205892 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM64/ARM64InstrFormats.td | 25 +++++++++++++++++-- lib/Target/ARM64/ARM64InstrInfo.td | 22 ++++++++-------- .../ARM64/InstPrinter/ARM64InstPrinter.cpp | 13 ++++++++++ .../ARM64/InstPrinter/ARM64InstPrinter.h | 20 +++++++++++++++ 4 files changed, 67 insertions(+), 13 deletions(-) diff --git a/lib/Target/ARM64/ARM64InstrFormats.td b/lib/Target/ARM64/ARM64InstrFormats.td index fc193fdd91f..af8b6838212 100644 --- a/lib/Target/ARM64/ARM64InstrFormats.td +++ b/lib/Target/ARM64/ARM64InstrFormats.td @@ -2431,7 +2431,13 @@ class am_unscaled_operand : Operand { let ParserMatchClass = MemoryUnscaledOperand; let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset); } +class am_unscaled_wb_operand : Operand { + let PrintMethod = "printAMUnscaledWB"; + let ParserMatchClass = MemoryUnscaledOperand; + let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset); +} def am_unscaled : am_unscaled_operand; +def am_unscaled_wb: am_unscaled_wb_operand; def am_unscaled8 : am_unscaled_operand, ComplexPattern; def am_unscaled16 : am_unscaled_operand, @@ -2569,7 +2575,7 @@ class LoadPreIdx sz, bit V, bits<2> opc, RegisterClass regtype, string asm> : BaseLoadStorePreIdx, + (ins am_unscaled_wb:$addr), asm, ""/*"$addr.base = $wback"*/>, Sched<[WriteLD, WriteAdr]>; let mayStore = 1, mayLoad = 0 in @@ -2577,7 +2583,7 @@ class StorePreIdx sz, bit V, bits<2> opc, RegisterClass regtype, string asm> : BaseLoadStorePreIdx, Sched<[WriteAdr, WriteST]>; } // hasSideEffects = 0 @@ -2752,6 +2758,11 @@ def am_indexed32simm7 : Operand { // ComplexPattern<...> let ParserMatchClass = MemoryIndexed32SImm7; let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset); } +def am_indexed32simm7_wb : Operand { // ComplexPattern<...> + let PrintMethod = "printAMIndexed32WB"; + let ParserMatchClass = MemoryIndexed32SImm7; + let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset); +} def MemoryIndexed64SImm7 : AsmOperandClass { let Name = "MemoryIndexed64SImm7"; @@ -2762,6 +2773,11 @@ def am_indexed64simm7 : Operand { // ComplexPattern<...> let ParserMatchClass = MemoryIndexed64SImm7; let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset); } +def am_indexed64simm7_wb : Operand { // ComplexPattern<...> + let PrintMethod = "printAMIndexed64WB"; + let ParserMatchClass = MemoryIndexed64SImm7; + let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset); +} def MemoryIndexed128SImm7 : AsmOperandClass { let Name = "MemoryIndexed128SImm7"; @@ -2772,6 +2788,11 @@ def am_indexed128simm7 : Operand { // ComplexPattern<...> let ParserMatchClass = MemoryIndexed128SImm7; let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset); } +def am_indexed128simm7_wb : Operand { // ComplexPattern<...> + let PrintMethod = "printAMIndexed128WB"; + let ParserMatchClass = MemoryIndexed128SImm7; + let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset); +} class BaseLoadStorePairPreIdx opc, bit V, bit L, dag oops, dag iops, string asm> diff --git a/lib/Target/ARM64/ARM64InstrInfo.td b/lib/Target/ARM64/ARM64InstrInfo.td index ca0ff681786..b3baf94d410 100644 --- a/lib/Target/ARM64/ARM64InstrInfo.td +++ b/lib/Target/ARM64/ARM64InstrInfo.td @@ -965,13 +965,13 @@ def LDPQi : LoadPairOffset<0b10, 1, FPR128, am_indexed128simm7, "ldp">; def LDPSWi : LoadPairOffset<0b01, 0, GPR64, am_indexed32simm7, "ldpsw">; // Pair (pre-indexed) -def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, am_indexed32simm7, "ldp">; -def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, am_indexed64simm7, "ldp">; -def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, am_indexed32simm7, "ldp">; -def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, am_indexed64simm7, "ldp">; -def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, am_indexed128simm7, "ldp">; +def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "ldp">; +def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "ldp">; +def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "ldp">; +def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "ldp">; +def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "ldp">; -def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, am_indexed32simm7, "ldpsw">; +def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, am_indexed32simm7_wb, "ldpsw">; // Pair (post-indexed) def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">; @@ -1514,11 +1514,11 @@ def STPDi : StorePairOffset<0b01, 1, FPR64, am_indexed64simm7, "stp">; def STPQi : StorePairOffset<0b10, 1, FPR128, am_indexed128simm7, "stp">; // Pair (pre-indexed) -def STPWpre : StorePairPreIdx<0b00, 0, GPR32, am_indexed32simm7, "stp">; -def STPXpre : StorePairPreIdx<0b10, 0, GPR64, am_indexed64simm7, "stp">; -def STPSpre : StorePairPreIdx<0b00, 1, FPR32, am_indexed32simm7, "stp">; -def STPDpre : StorePairPreIdx<0b01, 1, FPR64, am_indexed64simm7, "stp">; -def STPQpre : StorePairPreIdx<0b10, 1, FPR128, am_indexed128simm7, "stp">; +def STPWpre : StorePairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "stp">; +def STPXpre : StorePairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "stp">; +def STPSpre : StorePairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "stp">; +def STPDpre : StorePairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "stp">; +def STPQpre : StorePairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "stp">; // Pair (pre-indexed) def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">; diff --git a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp index a10624a0f89..ffa4a33b626 100644 --- a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp +++ b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp @@ -1200,6 +1200,19 @@ void ARM64InstPrinter::printAMIndexed(const MCInst *MI, unsigned OpNum, O << ']'; } +void ARM64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum, + unsigned Scale, raw_ostream &O) { + const MCOperand MO1 = MI->getOperand(OpNum + 1); + O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()); + if (MO1.isImm()) { + O << ", #" << (MO1.getImm() * Scale); + } else { + assert(MO1.isExpr() && "Unexpected operand type!"); + O << ", " << *MO1.getExpr(); + } + O << ']'; +} + void ARM64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum, raw_ostream &O) { unsigned prfop = MI->getOperand(OpNum).getImm(); diff --git a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h index 13e92899c81..778e8651b8f 100644 --- a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h +++ b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h @@ -73,28 +73,48 @@ protected: raw_ostream &O); void printAMIndexed(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O); + void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale, + raw_ostream &O); void printAMIndexed128(const MCInst *MI, unsigned OpNum, raw_ostream &O) { printAMIndexed(MI, OpNum, 16, O); } + void printAMIndexed128WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) { + printAMIndexedWB(MI, OpNum, 16, O); + } void printAMIndexed64(const MCInst *MI, unsigned OpNum, raw_ostream &O) { printAMIndexed(MI, OpNum, 8, O); } + void printAMIndexed64WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) { + printAMIndexedWB(MI, OpNum, 8, O); + } void printAMIndexed32(const MCInst *MI, unsigned OpNum, raw_ostream &O) { printAMIndexed(MI, OpNum, 4, O); } + void printAMIndexed32WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) { + printAMIndexedWB(MI, OpNum, 4, O); + } void printAMIndexed16(const MCInst *MI, unsigned OpNum, raw_ostream &O) { printAMIndexed(MI, OpNum, 2, O); } + void printAMIndexed16WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) { + printAMIndexedWB(MI, OpNum, 2, O); + } void printAMIndexed8(const MCInst *MI, unsigned OpNum, raw_ostream &O) { printAMIndexed(MI, OpNum, 1, O); } + void printAMIndexed8WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) { + printAMIndexedWB(MI, OpNum, 1, O); + } void printAMUnscaled(const MCInst *MI, unsigned OpNum, raw_ostream &O) { printAMIndexed(MI, OpNum, 1, O); } + void printAMUnscaledWB(const MCInst *MI, unsigned OpNum, raw_ostream &O) { + printAMIndexedWB(MI, OpNum, 1, O); + } void printAMNoIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printImmScale4(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printImmScale8(const MCInst *MI, unsigned OpNum, raw_ostream &O); -- 2.34.1