From 6aab9cf65cd1e96f9d0fa99f8453da454648bba1 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 18 Nov 2002 05:37:11 +0000 Subject: [PATCH] Start to add more information to instr.def git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4741 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86.h | 2 +- lib/Target/X86/X86InstrInfo.cpp | 2 +- lib/Target/X86/X86InstrInfo.def | 177 ++++++++++++++++---------------- lib/Target/X86/X86InstrInfo.h | 49 ++++++++- 4 files changed, 136 insertions(+), 94 deletions(-) diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h index d94ec28f3e5..10bc017993c 100644 --- a/lib/Target/X86/X86.h +++ b/lib/Target/X86/X86.h @@ -52,7 +52,7 @@ namespace X86 { // This defines a large number of symbolic names for X86 instruction opcodes. enum Opcode { -#define I(ENUM, NAME, FLAGS, TSFLAGS) ENUM, +#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS) ENUM, #include "X86InstrInfo.def" }; } diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index e54883395d2..c4785e7346c 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -12,7 +12,7 @@ // descriptors // static const MachineInstrDescriptor X86Insts[] = { -#define I(ENUM, NAME, FLAGS, TSFLAGS) \ +#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS) \ { NAME, \ -1, /* Always vararg */ \ ((TSFLAGS) & X86II::Void) ? -1 : 0, /* Result is in 0 */ \ diff --git a/lib/Target/X86/X86InstrInfo.def b/lib/Target/X86/X86InstrInfo.def index 6a780f9b4f1..69c6178b303 100644 --- a/lib/Target/X86/X86InstrInfo.def +++ b/lib/Target/X86/X86InstrInfo.def @@ -20,130 +20,131 @@ // Arguments to be passed into the I macro // #1: Enum name - This ends up being the opcode symbol in the X86 namespace // #2: Opcode name, as used by the gnu assembler -// #3: Instruction Flags - This should be a field or'd together that contains +// #3: The base opcode for the instruction +// #4: Instruction Flags - This should be a field or'd together that contains // constants from the MachineInstrInfo.h file. -// #4: Target Specific Flags - Another bitfield containing X86 specific flags +// #5: Target Specific Flags - Another bitfield containing X86 specific flags // that we are interested in for each instruction. These should be flags // defined in X86InstrInfo.h in the X86II namespace. // // The first instruction must always be the PHI instruction: -I(PHI , "phi", 0, 0) +I(PHI , "phi", 0, 0, 0) // The second instruction must always be the noop instruction: -I(NOOP , "nop", 0, X86II::Void) // nop 90 +I(NOOP , "nop", 0x90, 0, X86II::RawFrm | X86II::Void) // nop // Flow control instructions -I(RET , "ret", M_RET_FLAG, X86II::Void) // ret CB -I(JMP , "jmp", M_BRANCH_FLAG, X86II::Void) // jmp foo EB|E9 cb|w +I(RET , "ret", 0xCB, M_RET_FLAG, X86II::RawFrm | X86II::Void) // ret +I(JMP , "jmp", 0x00, M_BRANCH_FLAG, X86II::Void) // jmp foo EB|E9 cb|w // Misc instructions -I(LEAVE , "leave", 0, 0) // leave C9 +I(LEAVE , "leave", 0xC9, 0, X86II::RawFrm) // leave // Move instructions -I(MOVrr8 , "movb", 0, 0) // R8 = R8 88/r -I(MOVrr16 , "movw", 0, 0) // R16 = R16 89/r -I(MOVrr32 , "movl", 0, 0) // R32 = R32 89/r -I(MOVir8 , "movb", 0, 0) // R8 = imm8 B0+ rb -I(MOVir16 , "movw", 0, 0) // R16 = imm16 B8+ rw -I(MOVir32 , "movl", 0, 0) // R32 = imm32 B8+ rd -I(MOVmr8 , "movb", 0, 0) // R8 = [mem] 8A/r -I(MOVmr16 , "movw", 0, 0) // R16 = [mem] 8B/r -I(MOVmr32 , "movl", 0, 0) // R32 = [mem] 8B/r -I(MOVrm8 , "movb", 0, X86II::Void) // [mem] = R8 88/r -I(MOVrm16 , "movw", 0, X86II::Void) // [mem] = R16 89/r -I(MOVrm32 , "movl", 0, X86II::Void) // [mem] = R32 89/r +I(MOVrr8 , "movb", 0x88, 0, X86II::MRMDestReg) // R8 = R8 88/r +I(MOVrr16 , "movw", 0x89, 0, X86II::MRMDestReg) // R16 = R16 89/r +I(MOVrr32 , "movl", 0x89, 0, X86II::MRMDestReg) // R32 = R32 89/r +I(MOVir8 , "movb", 0xB0, 0, X86II::AddRegFrm) // R8 = imm8 B0+ rb +I(MOVir16 , "movw", 0xB8, 0, X86II::AddRegFrm) // R16 = imm16 B8+ rw +I(MOVir32 , "movl", 0xB8, 0, X86II::AddRegFrm) // R32 = imm32 B8+ rd +I(MOVmr8 , "movb", 0x8A, 0, X86II::MRMSrcMem) // R8 = [mem] 8A/r +I(MOVmr16 , "movw", 0x8B, 0, X86II::MRMSrcMem) // R16 = [mem] 8B/r +I(MOVmr32 , "movl", 0x8B, 0, X86II::MRMSrcMem) // R32 = [mem] 8B/r +I(MOVrm8 , "movb", 0x88, 0, X86II::MRMDestMem | X86II::Void) // [mem] = R8 88/r +I(MOVrm16 , "movw", 0x89, 0, X86II::MRMDestMem | X86II::Void) // [mem] = R16 89/r +I(MOVrm32 , "movl", 0x89, 0, X86II::MRMDestMem | X86II::Void) // [mem] = R32 89/r // Arithmetic instructions -I(ADDrr8 , "addb", 0, 0) // R8 += R8 00/r -I(ADDrr16 , "addw", 0, 0) // R16 += R16 01/r -I(ADDrr32 , "addl", 0, 0) // R32 += R32 01/r -I(SUBrr8 , "subb", 0, 0) // R8 -= R8 2A/r -I(SUBrr16 , "subw", 0, 0) // R16 -= R16 2B/r -I(SUBrr32 , "subl", 0, 0) // R32 -= R32 2B/r -I(MULrr8 , "mulb", 0, X86II::Void) // AX = AL*R8 F6/4 -I(MULrr16 , "mulw", 0, X86II::Void) // DX:AX= AX*R16 F7/4 -I(MULrr32 , "mull", 0, X86II::Void) // ED:EA= EA*R32 F7/4 +I(ADDrr8 , "addb", 0x00, 0, X86II::MRMDestReg) // R8 += R8 00/r +I(ADDrr16 , "addw", 0x01, 0, X86II::MRMDestReg) // R16 += R16 01/r +I(ADDrr32 , "addl", 0x01, 0, X86II::MRMDestReg) // R32 += R32 01/r +I(SUBrr8 , "subb", 0x2A, 0, X86II::MRMDestReg) // R8 -= R8 2A/r +I(SUBrr16 , "subw", 0x2B, 0, X86II::MRMDestReg) // R16 -= R16 2B/r +I(SUBrr32 , "subl", 0x2B, 0, X86II::MRMDestReg) // R32 -= R32 2B/r +I(MULrr8 , "mulb", 0xF6, 0, X86II::Void) // AX = AL*R8 F6/4 +I(MULrr16 , "mulw", 0xF7, 0, X86II::Void) // DX:AX= AX*R16 F7/4 +I(MULrr32 , "mull", 0xF7, 0, X86II::Void) // ED:EA= EA*R32 F7/4 // unsigned division/remainder -I(DIVrr8 , "divb", 0, X86II::Void) // AX/r8= AL&AH F6/6 -I(DIVrr16 , "divw", 0, X86II::Void) // DA/r16=AX&DX F7/6 -I(DIVrr32 , "divl", 0, X86II::Void) // DA/r32=EAX&DX F7/6 +I(DIVrr8 , "divb", 0xF6, 0, X86II::Void) // AX/r8= AL&AH F6/6 +I(DIVrr16 , "divw", 0xF7, 0, X86II::Void) // DA/r16=AX&DX F7/6 +I(DIVrr32 , "divl", 0xF7, 0, X86II::Void) // DA/r32=EAX&DX F7/6 // signed division/remainder -I(IDIVrr8 , "idivb", 0, X86II::Void) // AX/r8= AL&AH F6/6 -I(IDIVrr16 , "idivw", 0, X86II::Void) // DA/r16=AX&DX F7/6 -I(IDIVrr32 , "idivl", 0, X86II::Void) // DA/r32=EAX&DX F7/6 +I(IDIVrr8 , "idivb", 0xF6, 0, X86II::Void) // AX/r8= AL&AH F6/6 +I(IDIVrr16 , "idivw", 0xF7, 0, X86II::Void) // DA/r16=AX&DX F7/6 +I(IDIVrr32 , "idivl", 0xF7, 0, X86II::Void) // DA/r32=EAX&DX F7/6 // Logical operators -I(ANDrr8 , "andb", 0, 0) // R8 &= R8 20/r -I(ANDrr16 , "andw", 0, 0) // R16 &= R16 21/r -I(ANDrr32 , "andl", 0, 0) // R32 &= R32 21/r -I(ORrr8 , "orb", 0, 0) // R8 |= R8 08/r -I(ORrr16 , "orw", 0, 0) // R16 |= R16 09/r -I(ORrr32 , "orl", 0, 0) // R32 |= R32 09/r -I(XORrr8 , "xorb", 0, 0) // R8 ^= R8 30/r -I(XORrr16 , "xorw", 0, 0) // R16 ^= R16 31/r -I(XORrr32 , "xorl", 0, 0) // R32 ^= R32 31/r +I(ANDrr8 , "andb", 0x20, 0, X86II::MRMDestReg) // R8 &= R8 20/r +I(ANDrr16 , "andw", 0x21, 0, X86II::MRMDestReg) // R16 &= R16 21/r +I(ANDrr32 , "andl", 0x21, 0, X86II::MRMDestReg) // R32 &= R32 21/r +I(ORrr8 , "orb", 0x08, 0, X86II::MRMDestReg) // R8 |= R8 08/r +I(ORrr16 , "orw", 0x09, 0, X86II::MRMDestReg) // R16 |= R16 09/r +I(ORrr32 , "orl", 0x09, 0, X86II::MRMDestReg) // R32 |= R32 09/r +I(XORrr8 , "xorb", 0x30, 0, X86II::MRMDestReg) // R8 ^= R8 30/r +I(XORrr16 , "xorw", 0x31, 0, X86II::MRMDestReg) // R16 ^= R16 31/r +I(XORrr32 , "xorl", 0x31, 0, X86II::MRMDestReg) // R32 ^= R32 31/r // Shift instructions -I(SHLrr8 , "shlb", 0, 0) // R8 <<= cl D2/4 -I(SHLir8 , "shlb", 0, 0) // R8 <<= imm8 C0/4 ib -I(SHLrr16 , "shlw", 0, 0) // R16 <<= cl D3/4 -I(SHLir16 , "shlw", 0, 0) // R16 <<= imm8 C1/4 ib -I(SHLrr32 , "shll", 0, 0) // R32 <<= cl D3/4 -I(SHLir32 , "shll", 0, 0) // R32 <<= imm8 C1/4 ib -I(SHRrr8 , "shrb", 0, 0) // R8 >>>= cl D2/5 -I(SHRir8 , "shrb", 0, 0) // R8 >>>= imm8 C0/5 ib -I(SHRrr16 , "shrw", 0, 0) // R16 >>>= cl D3/5 -I(SHRir16 , "shrw", 0, 0) // R16 >>>= imm8 C1/5 ib -I(SHRrr32 , "shrl", 0, 0) // R32 >>>= cl D3/5 -I(SHRir32 , "shrl", 0, 0) // R32 >>>= imm8 C1/5 ib -I(SARrr8 , "sarb", 0, 0) // R8 >>= cl D2/7 -I(SARir8 , "sarb", 0, 0) // R8 >>= imm8 C0/7 ib -I(SARrr16 , "sarw", 0, 0) // R16 >>= cl D3/7 -I(SARir16 , "sarw", 0, 0) // R16 >>= imm8 C1/7 ib -I(SARrr32 , "sarl", 0, 0) // R32 >>= cl D3/7 -I(SARir32 , "sarl", 0, 0) // R32 >>= imm8 C1/7 ib +I(SHLrr8 , "shlb", 0xD2, 0, 0) // R8 <<= cl D2/4 +I(SHLrr16 , "shlw", 0xD3, 0, 0) // R16 <<= cl D3/4 +I(SHLrr32 , "shll", 0xD3, 0, 0) // R32 <<= cl D3/4 +I(SHLir8 , "shlb", 0xC0, 0, 0) // R8 <<= imm8 C0/4 ib +I(SHLir16 , "shlw", 0xC1, 0, 0) // R16 <<= imm8 C1/4 ib +I(SHLir32 , "shll", 0xC1, 0, 0) // R32 <<= imm8 C1/4 ib +I(SHRrr8 , "shrb", 0xD2, 0, 0) // R8 >>>= cl D2/5 +I(SHRrr16 , "shrw", 0xD3, 0, 0) // R16 >>>= cl D3/5 +I(SHRrr32 , "shrl", 0xD3, 0, 0) // R32 >>>= cl D3/5 +I(SHRir8 , "shrb", 0xC0, 0, 0) // R8 >>>= imm8 C0/5 ib +I(SHRir16 , "shrw", 0xC1, 0, 0) // R16 >>>= imm8 C1/5 ib +I(SHRir32 , "shrl", 0xC1, 0, 0) // R32 >>>= imm8 C1/5 ib +I(SARrr8 , "sarb", 0xD2, 0, 0) // R8 >>= cl D2/7 +I(SARrr16 , "sarw", 0xD3, 0, 0) // R16 >>= cl D3/7 +I(SARrr32 , "sarl", 0xD3, 0, 0) // R32 >>= cl D3/7 +I(SARir8 , "sarb", 0xC0, 0, 0) // R8 >>= imm8 C0/7 ib +I(SARir16 , "sarw", 0xC1, 0, 0) // R16 >>= imm8 C1/7 ib +I(SARir32 , "sarl", 0xC1, 0, 0) // R32 >>= imm8 C1/7 ib // Floating point loads -I(FLDr4 , "flds", 0, X86II::Void) // push float D9/0 -I(FLDr8 , "fldl ", 0, X86II::Void) // push double DD/0 +I(FLDr4 , "flds", 0xD9, 0, X86II::Void) // push float D9/0 +I(FLDr8 , "fldl ", 0xDD, 0, X86II::Void) // push double DD/0 // Floating point compares -I(FUCOMPP , "fucompp", 0, X86II::Void) // compare+pop2x DA E9 +I(FUCOMPP , "fucompp", 0xDA, 0, X86II::Void) // compare+pop2x DA E9 // Floating point flag ops -I(FNSTSWr8 , "fnstsw", 0, X86II::Void) // AX = fp flags DF E0 +I(FNSTSWr8 , "fnstsw", 0xDF, 0, X86II::Void) // AX = fp flags DF E0 // Condition code ops, incl. set if equal/not equal/... -I(SAHF , "sahf", 0, 0) // flags = AH 9E -I(SETA , "seta", 0, X86II::TB) // R8 = > unsign 0F 97 -I(SETAE , "setae", 0, X86II::TB) // R8 = >=unsign 0F 93 -I(SETB , "setb", 0, X86II::TB) // R8 = < unsign 0F 92 -I(SETBE , "setbe", 0, X86II::TB) // R8 = <=unsign 0F 96 -I(SETE , "sete", 0, X86II::TB) // R8 = == 0F 94 -I(SETG , "setg", 0, X86II::TB) // R8 = > signed 0F 9F -I(SETGE , "setge", 0, X86II::TB) // R8 = >=signed 0F 9D -I(SETL , "setl", 0, X86II::TB) // R8 = < signed 0F 9C -I(SETLE , "setle", 0, X86II::TB) // R8 = <=signed 0F 9E -I(SETNE , "setne", 0, X86II::TB) // R8 = != 0F 95 +I(SAHF , "sahf", 0x9E, 0, 0) // flags = AH 9E +I(SETA , "seta", 0x97, 0, X86II::TB) // R8 = > unsign 0F 97 +I(SETAE , "setae", 0x93, 0, X86II::TB) // R8 = >=unsign 0F 93 +I(SETB , "setb", 0x92, 0, X86II::TB) // R8 = < unsign 0F 92 +I(SETBE , "setbe", 0x96, 0, X86II::TB) // R8 = <=unsign 0F 96 +I(SETE , "sete", 0x94, 0, X86II::TB) // R8 = == 0F 94 +I(SETG , "setg", 0x9F, 0, X86II::TB) // R8 = > signed 0F 9F +I(SETGE , "setge", 0x9D, 0, X86II::TB) // R8 = >=signed 0F 9D +I(SETL , "setl", 0x9C, 0, X86II::TB) // R8 = < signed 0F 9C +I(SETLE , "setle", 0x9E, 0, X86II::TB) // R8 = <=signed 0F 9E +I(SETNE , "setne", 0x95, 0, X86II::TB) // R8 = != 0F 95 // Integer comparisons -I(CMPrr8 , "cmpb", 0, 0) // compare R8,R8 38/r -I(CMPrr16 , "cmpw", 0, 0) // compare R16,R16 39/r -I(CMPrr32 , "cmpl", 0, 0) // compare R32,R32 39/r +I(CMPrr8 , "cmpb", 0x38, 0, X86II::MRMDestReg) // compare R8,R8 38/r +I(CMPrr16 , "cmpw", 0x39, 0, X86II::MRMDestReg) // compare R16,R16 39/r +I(CMPrr32 , "cmpl", 0x39, 0, X86II::MRMDestReg) // compare R32,R32 39/r // Sign extenders (first 3 are good for DIV/IDIV; the others are more general) -I(CBW , "cbw", 0, 0) // AX = signext(AL) 98 -I(CWD , "cwd", 0, 0) // DX:AX = signext(AX) 99 -I(CDQ , "cdq", 0, 0) // EDX:EAX = signext(EAX) 99 -I(MOVSXr16r8 , "movsx", 0, X86II::TB) // R32 = signext(R8) 0F BE /r -I(MOVSXr32r8 , "movsx", 0, X86II::TB) // R32 = signext(R8) 0F BE /r -I(MOVSXr32r16 , "movsx", 0, X86II::TB) // R32 = signext(R16) 0F BF /r -I(MOVZXr16r8 , "movzx", 0, X86II::TB) // R32 = zeroext(R8) 0F B6 /r -I(MOVZXr32r8 , "movzx", 0, X86II::TB) // R32 = zeroext(R8) 0F B6 /r -I(MOVZXr32r16 , "movzx", 0, X86II::TB) // R32 = zeroext(R16) 0F B7 /r +I(CBW , "cbw", 0x98, 0, X86II::RawFrm) // AX = signext(AL) +I(CWD , "cwd", 0x99, 0, X86II::RawFrm) // DX:AX = signext(AX) +I(CDQ , "cdq", 0x99, 0, X86II::RawFrm) // EDX:EAX = signext(EAX) +I(MOVSXr16r8 , "movsx", 0xBE, 0, X86II::MRMSrcReg | X86II::TB) // R32 = signext(R8) 0F BE /r +I(MOVSXr32r8 , "movsx", 0xBE, 0, X86II::MRMSrcReg | X86II::TB) // R32 = signext(R8) 0F BE /r +I(MOVSXr32r16 , "movsx", 0xBF, 0, X86II::MRMSrcReg | X86II::TB) // R32 = signext(R16) 0F BF /r +I(MOVZXr16r8 , "movzx", 0xB6, 0, X86II::MRMSrcReg | X86II::TB) // R32 = zeroext(R8) 0F B6 /r +I(MOVZXr32r8 , "movzx", 0xB6, 0, X86II::MRMSrcReg | X86II::TB) // R32 = zeroext(R8) 0F B6 /r +I(MOVZXr32r16 , "movzx", 0xB7, 0, X86II::MRMSrcReg | X86II::TB) // R32 = zeroext(R16) 0F B7 /r // At this point, I is dead, so undefine the macro #undef I diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index 43f24e66084..415d81a05cf 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -15,14 +15,55 @@ /// namespace X86II { enum { + //===------------------------------------------------------------------===// + // Instruction types. These are the standard/most common forms for X86 + // instructions. + // + + /// Other - An instruction gets this form if it doesn't fit any of the + /// catagories below. + OtherFrm = 0, + + /// Raw - This form is for instructions that don't have any operands, so + /// they are just a fixed opcode value, like 'leave'. + RawFrm = 1, + + /// AddRegFrm - This form is used for instructions like 'push r32' that have + /// their one register operand added to their opcode. + AddRegFrm = 2, + + /// MRMDestReg - This form is used for instructions that use the Mod/RM byte + /// to specify a destination, which in this case is a register. + /// + MRMDestReg = 3, + + /// MRMDestMem - This form is used for instructions that use the Mod/RM byte + /// to specify a destination, which in this case is memory. + /// + MRMDestMem = 4, + + /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte + /// to specify a source, which in this case is a register. + /// + MRMSrcReg = 5, + + /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte + /// to specify a source, which in this case is memory. + /// + MRMSrcMem = 6, + + /// TODO: Mod/RM that uses a fixed opcode extension, like /0 + + + //===------------------------------------------------------------------===// + // Actual flags... + /// Void - Set if this instruction produces no value - Void = 1 << 0, + Void = 1 << 3, // TB - TwoByte - Set if this instruction has a two byte opcode, which // starts with a 0x0F byte before the real opcode. - TB = 1 << 1, - - + TB = 1 << 4, }; } -- 2.34.1