From 6aebfdaedd8b486ea70fe84898268e4682aa2f64 Mon Sep 17 00:00:00 2001
From: Randy Li <randy.li@rock-chips.com>
Date: Mon, 31 Oct 2016 18:16:38 +0800
Subject: [PATCH] ARM: dts: rockchip: add hevc vpu service for rk3288

Change-Id: I87a8c9df636e04b92948c87c27e82b43a67de184
Signed-off-by: Randy Li <randy.li@rock-chips.com>
---
 arch/arm/boot/dts/rk3288.dtsi | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 99bce3b994eb..7e65b167ab1e 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1099,6 +1099,35 @@
 		#iommu-cells = <0>;
 	};
 
+	hevc_service: hevc-service@ff9c0000 {
+		compatible = "rockchip,hevc_service";
+		reg = <0xff9c0000 0x400>;
+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_dec";
+		clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+			<&cru SCLK_HEVC_CORE>,
+			<&cru SCLK_HEVC_CABAC>;
+		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
+			"clk_cabac";
+		resets = <&cru SRST_HEVC>;
+		reset-names = "video";
+		power-domains = <&power RK3288_PD_HEVC>;
+		rockchip,grf = <&grf>;
+		dev_mode = <1>;
+		iommus = <&hevc_mmu>;
+		iommu_enabled = <1>;
+		status = "disabled";
+	};
+
+	hevc_mmu: iommu@ff9c0440 {
+		compatible = "rockchip,iommu";
+		reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
+		interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hevc_mmu";
+		power-domains = <&power RK3288_PD_HEVC>;
+		#iommu-cells = <0>;
+	};
+
 	gic: interrupt-controller@ffc01000 {
 		compatible = "arm,gic-400";
 		interrupt-controller;
-- 
2.34.1