From 6b7ef38e47c4cbb2d4da68fdba09dc885e076edb Mon Sep 17 00:00:00 2001 From: cym Date: Mon, 6 May 2013 11:26:24 +0800 Subject: [PATCH] RK3188:ddr_get_dpll_status only use for RK3188 --- arch/arm/mach-rk30/ddr.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-rk30/ddr.c b/arch/arm/mach-rk30/ddr.c index 6b8ea14c509c..cd242744d867 100755 --- a/arch/arm/mach-rk30/ddr.c +++ b/arch/arm/mach-rk30/ddr.c @@ -3391,8 +3391,9 @@ void __sramlocalfunc ddr_set_pll_exit_3168(uint32 freq_slew,uint32_t dqstr_value } #endif +static bool ddr_dpll_status = true; +#if defined(CONFIG_ARCH_RK3188) extern int efuse_readregs(u32 addr, u32 length, u8 *pData); -bool ddr_dpll_status = true; void ddr_get_dpll_status(void) //DPLL fial rerurn 0;DPLL good return 1; { uint8_t data_buf[32 + 1]; @@ -3403,7 +3404,7 @@ void ddr_get_dpll_status(void) //DPLL fial rerurn 0;DPLL good return 1; else ddr_dpll_status = true; } - +#endif uint32_t __sramfunc ddr_change_freq_sram(uint32_t nMHz) { @@ -3807,8 +3808,9 @@ int ddr_init(uint32_t dram_speed_bin, uint32_t freq) uint32_t gsr,dqstr; ddr_print("version 1.00 20130427 \n"); +#if defined(CONFIG_ARCH_RK3188) ddr_get_dpll_status(); - +#endif mem_type = pPHY_Reg->DCR.b.DDRMD; ddr_speed_bin = dram_speed_bin; -- 2.34.1