From 6ba48050ccbe08b1e94550b762d6cdb978228ad7 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Heiko=20St=C3=BCbner?= Date: Wed, 29 Jun 2016 14:44:50 +0800 Subject: [PATCH] FROMLIST: clk: rockchip: add clock flag parameter when register pll MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit add clock flag parameter so we can pass specific clock flag (like CLK_GET_RATE_NOCACHE etc..)to pll driver. Change-Id: I1e076b3efa6b5da082b6e68e2e2a4c9dfd93e3d4 Signed-off-by: Heiko Stübner Signed-off-by: Lin Huang --- drivers/clk/rockchip/clk-pll.c | 4 ++-- drivers/clk/rockchip/clk.c | 2 +- drivers/clk/rockchip/clk.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 5f1edeedd17f..ddaf6ecdea3d 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -1224,7 +1224,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, u8 num_parents, int con_offset, int grf_lock_offset, int lock_shift, int mode_offset, int mode_shift, struct rockchip_pll_rate_table *rate_table, - u8 clk_pll_flags) + unsigned long flags, u8 clk_pll_flags) { const char *pll_parents[3]; struct clk_init_data init; @@ -1280,7 +1280,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, init.name = pll_name; /* keep all plls untouched for now */ - init.flags = CLK_IGNORE_UNUSED; + init.flags = flags | CLK_IGNORE_UNUSED; init.parent_names = &parent_names[0]; init.num_parents = 1; diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 277f9270bf72..8e1f270ad81e 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -391,7 +391,7 @@ void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, list->con_offset, grf_lock_offset, list->lock_shift, list->mode_offset, list->mode_shift, list->rate_table, - list->pll_flags); + list->flags, list->pll_flags); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, list->name); diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 68d357fd16d0..12616a788172 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -242,7 +242,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, u8 num_parents, int con_offset, int grf_lock_offset, int lock_shift, int mode_offset, int mode_shift, struct rockchip_pll_rate_table *rate_table, - u8 clk_pll_flags); + unsigned long flags, u8 clk_pll_flags); struct rockchip_cpuclk_clksel { int reg; -- 2.34.1