From 6c77fdda35688ae3c9d9029a9824f7cf941f348d Mon Sep 17 00:00:00 2001 From: Chris Fries Date: Fri, 11 Feb 2011 14:26:20 -0600 Subject: [PATCH] [ARM] tegra: Enable pl310 data prefetching and prefetch offset Enable data prefetching in the L2 cache controller, and set the prefetch offset to 7. Memcpy performance measured copying 16 MB buffers 78 times: Data prefetch disabled, prefetch offset 0: 440 MB/s Enabling data prefetching, prefetch offset 0: 430 MB/s Enabling data prefetching, prefetch offset 7: 502 MB/s Overall, this patch gives a 14% improvement in memcpy performance. Prefetch offset of 8 causes prefetches to cross 4k boundaries and cannot be used. Original-author: Gary King Signed-off-by: Chris Fries Signed-off-by: Colin Cross Change-Id: I7ce0810b3f94edc2640df3f643cf81357052f2f1 --- arch/arm/mach-tegra/common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index a4b72dca2303..5283a17f3d2b 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -88,8 +88,9 @@ void __init tegra_init_cache(void) writel(0x331, p + L2X0_TAG_LATENCY_CTRL); writel(0x441, p + L2X0_DATA_LATENCY_CTRL); + writel(7, p + L2X0_PREFETCH_OFFSET); - l2x0_init(p, 0x6C480001, 0x8200c3fe); + l2x0_init(p, 0x7C480001, 0x8200c3fe); #endif } -- 2.34.1