From 6edcb1a60455368804d56913cc1fd34983bffe44 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Tue, 18 Feb 2014 18:34:00 +0800 Subject: [PATCH] ARM: rockchip: iomap.h add more rk3288 define --- arch/arm/mach-rockchip/iomap.h | 139 ++++++++++++++++++++++----------- 1 file changed, 93 insertions(+), 46 deletions(-) diff --git a/arch/arm/mach-rockchip/iomap.h b/arch/arm/mach-rockchip/iomap.h index d515f5f2dd77..fe9b26614844 100644 --- a/arch/arm/mach-rockchip/iomap.h +++ b/arch/arm/mach-rockchip/iomap.h @@ -5,54 +5,101 @@ #include #endif -#define RK_IO_ADDRESS(x) IOMEM(0xFED00000 + x) +#define RK_IO_ADDRESS(x) IOMEM(0xFED00000 + x) -#define RK_CRU_VIRT RK_IO_ADDRESS(0x00000000) -#define RK_GRF_VIRT RK_IO_ADDRESS(0x00010000) -#define RK_PMU_VIRT RK_IO_ADDRESS(0x00020000) -#define RK_ROM_VIRT RK_IO_ADDRESS(0x00030000) -#define RK_EFUSE_VIRT RK_IO_ADDRESS(0x00040000) -#define RK_GPIO_VIRT(n) RK_IO_ADDRESS(0x00050000 + (n) * 0x1000) -#define RK_DEBUG_UART_VIRT RK_IO_ADDRESS(0x00060000) -#define RK_CPU_AXI_BUS_VIRT RK_IO_ADDRESS(0x00070000) -#define RK_TIMER_VIRT RK_IO_ADDRESS(0x00080000) -#define RK_DDR_VIRT RK_IO_ADDRESS(0x000d0000) +#define RK_CRU_VIRT RK_IO_ADDRESS(0x00000000) +#define RK_GRF_VIRT RK_IO_ADDRESS(0x00010000) +#define RK_PMU_VIRT RK_IO_ADDRESS(0x00020000) +#define RK_ROM_VIRT RK_IO_ADDRESS(0x00030000) +#define RK_EFUSE_VIRT RK_IO_ADDRESS(0x00040000) +#define RK_GPIO_VIRT(n) RK_IO_ADDRESS(0x00050000 + (n) * 0x1000) +#define RK_DEBUG_UART_VIRT RK_IO_ADDRESS(0x00060000) +#define RK_CPU_AXI_BUS_VIRT RK_IO_ADDRESS(0x00070000) +#define RK_TIMER_VIRT RK_IO_ADDRESS(0x00080000) +#define RK_DDR_VIRT RK_IO_ADDRESS(0x000d0000) -#define RK3188_CRU_PHYS 0x20000000 -#define RK3188_CRU_SIZE SZ_4K -#define RK3188_GRF_PHYS 0x20008000 -#define RK3188_GRF_SIZE SZ_4K -#define RK3188_PMU_PHYS 0x20004000 -#define RK3188_PMU_SIZE SZ_4K -#define RK3188_ROM_PHYS 0x10120000 -#define RK3188_ROM_SIZE SZ_16K -#define RK3188_EFUSE_PHYS 0x20010000 -#define RK3188_EFUSE_SIZE SZ_4K -#define RK3188_GPIO0_PHYS 0x2000a000 -#define RK3188_GPIO1_PHYS 0x2003c000 -#define RK3188_GPIO2_PHYS 0x2003e000 -#define RK3188_GPIO3_PHYS 0x20080000 -#define RK3188_GPIO_SIZE SZ_4K -#define RK3188_CPU_AXI_BUS_PHYS 0x10128000 -#define RK3188_CPU_AXI_BUS_SIZE SZ_32K -#define RK3188_TIMER0_PHYS 0x20038000 -#define RK3188_TIMER3_PHYS 0x2000e000 -#define RK3188_TIMER_SIZE SZ_4K -#define RK3188_DDR_PCTL_PHYS 0x20020000 -#define RK3188_DDR_PCTL_SIZE SZ_16K -#define RK3188_DDR_PUBL_PHYS 0x20040000 -#define RK3188_DDR_PUBL_SIZE SZ_16K -#define RK3188_UART0_PHYS 0x10124000 -#define RK3188_UART1_PHYS 0x10126000 -#define RK3188_UART2_PHYS 0x20064000 -#define RK3188_UART3_PHYS 0x20068000 -#define RK3188_UART_SIZE SZ_4K +#define RK3188_CRU_PHYS 0x20000000 +#define RK3188_CRU_SIZE SZ_4K +#define RK3188_GRF_PHYS 0x20008000 +#define RK3188_GRF_SIZE SZ_4K +#define RK3188_PMU_PHYS 0x20004000 +#define RK3188_PMU_SIZE SZ_4K +#define RK3188_ROM_PHYS 0x10120000 +#define RK3188_ROM_SIZE SZ_16K +#define RK3188_EFUSE_PHYS 0x20010000 +#define RK3188_EFUSE_SIZE SZ_4K +#define RK3188_GPIO0_PHYS 0x2000a000 +#define RK3188_GPIO1_PHYS 0x2003c000 +#define RK3188_GPIO2_PHYS 0x2003e000 +#define RK3188_GPIO3_PHYS 0x20080000 +#define RK3188_GPIO_SIZE SZ_4K +#define RK3188_CPU_AXI_BUS_PHYS 0x10128000 +#define RK3188_CPU_AXI_BUS_SIZE SZ_32K +#define RK3188_TIMER0_PHYS 0x20038000 +#define RK3188_TIMER3_PHYS 0x2000e000 +#define RK3188_TIMER_SIZE SZ_4K +#define RK3188_DDR_PCTL_PHYS 0x20020000 +#define RK3188_DDR_PCTL_SIZE SZ_4K +#define RK3188_DDR_PUBL_PHYS 0x20040000 +#define RK3188_DDR_PUBL_SIZE SZ_4K +#define RK3188_UART0_PHYS 0x10124000 +#define RK3188_UART1_PHYS 0x10126000 +#define RK3188_UART2_PHYS 0x20064000 +#define RK3188_UART3_PHYS 0x20068000 +#define RK3188_UART_SIZE SZ_4K -#define RK3288_UART_BT_PHYS 0xff180000 -#define RK3288_UART_BB_PHYS 0xff190000 -#define RK3288_UART_DBG_PHYS 0xff690000 -#define RK3288_UART_GPS_PHYS 0xff1b0000 -#define RK3288_UART_EXP_PHYS 0xff1c0000 -#define RK3288_UART_SIZE SZ_4K +#define RK3288_CRU_PHYS 0xFF760000 +#define RK3288_CRU_SIZE SZ_4K +#define RK3288_GRF_PHYS 0xFF770000 +#define RK3288_GRF_SIZE SZ_4K +#define RK3288_SGRF_PHYS 0xFF740000 +#define RK3288_SGRF_SIZE SZ_4K +#define RK3288_PMU_PHYS 0xFF730000 +#define RK3288_PMU_SIZE SZ_4K +#define RK3288_ROM_PHYS 0xFFFD0000 +#define RK3288_ROM_SIZE (SZ_16K + SZ_4K) +#define RK3288_EFUSE_PHYS 0xFFB40000 +#define RK3288_EFUSE_SIZE SZ_4K +#define RK3288_GPIO0_PHYS 0xFF750000 +#define RK3288_GPIO1_PHYS 0xFF780000 +#define RK3288_GPIO2_PHYS 0xFF790000 +#define RK3288_GPIO3_PHYS 0xFF7A0000 +#define RK3288_GPIO4_PHYS 0xFF7B0000 +#define RK3288_GPIO5_PHYS 0xFF7C0000 +#define RK3288_GPIO6_PHYS 0xFF7D0000 +#define RK3288_GPIO7_PHYS 0xFF7E0000 +#define RK3288_GPIO8_PHYS 0xFF7F0000 +#define RK3288_GPIO_SIZE SZ_4K +#define RK3288_SERVICE_CORE_PHYS 0XFFA80000 +#define RK3288_SERVICE_CORE_SIZE SZ_4K +#define RK3288_SERVICE_DMAC_PHYS 0XFFA90000 +#define RK3288_SERVICE_DMAC_SIZE SZ_4K +#define RK3288_SERVICE_GPU_PHYS 0XFFAA0000 +#define RK3288_SERVICE_GPU_SIZE SZ_4K +#define RK3288_SERVICE_PERI_PHYS 0XFFAB0000 +#define RK3288_SERVICE_PERI_SIZE SZ_4K +#define RK3288_SERVICE_BUS_PHYS 0XFFAC0000 +#define RK3288_SERVICE_BUS_SIZE SZ_16K +#define RK3288_SERVICE_VIO_PHYS 0XFFAD0000 +#define RK3288_SERVICE_VIO_SIZE SZ_4K +#define RK3288_SERVICE_VPU_PHYS 0XFFAE0000 +#define RK3288_SERVICE_VPU_SIZE SZ_4K +#define RK3288_SERVICE_HEVC_PHYS 0XFFAF0000 +#define RK3288_SERVICE_HEVC_SIZE SZ_4K +#define RK3288_TIMER0_PHYS 0xFF6B0000 +#define RK3288_TIMER6_PHYS 0xFF810000 +#define RK3288_TIMER_SIZE SZ_4K +#define RK3288_DDR_PCTL0_PHYS 0xFF610000 +#define RK3288_DDR_PCTL1_PHYS 0xFF630000 +#define RK3288_DDR_PCTL_SIZE SZ_4K +#define RK3288_DDR_PUBL0_PHYS 0xFF620000 +#define RK3288_DDR_PUBL1_PHYS 0xFF640000 +#define RK3288_DDR_PUBL_SIZE SZ_4K +#define RK3288_UART_BT_PHYS 0xFF180000 +#define RK3288_UART_BB_PHYS 0xFF190000 +#define RK3288_UART_DBG_PHYS 0xFF690000 +#define RK3288_UART_GPS_PHYS 0xFF1B0000 +#define RK3288_UART_EXP_PHYS 0xFF1C0000 +#define RK3288_UART_SIZE SZ_4K #endif -- 2.34.1