From 6f2a45a957083e44e60785dc4b217d8070d2e344 Mon Sep 17 00:00:00 2001 From: "wenping.zhang" Date: Mon, 17 Oct 2016 10:30:13 +0800 Subject: [PATCH] arm64: dts: rockchip: add reset control registers for rk3399 dp driver. Change-Id: Ibbad2bd5ab49c71385045ca743740cbba8ed6bf0 Signed-off-by: wenping.zhang --- arch/arm64/boot/dts/rockchip/rk3399-android.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi index 06393a2f4000..83ed035d4b41 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi @@ -167,14 +167,15 @@ reg = <0x0 0xfec00000 0x0 0x100000>; interrupts = ; clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, - <&cru SCLK_SPDIF_REC_DPTX>; - clock-names = "core-clk", "pclk", "spdif"; + <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; + clock-names = "core-clk", "pclk", "spdif", "grf"; assigned-clocks = <&cru SCLK_DP_CORE>; assigned-clock-rates = <100000000>; power-domains = <&power RK3399_PD_HDCP>; phys = <&tcphy0_dp>, <&tcphy1_dp>; - resets = <&cru SRST_DPTX_SPDIF_REC>; - reset-names = "spdif"; + resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, + <&cru SRST_P_UPHY0_APB>; + reset-names = "spdif", "dptx", "apb"; rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <0>; -- 2.34.1