From 70f85730b199839891166b2a0acff126d1cc7c12 Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Fri, 7 Jan 2011 23:40:46 +0000 Subject: [PATCH] Add an explanatory message for an assertion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123042 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMISelLowering.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 38daeaa5bbd..9ecc8714917 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -3715,7 +3715,8 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, SelectionDAG &DAG) con // Since only 64-bit and 128-bit vectors are legal on ARM and // we've eliminated the other cases... - assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts); + assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts && + "unexpected vector sizes in ReconstructShuffle"); if (MaxElts[i] - MinElts[i] >= NumElts) { // Span too large for a VEXT to cope -- 2.34.1