From 725088ece4f1be61155da66fefbc65400212fed1 Mon Sep 17 00:00:00 2001 From: yxj Date: Fri, 19 Apr 2013 21:50:22 +0800 Subject: [PATCH] mfd:rk616:dhmi:fix register msk bug --- .../rockchip/hdmi/chips/rk616/rk616_hdmi.c | 8 ++- .../rockchip/hdmi/chips/rk616/rk616_hdmi_hw.c | 17 +++--- .../rockchip/hdmi/chips/rk616/rk616_hdmi_hw.h | 54 ++++++++++--------- 3 files changed, 46 insertions(+), 33 deletions(-) diff --git a/drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi.c b/drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi.c index 12edee746db0..b901a22bf3b7 100755 --- a/drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi.c +++ b/drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi.c @@ -37,6 +37,10 @@ extern void hdmi_register_display_sysfs(struct hdmi *hdmi, struct device *parent extern void hdmi_unregister_display_sysfs(struct hdmi *hdmi); +int set_hdmi_status(void) +{ + hdmi->hotplug = HDMI_HPD_ACTIVED; +} #if defined(CONFIG_DEBUG_FS) static int rk616_hdmi_reg_show(struct seq_file *s, void *v) @@ -52,8 +56,8 @@ static int rk616_hdmi_reg_show(struct seq_file *s, void *v) for(i=0;i<= (PHY_PRE_DIV_RATIO << 2);i+=4) { - rk616->read_dev(rk616,i,&val); - seq_printf(s,"reg%02x>>0x%08x\n",i>>2,val); + rk616->read_dev(rk616,RK616_HDMI_BASE + i,&val); + seq_printf(s,"reg%02x>>0x%08x\n",(i>>2),val); } return 0; diff --git a/drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi_hw.c b/drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi_hw.c index dca27eb0abfc..ab2d2031d798 100755 --- a/drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi_hw.c +++ b/drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi_hw.c @@ -428,8 +428,7 @@ irqreturn_t hdmi_irq(int irq, void *priv) HDMIRdReg(INTERRUPT_STATUS1,&interrupt1); HDMIWrReg(INTERRUPT_STATUS1, interrupt1); #if 1 - hdmi_dbg(hdmi->dev, "[%s] interrupt1 %02x \n",\ - __FUNCTION__, interrupt1); + hdmi_dbg(hdmi->dev,"[%s] interrupt1 %02x\n",__func__, interrupt1); #endif if(interrupt1 & m_INT_HOTPLUG ){ if(hdmi->state == HDMI_SLEEP) @@ -453,13 +452,16 @@ irqreturn_t hdmi_irq(int irq, void *priv) static void rk616_hdmi_reset(void) { - char val = 0; - val = v_REG_CLK_INV| v_VCLK_INV |v_REG_CLK_SOURCE_SYS|v_PWR_ON |v_INT_POL_LOW; - HDMIWrReg(SYS_CTRL,val); + u32 val = 0; + u32 msk = 0; + + HDMIMskReg(SYS_CTRL,m_RST_DIGITAL,v_NOT_RST_DIGITAL); delay100us(); HDMIMskReg(SYS_CTRL,m_RST_ANALOG,v_NOT_RST_ANALOG); delay100us(); - HDMIMskReg(SYS_CTRL,m_RST_DIGITAL,v_NOT_RST_DIGITAL); + msk = m_REG_CLK_INV | m_VCLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL; + val = v_REG_CLK_INV| v_VCLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON |v_INT_POL_LOW; + HDMIMskReg(SYS_CTRL,msk,val); rk616_hdmi_set_pwr_mode(LOWER_PWR); } @@ -476,7 +478,8 @@ int rk616_hdmi_initial(void) hdmi->read_edid = rk616_hdmi_read_edid; rk616_hdmi_reset(); - //rk616_hdmi_init_pol_set(g_rk616_hdmi,0); + + rk616_hdmi_init_pol_set(g_rk616_hdmi,0); if(hdmi->hdcp_power_on_cb) rc = hdmi->hdcp_power_on_cb(); diff --git a/drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi_hw.h b/drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi_hw.h index 11ca16dedf2d..dc8d65a15db0 100755 --- a/drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi_hw.h +++ b/drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi_hw.h @@ -10,28 +10,32 @@ enum { OUTPUT_DVI = 0, OUTPUT_HDMI }; -#define SYS_CTRL 0x00 - #define m_RST_ANALOG (1<<6) - #define v_RST_ANALOG (0<<6) - #define v_NOT_RST_ANALOG (0<<6) - #define m_RST_DIGITAL (1<<5) - #define v_RST_DIGITAL (0<<5) - #define v_NOT_RST_DIGITAL (1<<5) - #define m_REG_CLK_INV (1<<4) - #define v_REG_CLK_NOT_INV (0<<4) - #define v_REG_CLK_INV (1<<4) - #define m_VCLK_INV (1<<3) - #define v_VCLK_NOT_INV (0<<3) - #define v_VCLK_INV (0<<3) - #define m_REG_CLK_SOURCE (1<<2) - #define v_REG_CLK_SOURCE_TMDS (0<<2) - #define v_REG_CLK_SOURCE_SYS (1<<2) - #define m_POWER (1<<1) - #define v_PWR_ON (0<<1) - #define v_PWR_OFF (1<<1) - #define m_INT_POL (1<<0) - #define v_INT_POL_HIGH 1 - #define v_INT_POL_LOW 0 + +#define SYS_CTRL 0x00 +#define m_RST_ANALOG (1<<6) +#define v_RST_ANALOG (0<<6) +#define v_NOT_RST_ANALOG (1<<6) + +#define m_RST_DIGITAL (1<<5) +#define v_RST_DIGITAL (0<<5) +#define v_NOT_RST_DIGITAL (1<<5) + +#define m_REG_CLK_INV (1<<4) +#define v_REG_CLK_NOT_INV (0<<4) +#define v_REG_CLK_INV (1<<4) +#define m_VCLK_INV (1<<3) +#define v_VCLK_NOT_INV (0<<3) +#define v_VCLK_INV (1<<3) +#define m_REG_CLK_SOURCE (1<<2) +#define v_REG_CLK_SOURCE_TMDS (0<<2) +#define v_REG_CLK_SOURCE_SYS (1<<2) +#define m_POWER (1<<1) +#define v_PWR_ON (0<<1) +#define v_PWR_OFF (1<<1) +#define m_INT_POL (1<<0) +#define v_INT_POL_HIGH 1 +#define v_INT_POL_LOW 0 + #define VIDEO_CONTRL1 0x01 #define m_VIDEO_INPUT_FORMAT (7 << 1) @@ -234,7 +238,7 @@ enum { #define v_TMDS_FROM_GEN (1<<5) #define m_PHASE_CLK (1<<4) #define v_DEFAULT_PHASE (0<<4) - #define v_SYNC_PHASE (0<<4) + #define v_SYNC_PHASE (1<<4) #define m_TMDS_CURRENT_PWR (1<<3) #define v_TURN_ON_CURRENT (0<<3) #define v_CAT_OFF_CURRENT (1<<3) @@ -277,9 +281,11 @@ enum { }while(0) #define HDMIMskReg(addr,Msk,val) do{ \ + u32 tkv = 0;\ u32 temp=0; \ HDMIRdReg(addr,&temp); \ - HDMIWrReg(addr, ((val)&(Msk))|(temp&(~Msk))); \ + tkv = ((val)&(Msk))|(temp&(~Msk)); \ + HDMIWrReg(addr,tkv); \ }while(0) extern struct mfd_rk616 *g_rk616_hdmi; -- 2.34.1