From 735b2ce1dd396379ecd4cb968b5c9f1902876692 Mon Sep 17 00:00:00 2001 From: xxx Date: Tue, 1 Jul 2014 16:58:51 +0800 Subject: [PATCH] add:ddr reg dump,resume code data align --- arch/arm/mach-rockchip/pm-rk3288.c | 24 ++++++++++++++++-------- arch/arm/mach-rockchip/sleep.S | 3 ++- 2 files changed, 18 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-rockchip/pm-rk3288.c b/arch/arm/mach-rockchip/pm-rk3288.c index 86fe55a9eca2..850cf0edf684 100755 --- a/arch/arm/mach-rockchip/pm-rk3288.c +++ b/arch/arm/mach-rockchip/pm-rk3288.c @@ -1269,14 +1269,22 @@ static void rkpm_save_setting_resume_first(void) static void rkpm_save_setting(u32 ctrbits) { - rk3288_powermode=rkpm_slp_mode_set(ctrbits); - if(rk3288_powermode&BIT(pmu_pwr_mode_en)) - { - sram_code_data_save(rk3288_powermode); - rkpm_peri_save(rk3288_powermode); - } - else - return ; + +#if 0 + rkpm_ddr_regs_dump(RK_DDR_VIRT,0,0x3fc); + rkpm_ddr_regs_dump(RK_DDR_VIRT+RK3288_DDR_PCTL_SIZE,0,0x294); + + rkpm_ddr_regs_dump(RK_DDR_VIRT+RK3288_DDR_PCTL_SIZE+RK3288_DDR_PUBL_SIZE,0,0x3fc); + rkpm_ddr_regs_dump(RK_DDR_VIRT+RK3288_DDR_PCTL_SIZE*2+RK3288_DDR_PUBL_SIZE,0,0x294); +#endif + rk3288_powermode=rkpm_slp_mode_set(ctrbits); + if(rk3288_powermode&BIT(pmu_pwr_mode_en)) + { + sram_code_data_save(rk3288_powermode); + rkpm_peri_save(rk3288_powermode); + } + else + return ; } static void rkpm_save_setting_resume(void) diff --git a/arch/arm/mach-rockchip/sleep.S b/arch/arm/mach-rockchip/sleep.S index 1839b5d598b9..40e3c8c46303 100755 --- a/arch/arm/mach-rockchip/sleep.S +++ b/arch/arm/mach-rockchip/sleep.S @@ -18,7 +18,8 @@ ldmfd sp!, { r3 - r12, pc } ENDPROC(rkpm_slp_cpu_while_tst) - +.data +.align //65 A 48 0 97 a ENTRY(rkpm_slp_cpu_resume) 9: mov r1,r1 -- 2.34.1