From 7548a540f74be48b3d900134e7220155aab1703a Mon Sep 17 00:00:00 2001
From: Brian Gaeke <gaeke@uiuc.edu>
Date: Thu, 24 Jun 2004 06:44:57 +0000
Subject: [PATCH] Strange as it may sound, we'll not use LDD/STD to store
 longs. For reasons of representational consistency, we want to address the
 halves of each 64-bit value separately.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14356 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Sparc/InstSelectSimple.cpp    | 6 ++++--
 lib/Target/Sparc/SparcV8ISelSimple.cpp   | 6 ++++--
 lib/Target/SparcV8/InstSelectSimple.cpp  | 6 ++++--
 lib/Target/SparcV8/SparcV8ISelSimple.cpp | 6 ++++--
 4 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/lib/Target/Sparc/InstSelectSimple.cpp b/lib/Target/Sparc/InstSelectSimple.cpp
index e25a73c6ae2..bef5002160e 100644
--- a/lib/Target/Sparc/InstSelectSimple.cpp
+++ b/lib/Target/Sparc/InstSelectSimple.cpp
@@ -546,7 +546,8 @@ void V8ISel::visitLoadInst(LoadInst &I) {
     BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
     return;
    case cLong:
-    BuildMI (BB, V8::LDDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
+    BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
+    BuildMI (BB, V8::LDmr, 1, DestReg+1).addReg (PtrReg).addSImm(4);
     return;
    default:
     std::cerr << "Load instruction not handled: " << I;
@@ -570,7 +571,8 @@ void V8ISel::visitStoreInst(StoreInst &I) {
     BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
     return;
    case cLong:
-    BuildMI (BB, V8::STDrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
+    BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
+    BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
     return;
    default:
     std::cerr << "Store instruction not handled: " << I;
diff --git a/lib/Target/Sparc/SparcV8ISelSimple.cpp b/lib/Target/Sparc/SparcV8ISelSimple.cpp
index e25a73c6ae2..bef5002160e 100644
--- a/lib/Target/Sparc/SparcV8ISelSimple.cpp
+++ b/lib/Target/Sparc/SparcV8ISelSimple.cpp
@@ -546,7 +546,8 @@ void V8ISel::visitLoadInst(LoadInst &I) {
     BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
     return;
    case cLong:
-    BuildMI (BB, V8::LDDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
+    BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
+    BuildMI (BB, V8::LDmr, 1, DestReg+1).addReg (PtrReg).addSImm(4);
     return;
    default:
     std::cerr << "Load instruction not handled: " << I;
@@ -570,7 +571,8 @@ void V8ISel::visitStoreInst(StoreInst &I) {
     BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
     return;
    case cLong:
-    BuildMI (BB, V8::STDrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
+    BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
+    BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
     return;
    default:
     std::cerr << "Store instruction not handled: " << I;
diff --git a/lib/Target/SparcV8/InstSelectSimple.cpp b/lib/Target/SparcV8/InstSelectSimple.cpp
index e25a73c6ae2..bef5002160e 100644
--- a/lib/Target/SparcV8/InstSelectSimple.cpp
+++ b/lib/Target/SparcV8/InstSelectSimple.cpp
@@ -546,7 +546,8 @@ void V8ISel::visitLoadInst(LoadInst &I) {
     BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
     return;
    case cLong:
-    BuildMI (BB, V8::LDDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
+    BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
+    BuildMI (BB, V8::LDmr, 1, DestReg+1).addReg (PtrReg).addSImm(4);
     return;
    default:
     std::cerr << "Load instruction not handled: " << I;
@@ -570,7 +571,8 @@ void V8ISel::visitStoreInst(StoreInst &I) {
     BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
     return;
    case cLong:
-    BuildMI (BB, V8::STDrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
+    BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
+    BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
     return;
    default:
     std::cerr << "Store instruction not handled: " << I;
diff --git a/lib/Target/SparcV8/SparcV8ISelSimple.cpp b/lib/Target/SparcV8/SparcV8ISelSimple.cpp
index e25a73c6ae2..bef5002160e 100644
--- a/lib/Target/SparcV8/SparcV8ISelSimple.cpp
+++ b/lib/Target/SparcV8/SparcV8ISelSimple.cpp
@@ -546,7 +546,8 @@ void V8ISel::visitLoadInst(LoadInst &I) {
     BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
     return;
    case cLong:
-    BuildMI (BB, V8::LDDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
+    BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
+    BuildMI (BB, V8::LDmr, 1, DestReg+1).addReg (PtrReg).addSImm(4);
     return;
    default:
     std::cerr << "Load instruction not handled: " << I;
@@ -570,7 +571,8 @@ void V8ISel::visitStoreInst(StoreInst &I) {
     BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
     return;
    case cLong:
-    BuildMI (BB, V8::STDrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
+    BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
+    BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
     return;
    default:
     std::cerr << "Store instruction not handled: " << I;
-- 
2.34.1