From 778404601266effff17d5c43d0ad08b8ca2522d0 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Mon, 7 Nov 2011 19:01:49 +0000 Subject: [PATCH] Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted when shift amount is larger than 32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143990 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips64InstrInfo.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 83bd7b88c59..1e8bf702421 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -155,9 +155,9 @@ def : Pat<(i64 immZExt16:$in), (ORi64 ZERO_64, imm:$in)>; // zextloadi32_u -def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>, +def : Pat<(zextloadi32_u addr:$a), (DSRL32 (DSLL32 (ULW64_P8 addr:$a), 0), 0)>, Requires<[IsN64]>; -def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>, +def : Pat<(zextloadi32_u addr:$a), (DSRL32 (DSLL32 (ULW64 addr:$a), 0), 0)>, Requires<[NotN64]>; // hi/lo relocs -- 2.34.1