From 78dd7a580c7ad7234395d2c0207c98e751378cd7 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 5 Apr 2013 01:25:41 +0000 Subject: [PATCH] Clean up some confusing language, and use more realistic examples. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178828 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetInstrInfo.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index fb311d85085..0ba75e5d7ca 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -364,11 +364,10 @@ public: /// condition code in Cond. /// /// When successful, also return the latency in cycles from TrueReg, - /// FalseReg, and Cond to the destination register. The Cond latency should - /// compensate for a conditional branch being removed. For example, if a - /// conditional branch has a 3 cycle latency from the condition code read, - /// and a cmov instruction has a 2 cycle latency from the condition code - /// read, CondCycles should be returned as -1. + /// FalseReg, and Cond to the destination register. In most cases, a select + /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1 + /// + /// Some x86 implementations have 2-cycle cmov instructions. /// /// @param MBB Block where select instruction would be inserted. /// @param Cond Condition returned by AnalyzeBranch. -- 2.34.1