From 7a16f34aa6c6ee4e39d2381e9ffc2f5b1f247ed1 Mon Sep 17 00:00:00 2001 From: David Blaikie Date: Wed, 3 Dec 2014 19:58:45 +0000 Subject: [PATCH] Simplify ownership of RegClasses by using list instead of vector This complicates a few algorithms due to not having random access, but not by a huge degree I don't think (open to debate/design discussion/etc). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223261 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/AsmMatcherEmitter.cpp | 22 ++--- utils/TableGen/CodeGenRegisters.cpp | 116 +++++++++++++------------ utils/TableGen/CodeGenRegisters.h | 6 +- utils/TableGen/CodeGenTarget.cpp | 9 +- utils/TableGen/DAGISelMatcherGen.cpp | 8 +- utils/TableGen/RegisterInfoEmitter.cpp | 49 ++++------- 6 files changed, 100 insertions(+), 110 deletions(-) diff --git a/utils/TableGen/AsmMatcherEmitter.cpp b/utils/TableGen/AsmMatcherEmitter.cpp index b777d66997e..5b2ff6792d4 100644 --- a/utils/TableGen/AsmMatcherEmitter.cpp +++ b/utils/TableGen/AsmMatcherEmitter.cpp @@ -1089,9 +1089,9 @@ buildRegisterClasses(SmallPtrSetImpl &SingletonRegisters) { RegisterSetSet RegisterSets; // Gather the defined sets. - for (const CodeGenRegisterClass *RC : RegClassList) - RegisterSets.insert(RegisterSet(RC->getOrder().begin(), - RC->getOrder().end())); + for (const CodeGenRegisterClass &RC : RegClassList) + RegisterSets.insert( + RegisterSet(RC.getOrder().begin(), RC.getOrder().end())); // Add any required singleton sets. for (Record *Rec : SingletonRegisters) { @@ -1160,19 +1160,19 @@ buildRegisterClasses(SmallPtrSetImpl &SingletonRegisters) { } // Name the register classes which correspond to a user defined RegisterClass. - for (const CodeGenRegisterClass *RC : RegClassList) { + for (const CodeGenRegisterClass &RC : RegClassList) { // Def will be NULL for non-user defined register classes. - Record *Def = RC->getDef(); + Record *Def = RC.getDef(); if (!Def) continue; - ClassInfo *CI = RegisterSetClasses[RegisterSet(RC->getOrder().begin(), - RC->getOrder().end())]; + ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(), + RC.getOrder().end())]; if (CI->ValueName.empty()) { - CI->ClassName = RC->getName(); - CI->Name = "MCK_" + RC->getName(); - CI->ValueName = RC->getName(); + CI->ClassName = RC.getName(); + CI->Name = "MCK_" + RC.getName(); + CI->ValueName = RC.getName(); } else - CI->ValueName = CI->ValueName + "," + RC->getName(); + CI->ValueName = CI->ValueName + "," + RC.getName(); RegisterClassClasses.insert(std::make_pair(Def, CI)); } diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp index 6104ac2eab9..7af2438446b 100644 --- a/utils/TableGen/CodeGenRegisters.cpp +++ b/utils/TableGen/CodeGenRegisters.cpp @@ -810,34 +810,34 @@ static bool testSubClass(const CodeGenRegisterClass *A, /// Register classes with the same registers, spill size, and alignment form a /// clique. They will be ordered alphabetically. /// -static int TopoOrderRC(CodeGenRegisterClass *const *PA, - CodeGenRegisterClass *const *PB) { - auto *A = *PA; - auto *B = *PB; +static bool TopoOrderRC(const CodeGenRegisterClass &PA, + const CodeGenRegisterClass &PB) { + auto *A = &PA; + auto *B = &PB; if (A == B) return 0; // Order by ascending spill size. if (A->SpillSize < B->SpillSize) - return -1; + return true; if (A->SpillSize > B->SpillSize) - return 1; + return false; // Order by ascending spill alignment. if (A->SpillAlignment < B->SpillAlignment) - return -1; + return true; if (A->SpillAlignment > B->SpillAlignment) - return 1; + return false; // Order by descending set size. Note that the classes' allocation order may // not have been computed yet. The Members set is always vaild. if (A->getMembers().size() > B->getMembers().size()) - return -1; + return true; if (A->getMembers().size() < B->getMembers().size()) - return 1; + return false; // Finally order by name as a tie breaker. - return StringRef(A->getName()).compare(B->getName()); + return StringRef(A->getName()) < B->getName(); } std::string CodeGenRegisterClass::getQualifiedName() const { @@ -854,13 +854,13 @@ void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) { // Visit backwards so sub-classes are seen first. for (auto I = RegClasses.rbegin(), E = RegClasses.rend(); I != E; ++I) { - CodeGenRegisterClass &RC = **I; + CodeGenRegisterClass &RC = *I; RC.SubClasses.resize(RegClasses.size()); RC.SubClasses.set(RC.EnumValue); // Normally, all subclasses have IDs >= rci, unless RC is part of a clique. for (auto I2 = I.base(), E2 = RegClasses.end(); I2 != E2; ++I2) { - CodeGenRegisterClass &SubRC = **I2; + CodeGenRegisterClass &SubRC = *I2; if (RC.SubClasses.test(SubRC.EnumValue)) continue; if (!testSubClass(&RC, &SubRC)) @@ -871,30 +871,30 @@ void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) { } // Sweep up missed clique members. They will be immediately preceding RC. - for (auto I2 = std::next(I); I2 != E && testSubClass(&RC, *I2); ++I2) - RC.SubClasses.set((*I2)->EnumValue); + for (auto I2 = std::next(I); I2 != E && testSubClass(&RC, &*I2); ++I2) + RC.SubClasses.set(I2->EnumValue); } // Compute the SuperClasses lists from the SubClasses vectors. - for (auto *RC : RegClasses) { - const BitVector &SC = RC->getSubClasses(); + for (auto &RC : RegClasses) { + const BitVector &SC = RC.getSubClasses(); auto I = RegClasses.begin(); for (int s = 0, next_s = SC.find_first(); next_s != -1; next_s = SC.find_next(s)) { std::advance(I, next_s - s); s = next_s; - if (*I == RC) + if (&*I == &RC) continue; - (*I)->SuperClasses.push_back(RC); + I->SuperClasses.push_back(&RC); } } // With the class hierarchy in place, let synthesized register classes inherit // properties from their closest super-class. The iteration order here can // propagate properties down multiple levels. - for (auto *RC : RegClasses) - if (!RC->getDef()) - RC->inheritProperties(RegBank); + for (auto &RC : RegClasses) + if (!RC.getDef()) + RC.inheritProperties(RegBank); } void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, @@ -995,18 +995,18 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) { // Allocate user-defined register classes. for (auto *RC : RCs) { - RegClasses.push_back(new CodeGenRegisterClass(*this, RC)); - addToMaps(RegClasses.back()); + RegClasses.push_back(CodeGenRegisterClass(*this, RC)); + addToMaps(&RegClasses.back()); } // Infer missing classes to create a full algebra. computeInferredRegisterClasses(); // Order register classes topologically and assign enum values. - array_pod_sort(RegClasses.begin(), RegClasses.end(), TopoOrderRC); + RegClasses.sort(TopoOrderRC); unsigned i = 0; - for (auto *RC : RegClasses) - RC->EnumValue = i++; + for (auto &RC : RegClasses) + RC.EnumValue = i++; CodeGenRegisterClass::computeSubClasses(*this); } @@ -1057,9 +1057,9 @@ CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC, return FoundI->second; // Sub-class doesn't exist, create a new one. - RegClasses.push_back(new CodeGenRegisterClass(*this, Name, K)); - addToMaps(RegClasses.back()); - return RegClasses.back(); + RegClasses.push_back(CodeGenRegisterClass(*this, Name, K)); + addToMaps(&RegClasses.back()); + return &RegClasses.back(); } CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) { @@ -1247,11 +1247,11 @@ static void computeUberSets(std::vector &UberSets, // For simplicitly make the SetID the same as EnumValue. IntEqClasses UberSetIDs(Registers.size()+1); std::set AllocatableRegs; - for (auto *RegClass : RegBank.getRegClasses()) { - if (!RegClass->Allocatable) + for (auto &RegClass : RegBank.getRegClasses()) { + if (!RegClass.Allocatable) continue; - const CodeGenRegister::Set &Regs = RegClass->getMembers(); + const CodeGenRegister::Set &Regs = RegClass.getMembers(); if (Regs.empty()) continue; @@ -1525,16 +1525,16 @@ void CodeGenRegBank::computeRegUnitSets() { // Compute a unique RegUnitSet for each RegClass. auto &RegClasses = getRegClasses(); - for (auto *RC : RegClasses) { - if (!RC->Allocatable) + for (auto &RC : RegClasses) { + if (!RC.Allocatable) continue; // Speculatively grow the RegUnitSets to hold the new set. RegUnitSets.resize(RegUnitSets.size() + 1); - RegUnitSets.back().Name = RC->getName(); + RegUnitSets.back().Name = RC.getName(); // Compute a sorted list of units in this class. - RC->buildRegUnitSet(RegUnitSets.back().Units); + RC.buildRegUnitSet(RegUnitSets.back().Units); // Find an existing RegUnitSet. std::vector::const_iterator SetI = @@ -1634,20 +1634,20 @@ void CodeGenRegBank::computeRegUnitSets() { // For each register class, list the UnitSets that are supersets. RegClassUnitSets.resize(RegClasses.size()); int RCIdx = -1; - for (auto *RC : RegClasses) { + for (auto &RC : RegClasses) { ++RCIdx; - if (!RC->Allocatable) + if (!RC.Allocatable) continue; // Recompute the sorted list of units in this class. std::vector RCRegUnits; - RC->buildRegUnitSet(RCRegUnits); + RC.buildRegUnitSet(RCRegUnits); // Don't increase pressure for unallocatable regclasses. if (RCRegUnits.empty()) continue; - DEBUG(dbgs() << "RC " << RC->getName() << " Units: \n"; + DEBUG(dbgs() << "RC " << RC.getName() << " Units: \n"; for (unsigned i = 0, e = RCRegUnits.size(); i < e; ++i) dbgs() << RegUnits[RCRegUnits[i]].getRoots()[0]->getName() << " "; dbgs() << "\n UnitSetIDs:"); @@ -1732,12 +1732,13 @@ void CodeGenRegBank::computeDerivedInfo() { // returns a maximal register class for all X. // void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) { - // This loop might add more subclasses, invalidating iterators, so don't use - // range-for or iterator-based loops (unless RegClasses is changed to use a - // container with appropriate iterator invalidation semantics for this). - for (unsigned rci = 0, rce = RegClasses.size(); rci != rce; ++rci) { + assert(!RegClasses.empty()); + // Stash the iterator to the last element so that this loop doesn't visit + // elements added by the getOrCreateSubClass call within it. + for (auto I = RegClasses.begin(), E = std::prev(RegClasses.end()); + I != std::next(E); ++I) { CodeGenRegisterClass *RC1 = RC; - CodeGenRegisterClass *RC2 = RegClasses[rci]; + CodeGenRegisterClass *RC2 = &*I; if (RC1 == RC2) continue; @@ -1844,9 +1845,11 @@ void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC, // this loop. They will never be useful. // Careful if trying to transform this loop to use iterators - as this loop // will add new classes it will invalidate iterators to RegClasses. - for (unsigned rci = FirstSubRegRC, rce = RegClasses.size(); rci != rce; - ++rci) { - CodeGenRegisterClass &SubRC = *RegClasses[rci]; + assert(!RegClasses.empty()); + for (auto I = std::next(RegClasses.begin(), FirstSubRegRC), + E = std::prev(RegClasses.end()); + I != std::next(E); ++I) { + CodeGenRegisterClass &SubRC = *I; // Topological shortcut: SubRC members have the wrong shape. if (!TopoSigs.anyCommon(SubRC.getTopoSigs())) continue; @@ -1883,10 +1886,9 @@ void CodeGenRegBank::computeInferredRegisterClasses() { // Visit all register classes, including the ones being added by the loop. // Watch out for iterator invalidation here. - // inferMatchingSuperRegClass inside this loop can add new elements to - // RegClasses, so this loop can't use range-for or even explicit iterators. - for (unsigned rci = 0; rci != RegClasses.size(); ++rci) { - CodeGenRegisterClass *RC = RegClasses[rci]; + unsigned rci = 0; + for (auto &RCR : RegClasses) { + CodeGenRegisterClass *RC = &RCR; // Synthesize answers for getSubClassWithSubReg(). inferSubClassWithSubReg(RC); @@ -1905,10 +1907,11 @@ void CodeGenRegBank::computeInferredRegisterClasses() { // [0..FirstNewRC). We need to cover SubRC = [FirstNewRC..rci]. if (rci + 1 == FirstNewRC) { unsigned NextNewRC = RegClasses.size(); - for (unsigned rci2 = 0; rci2 != FirstNewRC; ++rci2) + auto I2 = RegClasses.begin(); + for (unsigned rci2 = 0; rci2 != FirstNewRC; ++rci2, ++I2) // This can add more things to RegClasses, be careful about iterator // invalidation of outer loop variables. - inferMatchingSuperRegClass(RegClasses[rci2], FirstNewRC); + inferMatchingSuperRegClass(&*I2, FirstNewRC); FirstNewRC = NextNewRC; } } @@ -1923,8 +1926,7 @@ const CodeGenRegisterClass* CodeGenRegBank::getRegClassForRegister(Record *R) { const CodeGenRegister *Reg = getReg(R); const CodeGenRegisterClass *FoundRC = nullptr; - for (const auto *RCP : getRegClasses()) { - const CodeGenRegisterClass &RC = *RCP; + for (const auto &RC : getRegClasses()) { if (!RC.contains(Reg)) continue; diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h index fc585fa42c2..d42d9dafa2b 100644 --- a/utils/TableGen/CodeGenRegisters.h +++ b/utils/TableGen/CodeGenRegisters.h @@ -471,7 +471,7 @@ namespace llvm { SmallVector RegUnits; // Register classes. - std::vector RegClasses; + std::list RegClasses; DenseMap Def2RC; typedef std::map RCKeyMap; RCKeyMap Key2RC; @@ -609,9 +609,9 @@ namespace llvm { RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; } const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; } - std::vector &getRegClasses() { return RegClasses; } + std::list &getRegClasses() { return RegClasses; } - const std::vector &getRegClasses() const { + const std::list &getRegClasses() const { return RegClasses; } diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp index ccf9f8ad9cb..62938f7027b 100644 --- a/utils/TableGen/CodeGenTarget.cpp +++ b/utils/TableGen/CodeGenTarget.cpp @@ -233,8 +233,8 @@ getRegisterVTs(Record *R) const { const CodeGenRegister *Reg = getRegBank().getReg(R); std::vector Result; for (const auto &RC : getRegBank().getRegClasses()) { - if (RC->contains(Reg)) { - ArrayRef InVTs = RC->getValueTypes(); + if (RC.contains(Reg)) { + ArrayRef InVTs = RC.getValueTypes(); Result.insert(Result.end(), InVTs.begin(), InVTs.end()); } } @@ -247,9 +247,8 @@ getRegisterVTs(Record *R) const { void CodeGenTarget::ReadLegalValueTypes() const { - for (const auto *RC : getRegBank().getRegClasses()) - for (unsigned ri = 0, re = RC->VTs.size(); ri != re; ++ri) - LegalValueTypes.push_back(RC->VTs[ri]); + for (const auto &RC : getRegBank().getRegClasses()) + LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end()); // Remove duplicates. std::sort(LegalValueTypes.begin(), LegalValueTypes.end()); diff --git a/utils/TableGen/DAGISelMatcherGen.cpp b/utils/TableGen/DAGISelMatcherGen.cpp index 47d3b647156..eb806192bdc 100644 --- a/utils/TableGen/DAGISelMatcherGen.cpp +++ b/utils/TableGen/DAGISelMatcherGen.cpp @@ -28,18 +28,18 @@ static MVT::SimpleValueType getRegisterValueType(Record *R, MVT::SimpleValueType VT = MVT::Other; const CodeGenRegister *Reg = T.getRegBank().getReg(R); - for (const auto *RC : T.getRegBank().getRegClasses()) { - if (!RC->contains(Reg)) + for (const auto &RC : T.getRegBank().getRegClasses()) { + if (!RC.contains(Reg)) continue; if (!FoundRC) { FoundRC = true; - VT = RC->getValueTypeNum(0); + VT = RC.getValueTypeNum(0); continue; } // If this occurs in multiple register classes, they all have to agree. - assert(VT == RC->getValueTypeNum(0)); + assert(VT == RC.getValueTypeNum(0)); } return VT; } diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 863af8ec64d..fa10dbbb872 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -111,9 +111,9 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, if (!Namespace.empty()) OS << "namespace " << Namespace << " {\n"; OS << "enum {\n"; - for (const auto *RC : RegisterClasses) - OS << " " << RC->getName() << "RegClassID" - << " = " << RC->EnumValue << ",\n"; + for (const auto &RC : RegisterClasses) + OS << " " << RC.getName() << "RegClassID" + << " = " << RC.EnumValue << ",\n"; OS << "\n };\n"; if (!Namespace.empty()) OS << "}\n"; @@ -177,8 +177,7 @@ EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, << "const RegClassWeight &" << ClassName << "::\n" << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" << " static const RegClassWeight RCWeightTable[] = {\n"; - for (const auto *RCP : RegBank.getRegClasses()) { - const CodeGenRegisterClass &RC = *RCP; + for (const auto &RC : RegBank.getRegClasses()) { const CodeGenRegister::Set &Regs = RC.getMembers(); if (Regs.empty()) OS << " {0, 0"; @@ -844,8 +843,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, SequenceToOffsetTable RegClassStrings; // Emit the register enum value arrays for each RegisterClass - for (const auto *RCP : RegisterClasses) { - const CodeGenRegisterClass &RC = *RCP; + for (const auto &RC : RegisterClasses) { ArrayRef Order = RC.getOrder(); // Give the register class a legal C name if it's anonymous. @@ -885,9 +883,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, OS << "extern const MCRegisterClass " << TargetName << "MCRegisterClasses[] = {\n"; - for (const auto *RCP : RegisterClasses) { - const CodeGenRegisterClass &RC = *RCP; - + for (const auto &RC : RegisterClasses) { // Asserts to make sure values will fit in table assuming types from // MCRegisterInfo.h assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large."); @@ -989,11 +985,10 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, const auto &RegisterClasses = RegBank.getRegClasses(); if (!RegisterClasses.empty()) { - OS << "namespace " << RegisterClasses.front()->Namespace + OS << "namespace " << RegisterClasses.front().Namespace << " { // Register classes\n"; - for (const auto *RCP : RegisterClasses) { - const CodeGenRegisterClass &RC = *RCP; + for (const auto &RC : RegisterClasses) { const std::string &Name = RC.getName(); // Output the extern for the instance. @@ -1030,8 +1025,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, std::set AllocatableRegs; // Collect allocatable registers. - for (const auto *RCP : RegisterClasses) { - const CodeGenRegisterClass &RC = *RCP; + for (const auto &RC : RegisterClasses) { ArrayRef Order = RC.getOrder(); if (RC.Allocatable) @@ -1040,8 +1034,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, // Build a shared array of value types. SequenceToOffsetTable > VTSeqs; - for (const auto *RC : RegisterClasses) - VTSeqs.add(RC->VTs); + for (const auto &RC : RegisterClasses) + VTSeqs.add(RC.VTs); VTSeqs.layout(); OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); @@ -1094,8 +1088,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, SequenceToOffsetTable SuperRegIdxSeqs; BitVector MaskBV(RegisterClasses.size()); - for (const auto *RCP : RegisterClasses) { - const CodeGenRegisterClass &RC = *RCP; + for (const auto &RC : RegisterClasses) { OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n "; printBitVectorAsHex(OS, RC.getSubClasses(), 32); @@ -1122,8 +1115,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, OS << "};\n\n"; // Emit NULL terminated super-class lists. - for (const auto *RCP : RegisterClasses) { - const CodeGenRegisterClass &RC = *RCP; + for (const auto &RC : RegisterClasses) { ArrayRef Supers = RC.getSuperClasses(); // Skip classes without supers. We can reuse NullRegClasses. @@ -1138,8 +1130,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, } // Emit methods. - for (const auto *RCP : RegisterClasses) { - const CodeGenRegisterClass &RC = *RCP; + for (const auto &RC : RegisterClasses) { if (!RC.AltOrderSelect.empty()) { OS << "\nstatic inline unsigned " << RC.getName() << "AltOrderSelect(const MachineFunction &MF) {" @@ -1171,11 +1162,10 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, } // Now emit the actual value-initialized register class instances. - OS << "\nnamespace " << RegisterClasses.front()->Namespace + OS << "\nnamespace " << RegisterClasses.front().Namespace << " { // Register class instances\n"; - for (const auto *RCP : RegisterClasses) { - const CodeGenRegisterClass &RC = *RCP; + for (const auto &RC : RegisterClasses) { OS << " extern const TargetRegisterClass " << RC.getName() << "RegClass = {\n " << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " @@ -1198,8 +1188,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, OS << "\nnamespace {\n"; OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; - for (const auto *RC : RegisterClasses) - OS << " &" << RC->getQualifiedName() << "RegClass,\n"; + for (const auto &RC : RegisterClasses) + OS << " &" << RC.getQualifiedName() << "RegClass,\n"; OS << " };\n"; OS << "}\n"; // End of anonymous namespace... @@ -1240,8 +1230,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, else PrintFatalError("Too many register classes."); OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; - for (const auto *RCP : RegisterClasses) { - const CodeGenRegisterClass &RC = *RCP; + for (const auto &RC : RegisterClasses) { OS << " {\t// " << RC.getName() << "\n"; for (auto &Idx : SubRegIndices) { if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) -- 2.34.1