From 7a38d450b62e7b27b350352c0ab08b66bea00131 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 12 Jul 2012 23:36:52 +0800 Subject: [PATCH] arm: at91: dt: at91sam9 add nand pinctrl support Acked-by: Nicolas Ferre Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- arch/arm/boot/dts/at91sam9260.dtsi | 10 ++++++++++ arch/arm/boot/dts/at91sam9263.dtsi | 10 ++++++++++ arch/arm/boot/dts/at91sam9g45.dtsi | 10 ++++++++++ arch/arm/boot/dts/at91sam9n12.dtsi | 10 ++++++++++ arch/arm/boot/dts/at91sam9x5.dtsi | 10 ++++++++++ 5 files changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 838328a18297..9a24ffbb7231 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -208,6 +208,14 @@ }; }; + nand { + pinctrl_nand: nand-0 { + atmel,pins = + <2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */ + 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */ + }; + }; + pioA: gpio@fffff400 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; @@ -382,6 +390,8 @@ >; atmel,nand-addr-offset = <21>; atmel,nand-cmd-offset = <22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; gpios = <&pioC 13 0 &pioC 14 0 0 diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 579f82d23d34..251ccec430a4 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -155,6 +155,14 @@ }; }; + nand { + pinctrl_nand: nand-0 { + atmel,pins = + <0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/ + 3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */ + }; + }; + pioA: gpio@fffff200 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff200 0x200>; @@ -281,6 +289,8 @@ >; atmel,nand-addr-offset = <21>; atmel,nand-cmd-offset = <22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; gpios = <&pioA 22 0 &pioD 15 0 0 diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 48a2ed72fea0..c340f6635d81 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -188,6 +188,14 @@ }; }; + nand { + pinctrl_nand: nand-0 { + atmel,pins = + <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/ + 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */ + }; + }; + pioA: gpio@fffff200 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff200 0x200>; @@ -364,6 +372,8 @@ >; atmel,nand-addr-offset = <21>; atmel,nand-cmd-offset = <22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; gpios = <&pioC 8 0 &pioC 14 0 0 diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index e057f660296f..7b644c5b0bed 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -191,6 +191,14 @@ }; }; + nand { + pinctrl_nand: nand-0 { + atmel,pins = + <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/ + 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */ + }; + }; + pioA: gpio@fffff400 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; @@ -315,6 +323,8 @@ >; atmel,nand-addr-offset = <21>; atmel,nand-cmd-offset = <22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; gpios = <&pioD 5 0 &pioD 4 0 0 diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 1a68e41bbcdd..6a40b777ea4c 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -198,6 +198,14 @@ }; }; + nand { + pinctrl_nand: nand-0 { + atmel,pins = + <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */ + 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */ + }; + }; + pioA: gpio@fffff400 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; @@ -371,6 +379,8 @@ >; atmel,nand-addr-offset = <21>; atmel,nand-cmd-offset = <22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; gpios = <&pioD 5 0 &pioD 4 0 0 -- 2.34.1