From 7bdfd1b4433a989038f757a14b8b01210981f114 Mon Sep 17 00:00:00 2001
From: Quentin Colombet <qcolombet@apple.com>
Date: Mon, 18 Aug 2014 17:55:43 +0000
Subject: [PATCH] [X86][Haswell][SchedModel] Add architecture specific
 scheduling models. Group: Integer MMX and XMM instructions. Sub-group: Other
 instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215917 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86SchedHaswell.td | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/lib/Target/X86/X86SchedHaswell.td b/lib/Target/X86/X86SchedHaswell.td
index 38833de7c25..f998bb6b4db 100644
--- a/lib/Target/X86/X86SchedHaswell.td
+++ b/lib/Target/X86/X86SchedHaswell.td
@@ -1536,4 +1536,13 @@ def : InstRW<[WritePShift], (instregex "(V?)PS(LL|RL|RA)(W|D|Q)(Y?)rr")>;
 // PSLL,PSRL DQ.
 def : InstRW<[WriteP5], (instregex "(V?)PS(R|L)LDQ(Y?)ri")>;
 
+//-- Other --//
+
+// EMMS.
+def WriteEMMS : SchedWriteRes<[]> {
+  let Latency = 13;
+  let NumMicroOps = 31;
+}
+def : InstRW<[WriteEMMS], (instregex "MMX_EMMS")>;
+
 } // SchedModel
-- 
2.34.1