From 7be3a33a0b957d2f0f21d3e0eead84ca5fcb34ed Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Thu, 16 Jul 2015 21:14:07 +0000 Subject: [PATCH] [PowerPC] v4i32 is a VSRCRegClass I was looking at some vector code generation and kept seeing unnecessary vector copies into the Altivec half of the VSX registers. I discovered that we overlooked v4i32 when adding the register classes for VSX; we only added v4f32 and v2f64. This means that anything that canonicalizes into v4i32 (which is a LOT of stuff) ends up being forced into VRRC on its way to VSRC. The fix is one line. The rest of the patch is fixing up some test cases whose code generation has changed as a result. This seems like it would be a good candidate for backport to 3.7. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242442 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCISelLowering.cpp | 1 + test/CodeGen/PowerPC/vsx.ll | 69 +++++++++---------- test/CodeGen/PowerPC/vsx_insert_extract_le.ll | 8 +-- 3 files changed, 39 insertions(+), 39 deletions(-) diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index cfbd0e38aad..b9868053def 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -580,6 +580,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, addRegisterClass(MVT::f64, &PPC::VSFRCRegClass); + addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass); addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass); addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass); diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll index f85acebeea6..dceb2516c69 100644 --- a/test/CodeGen/PowerPC/vsx.ll +++ b/test/CodeGen/PowerPC/vsx.ll @@ -70,10 +70,10 @@ entry: ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test5 -; CHECK-FISL: vor 4, 2, 2 -; CHECK-FISL: vor 5, 3, 3 -; CHECK-FISL: xxlxor 36, 36, 37 -; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: vor +; CHECK-FISL: vor +; CHECK-FISL: xxlxor +; CHECK-FISL: vor 2 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test5 @@ -133,10 +133,10 @@ entry: ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test8 -; CHECK-FISL: vor 4, 2, 2 -; CHECK-FISL: vor 5, 3, 3 -; CHECK-FISL: xxlor 36, 36, 37 -; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: vor +; CHECK-FISL: vor +; CHECK-FISL: xxlor +; CHECK-FISL: vor 2 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test8 @@ -196,10 +196,10 @@ entry: ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test11 -; CHECK-FISL: vor 4, 2, 2 -; CHECK-FISL: vor 5, 3, 3 -; CHECK-FISL: xxland 36, 36, 37 -; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: vor +; CHECK-FISL: vor +; CHECK-FISL: xxland +; CHECK-FISL: vor 2 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test11 @@ -260,17 +260,14 @@ entry: ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test14 -; CHECK-FISL: vor 4, 2, 2 -; CHECK-FISL: vor 5, 3, 3 -; CHECK-FISL: xxlor 36, 36, 37 -; CHECK-FISL: vor 0, 4, 4 -; CHECK-FISL: vor 4, 2, 2 -; CHECK-FISL: vor 5, 3, 3 -; CHECK-FISL: xxlnor 36, 36, 37 +; CHECK-FISL: vor 4, 3, 3 +; CHECK-FISL: vor 5, 2, 2 +; CHECK-FISL: xxlor 0, 37, 36 +; CHECK-FISL: xxlnor 36, 37, 36 ; CHECK-FISL: vor 2, 4, 4 ; CHECK-FISL: lis 0, -1 ; CHECK-FISL: ori 0, 0, 65520 -; CHECK-FISL: stvx 0, 1, 0 +; CHECK-FISL: stxvd2x 0, 1, 0 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test14 @@ -347,15 +344,13 @@ entry: ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test17 -; CHECK-FISL: vspltisb 4, -1 -; CHECK-FISL: vor 5, 3, 3 -; CHECK-FISL: vor 0, 4, 4 -; CHECK-FISL: xxlxor 37, 37, 32 -; CHECK-FISL: vor 3, 5, 5 +; CHECK-FISL: vor 4, 3, 3 ; CHECK-FISL: vor 5, 2, 2 -; CHECK-FISL: vor 0, 3, 3 -; CHECK-FISL: xxland 37, 37, 32 -; CHECK-FISL: vor 2, 5, 5 +; CHECK-FISL: vspltisb 2, -1 +; CHECK-FISL: vor 0, 2, 2 +; CHECK-FISL: xxlxor 36, 36, 32 +; CHECK-FISL: xxland 36, 37, 36 +; CHECK-FISL: vor 2, 4, 4 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test17 @@ -434,12 +429,18 @@ entry: ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} ; CHECK-REG: blr +; FIXME: The fast-isel code is pretty miserable for this one. + ; CHECK-FISL-LABEL: @test20 -; CHECK-FISL: vcmpequw 4, 4, 5 -; CHECK-FISL: vor 0, 3, 3 -; CHECK-FISL: vor 1, 2, 2 -; CHECK-FISL: vor 6, 4, 4 -; CHECK-FISL: xxsel 32, 32, 33, 38 +; CHECK-FISL: vor 0, 5, 5 +; CHECK-FISL: vor 1, 4, 4 +; CHECK-FISL: vor 6, 3, 3 +; CHECK-FISL: vor 7, 2, 2 +; CHECK-FISL: vor 2, 1, 1 +; CHECK-FISL: vor 3, 0, 0 +; CHECK-FISL: vcmpequw 2, 2, 3 +; CHECK-FISL: vor 0, 2, 2 +; CHECK-FISL: xxsel 32, 38, 39, 32 ; CHECK-FISL: vor 2, 0, 0 ; CHECK-FISL: blr @@ -794,8 +795,6 @@ define <4 x i32> @test34(<4 x i32>* %a) { ; CHECK-FISL-LABEL: @test34 ; CHECK-FISL: lxvw4x 0, 0, 3 ; CHECK-FISL: xxlor 34, 0, 0 -; CHECK-FISL: vor 3, 2, 2 -; CHECK-FISL: vor 2, 3, 3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test34 diff --git a/test/CodeGen/PowerPC/vsx_insert_extract_le.ll b/test/CodeGen/PowerPC/vsx_insert_extract_le.ll index 84bbdd75b0f..6c89b1092bd 100644 --- a/test/CodeGen/PowerPC/vsx_insert_extract_le.ll +++ b/test/CodeGen/PowerPC/vsx_insert_extract_le.ll @@ -8,9 +8,9 @@ define <2 x double> @testi0(<2 x double>* %p1, double* %p2) { ; CHECK-LABEL: testi0 ; CHECK: lxvd2x 0, 0, 3 -; CHECK: lxsdx 34, 0, 4 +; CHECK: lxsdx 1, 0, 4 ; CHECK: xxswapd 0, 0 -; CHECK: xxspltd 1, 34, 0 +; CHECK: xxspltd 1, 1, 0 ; CHECK: xxpermdi 34, 0, 1, 1 } @@ -22,9 +22,9 @@ define <2 x double> @testi1(<2 x double>* %p1, double* %p2) { ; CHECK-LABEL: testi1 ; CHECK: lxvd2x 0, 0, 3 -; CHECK: lxsdx 34, 0, 4 +; CHECK: lxsdx 1, 0, 4 ; CHECK: xxswapd 0, 0 -; CHECK: xxspltd 1, 34, 0 +; CHECK: xxspltd 1, 1, 0 ; CHECK: xxmrgld 34, 1, 0 } -- 2.34.1