From 7c4ae262d3800546de72216fb2c304058ce13986 Mon Sep 17 00:00:00 2001 From: xxx Date: Fri, 27 Jun 2014 18:23:08 +0800 Subject: [PATCH] fixed : ft test config --- arch/arm/boot/dts/rk3288-ft.dts | 10 +- arch/arm/configs/rockchip_ft_defconfig | 11 +- .../mach-rockchip/rk_pm_tests/ft/ft_test.c | 101 +++++++++--------- 3 files changed, 64 insertions(+), 58 deletions(-) mode change 100644 => 100755 arch/arm/mach-rockchip/rk_pm_tests/ft/ft_test.c diff --git a/arch/arm/boot/dts/rk3288-ft.dts b/arch/arm/boot/dts/rk3288-ft.dts index 2aa85ad24f4a..7fdbdac6dc42 100755 --- a/arch/arm/boot/dts/rk3288-ft.dts +++ b/arch/arm/boot/dts/rk3288-ft.dts @@ -16,16 +16,18 @@ status = "okay"; }; - rockchip_ft_test { - // rockchip,arm_rate =<408000000 504000000 600000000 792000000>; - // firs rate is setting in rockchip_clocks_init,so it is set 0xfffffffff + rockchip_ft_test { + // firs rate is setting in rockchip_clocks_init,so it is set 0xfffffffff + //rockchip,arm_rate =<0xffffffff 456000000 504000000 552000000>; rockchip,arm_rate =<0xffffffff (1728000000*1) (1752000000*1) (1800000000*1)>; rockchip,l1_tst_cnt=<(5*10*2-10) (5*10*2-10) (5*10*2-10) (80-10+0) >; rockchip,l2_cpy_cnt= <5 5 4 (4+0)>; rockchip,ftt_tst_cnt= <1 1 1 (0+0)>; rockchip,pi_tst_cnt= <12 12 10 (8+0)>; rockchip,stp_task_num= <300 250 250 (80+0)>; - rockchip,ft_end_cnt= <0x23>; + rockchip,ft_end_cnt= <(0x24)>; + //ready_pin idle_pin + rockchip,ft_vol_gpios= ; }; }; diff --git a/arch/arm/configs/rockchip_ft_defconfig b/arch/arm/configs/rockchip_ft_defconfig index 7931ecf64121..808a6864e657 100644 --- a/arch/arm/configs/rockchip_ft_defconfig +++ b/arch/arm/configs/rockchip_ft_defconfig @@ -23,10 +23,6 @@ CONFIG_RK_FT_TEST=y # CONFIG_ARM_THUMB is not set # CONFIG_SWP_EMULATE is not set # CONFIG_KUSER_HELPERS is not set -CONFIG_FIQ_DEBUGGER=y -CONFIG_FIQ_DEBUGGER_NO_SLEEP=y -CONFIG_FIQ_DEBUGGER_CONSOLE=y -CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y CONFIG_SMP=y CONFIG_PREEMPT=y CONFIG_AEABI=y @@ -61,6 +57,13 @@ CONFIG_SRAM=y # CONFIG_HWMON is not set # CONFIG_IEP is not set # CONFIG_USB_SUPPORT is not set +CONFIG_STAGING=y +CONFIG_ANDROID=y +# CONFIG_ANDROID_TIMED_OUTPUT is not set +CONFIG_FIQ_DEBUGGER=y +CONFIG_FIQ_DEBUGGER_NO_SLEEP=y +CONFIG_FIQ_DEBUGGER_CONSOLE=y +CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y # CONFIG_IOMMU_SUPPORT is not set # CONFIG_FILE_LOCKING is not set # CONFIG_DNOTIFY is not set diff --git a/arch/arm/mach-rockchip/rk_pm_tests/ft/ft_test.c b/arch/arm/mach-rockchip/rk_pm_tests/ft/ft_test.c old mode 100644 new mode 100755 index 9b30a44f8ac2..1005e9749a52 --- a/arch/arm/mach-rockchip/rk_pm_tests/ft/ft_test.c +++ b/arch/arm/mach-rockchip/rk_pm_tests/ft/ft_test.c @@ -99,7 +99,7 @@ const static unsigned int ftt_tst_cnt [TST_SETUPS]={1,1,1,0}; const static unsigned int pi_tst_cnt[TST_SETUPS]={12,12,10,8}; const static unsigned int stp_task_num[TST_SETUPS]={300,250,250,80}; -static u32 ft_end_cnt=0x24; +static u32 ft_end_cnt=0x20; // #define get_setup_tasks(a) ft_get_min(a,TST_TASK_NUM) @@ -616,25 +616,20 @@ int ft_cpu_test_type0_check(int steps,const char *str) return ret; } /*************************************type1 rate tst case**************************************/ -#define ENABLE_FT_TEST_GPIO // for ft seting 1.6G volt -#ifdef ENABLE_FT_TEST_GPIO +static u32 ft_client_ready_pin =0; +static u32 ft_client_idle_pin =0; -#define FT_CLIENT_READY_PIN (0x0c20) -#define FT_CLIENT_IDLE_PIN (0x0a00) #include "rk_ft_io.c" -#endif - -//uint32_t ddr_change_freq(uint32_t nMHz); +//#define FT_CLIENT_READY_PIN (0x0c20) +//#define FT_CLIENT_IDLE_PIN (0x0a00) int ft_cpu_test_type1_check(int steps,const char *str) { int cpu, ret = 0,i; int rate; - #ifdef ENABLE_FT_TEST_GPIO u8 idle_gpio_level; - #endif if(arm_setups_rate[steps]) { @@ -656,24 +651,20 @@ int ft_cpu_test_type1_check(int steps,const char *str) #endif } - - - #ifdef ENABLE_FT_TEST_GPIO - - //ft_printk("S%s,will set gpio\n",str); - - - idle_gpio_level=gpio_get_input_level(FT_CLIENT_IDLE_PIN); - // send msg to ctr board to up the volt - gpio_set_output_level(FT_CLIENT_READY_PIN,RKPM_GPIO_OUT_H); - - // waiting for volt upping ok - while( idle_gpio_level== gpio_get_input_level(FT_CLIENT_IDLE_PIN)); - gpio_set_output_level(FT_CLIENT_READY_PIN,RKPM_GPIO_OUT_L); - - //ft_printk("S%s,set gpio end\n",str); - #endif - + if(ft_client_ready_pin&&ft_client_ready_pin) + { + + //ft_printk("S%s,will set gpio\n",str); + idle_gpio_level=gpio_get_input_level(ft_client_idle_pin); + // send msg to ctr board to up the volt + gpio_set_output_level(ft_client_ready_pin,RKPM_GPIO_OUT_H); + + // waiting for volt upping ok + while( idle_gpio_level== gpio_get_input_level(ft_client_idle_pin)); + gpio_set_output_level(ft_client_ready_pin,RKPM_GPIO_OUT_L); + //ft_printk("S%s,set gpio end\n",str); + + } if(arm_setups_rate[steps]>=rate) { clk_set_rate(arm_clk,arm_setups_rate[steps]); @@ -918,9 +909,9 @@ int rk_ft_tests_cpus_init(int cpu) static int __init rk_ft_tests_init(void) { int cpu, i,ret = 0; - struct sched_param param = { .sched_priority =0 }; - + struct sched_param param = { .sched_priority =0 }; struct device_node *parent; + u32 temp_gpios[2]; ft_printk_info("%s\n",__FUNCTION__); @@ -976,21 +967,27 @@ static int __init rk_ft_tests_init(void) ,i,l1_tst_cnt[i],l2_cpy_cnt[i],ftt_tst_cnt[i],pi_tst_cnt[i],stp_task_num[i]); } - - if(of_property_read_u32_array(parent,"rockchip,ft_end_cnt",&ft_end_cnt,1)) + + if(of_property_read_u32_array(parent,"rockchip,ft_end_cnt",(u32 *)&ft_end_cnt,1)) { printk("%s:ft_end_cnt error\n",__FUNCTION__); return -1; } - - - + if(of_property_read_u32_array(parent,"rockchip,ft_vol_gpios",(u32 *)&temp_gpios[0],2)) + { + printk("%s:no ft_vol_gpios info,so ft ctr vol is not support\n",__FUNCTION__); + } + else + { + ft_client_ready_pin=temp_gpios[0]; + ft_client_idle_pin=temp_gpios[1]; + ft_printk_info("ft_vol_gpio%x,%x\n",ft_client_ready_pin,ft_client_idle_pin); + } //ddr_clk = clk_get(NULL, "clk_ddr"); //clk_set_rate(ddr_clk,0); - for(i=0;i