From 7ca9bb05f09dc85a15cce5dcf1d237559ae25f67 Mon Sep 17 00:00:00 2001 From: James Wylder Date: Thu, 3 Mar 2011 12:25:52 -0600 Subject: [PATCH] ARM: tegra: stingray: Update Memory tables Change all rates to integer multipliers, and Add table for 40nm Elpida Change-Id: Ie3a4e47948f541326da664537604e2c3061e3a92 Signed-off-by: James Wylder --- arch/arm/mach-tegra/board-stingray-memory.c | 357 +++++++++++++++++--- 1 file changed, 312 insertions(+), 45 deletions(-) diff --git a/arch/arm/mach-tegra/board-stingray-memory.c b/arch/arm/mach-tegra/board-stingray-memory.c index 139a02f775ae..0eb5c303a3a0 100644 --- a/arch/arm/mach-tegra/board-stingray-memory.c +++ b/arch/arm/mach-tegra/board-stingray-memory.c @@ -23,7 +23,7 @@ static const struct tegra_emc_table stingray_emc_tables_samsung[] = { { - .rate = 60000, /* SDRAM frquency */ + .rate = 50000, /* SDRAM frequency */ .regs = { 0x00000004, /* RC */ 0x00000008, /* RFC */ @@ -74,11 +74,11 @@ static const struct tegra_emc_table stingray_emc_tables_samsung[] = { } }, { - .rate = 120000, /* SDRAM frquency */ + .rate = 150000, /* SDRAM frequency */ .regs = { - 0x00000007, /* RC */ - 0x0000000f, /* RFC */ - 0x00000005, /* RAS */ + 0x00000009, /* RC */ + 0x00000014, /* RFC */ + 0x00000007, /* RAS */ 0x00000003, /* RP */ 0x00000006, /* R2W */ 0x00000004, /* W2R */ @@ -93,7 +93,7 @@ static const struct tegra_emc_table stingray_emc_tables_samsung[] = { 0x00000003, /* QRST */ 0x00000008, /* QSAFE */ 0x0000000b, /* RDV */ - 0x0000017f, /* REFRESH */ + 0x0000021f, /* REFRESH */ 0x00000000, /* BURST_REFRESH_NUM */ 0x00000003, /* PDEX2WR */ 0x00000003, /* PDEX2RD */ @@ -101,23 +101,128 @@ static const struct tegra_emc_table stingray_emc_tables_samsung[] = { 0x00000008, /* ACT2PDEN */ 0x00000001, /* AR2PDEN */ 0x0000000a, /* RW2PDEN */ - 0x00000010, /* TXSR */ + 0x00000015, /* TXSR */ 0x00000003, /* TCKE */ 0x00000008, /* TFAW */ 0x00000004, /* TRPAB */ 0x00000006, /* TCLKSTABLE */ 0x00000002, /* TCLKSTOP */ - 0x000001c2, /* TREFBW */ + 0x00000270, /* TREFBW */ 0x00000004, /* QUSE_EXTRA */ 0x00000001, /* FBIO_CFG6 */ 0x00000000, /* ODT_WRITE */ 0x00000000, /* ODT_READ */ 0x00000082, /* FBIO_CFG5 */ - 0xa09404ae, /* CFG_DIG_DLL */ + 0xa06804ae, /* CFG_DIG_DLL */ + 0x007fe010, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x0000000e, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + .rate = 300000, /* SDRAM frequency */ + .regs = { + 0x00000012, /* RC */ + 0x00000027, /* RFC */ + 0x0000000d, /* RAS */ + 0x00000006, /* RP */ + 0x00000007, /* R2W */ + 0x00000005, /* W2R */ + 0x00000003, /* R2P */ + 0x00000009, /* W2P */ + 0x00000006, /* RD_RCD */ + 0x00000006, /* WR_RCD */ + 0x00000003, /* RRD */ + 0x00000003, /* REXT */ + 0x00000002, /* WDV */ + 0x00000006, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000009, /* QSAFE */ + 0x0000000c, /* RDV */ + 0x0000045f, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000004, /* PDEX2WR */ + 0x00000004, /* PDEX2RD */ + 0x00000006, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000e, /* RW2PDEN */ + 0x0000002a, /* TXSR */ + 0x00000003, /* TCKE */ + 0x0000000f, /* TFAW */ + 0x00000007, /* TRPAB */ + 0x00000005, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x000004e0, /* TREFBW */ + 0x00000005, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000282, /* FBIO_CFG5 */ + 0xe04c048b, /* CFG_DIG_DLL */ 0x007fd010, /* DLL_XFORM_DQS */ 0x00000000, /* DLL_XFORM_QUSE */ 0x00000000, /* ZCAL_REF_CNT */ - 0x0000000a, /* ZCAL_WAIT_CNT */ + 0x0000001b, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + } +}; + +static const struct tegra_emc_table stingray_emc_tables_elpida_50nm[] = { + { + .rate = 25000, /* SDRAM frequency */ + .regs = { + 0x00000002, /* RC */ + 0x00000006, /* RFC */ + 0x00000003, /* RAS */ + 0x00000003, /* RP */ + 0x00000006, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x00000009, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000002, /* REXT */ + 0x00000002, /* WDV */ + 0x00000004, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000008, /* QSAFE */ + 0x0000000b, /* RDV */ + 0x0000004d, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000a, /* RW2PDEN */ + 0x00000004, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000008, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000068, /* TREFBW */ + 0x00000003, /* QUSE_EXTRA */ + 0x00000003, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000082, /* FBIO_CFG5 */ + 0xa06a04ae, /* CFG_DIG_DLL */ + 0x00070000, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000003, /* ZCAL_WAIT_CNT */ 0x00000000, /* AUTO_CAL_INTERVAL */ 0x00000000, /* CFG_CLKTRIM_0 */ 0x00000000, /* CFG_CLKTRIM_1 */ @@ -125,7 +230,109 @@ static const struct tegra_emc_table stingray_emc_tables_samsung[] = { } }, { - .rate = 200000, /* SDRAM frquency */ + .rate = 50000, /* SDRAM frequency */ + .regs = { + 0x00000003, /* RC */ + 0x00000007, /* RFC */ + 0x00000003, /* RAS */ + 0x00000003, /* RP */ + 0x00000006, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x00000009, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000002, /* REXT */ + 0x00000002, /* WDV */ + 0x00000005, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000008, /* QSAFE */ + 0x0000000b, /* RDV */ + 0x0000009f, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000a, /* RW2PDEN */ + 0x00000007, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000008, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x000000d0, /* TREFBW */ + 0x00000004, /* QUSE_EXTRA */ + 0x00000000, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000082, /* FBIO_CFG5 */ + 0xa06a04ae, /* CFG_DIG_DLL */ + 0x00070000, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000005, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + .rate = 75000, /* SDRAM frequency */ + .regs = { + 0x00000005, /* RC */ + 0x0000000a, /* RFC */ + 0x00000004, /* RAS */ + 0x00000003, /* RP */ + 0x00000006, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x00000009, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000002, /* REXT */ + 0x00000002, /* WDV */ + 0x00000005, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000008, /* QSAFE */ + 0x0000000b, /* RDV */ + 0x000000ff, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000a, /* RW2PDEN */ + 0x0000000b, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000008, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000138, /* TREFBW */ + 0x00000004, /* QUSE_EXTRA */ + 0x00000000, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000082, /* FBIO_CFG5 */ + 0xa06a04ae, /* CFG_DIG_DLL */ + 0x00070000, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000007, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + .rate = 150000, /* SDRAM frequency */ .regs = { 0x00000009, /* RC */ 0x00000014, /* RFC */ @@ -164,8 +371,8 @@ static const struct tegra_emc_table stingray_emc_tables_samsung[] = { 0x00000000, /* ODT_WRITE */ 0x00000000, /* ODT_READ */ 0x00000082, /* FBIO_CFG5 */ - 0xa06804ae, /* CFG_DIG_DLL */ - 0x007fe010, /* DLL_XFORM_DQS */ + 0xa04c04ae, /* CFG_DIG_DLL */ + 0x007e0010, /* DLL_XFORM_DQS */ 0x00000000, /* DLL_XFORM_QUSE */ 0x00000000, /* ZCAL_REF_CNT */ 0x0000000e, /* ZCAL_WAIT_CNT */ @@ -176,7 +383,7 @@ static const struct tegra_emc_table stingray_emc_tables_samsung[] = { } }, { - .rate = 300000, /* SDRAM frquency */ + .rate = 300000, /* SDRAM frequency */ .regs = { 0x00000012, /* RC */ 0x00000027, /* RFC */ @@ -215,8 +422,8 @@ static const struct tegra_emc_table stingray_emc_tables_samsung[] = { 0x00000000, /* ODT_WRITE */ 0x00000000, /* ODT_READ */ 0x00000282, /* FBIO_CFG5 */ - 0xe04c048b, /* CFG_DIG_DLL */ - 0x007fd010, /* DLL_XFORM_DQS */ + 0xe03c048b, /* CFG_DIG_DLL */ + 0x007e0010, /* DLL_XFORM_DQS */ 0x00000000, /* DLL_XFORM_QUSE */ 0x00000000, /* ZCAL_REF_CNT */ 0x0000001b, /* ZCAL_WAIT_CNT */ @@ -228,12 +435,63 @@ static const struct tegra_emc_table stingray_emc_tables_samsung[] = { } }; -static const struct tegra_emc_table stingray_emc_tables_elpida[] = { +static const struct tegra_emc_table stingray_emc_tables_elpida_40nm[] = { { - .rate = 60000, /* SDRAM frquency */ + .rate = 25000, /* SDRAM frequency */ .regs = { - 0x00000004, /* RC */ - 0x00000008, /* RFC */ + 0x00000002, /* RC */ + 0x00000006, /* RFC */ + 0x00000003, /* RAS */ + 0x00000003, /* RP */ + 0x00000006, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x00000009, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000002, /* REXT */ + 0x00000002, /* WDV */ + 0x00000004, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000008, /* QSAFE */ + 0x0000000b, /* RDV */ + 0x0000004d, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000a, /* RW2PDEN */ + 0x00000004, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000008, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000068, /* TREFBW */ + 0x00000003, /* QUSE_EXTRA */ + 0x00000003, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000082, /* FBIO_CFG5 */ + 0xa0ae04ae, /* CFG_DIG_DLL */ + 0x00070000, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000003, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + .rate = 50000, /* SDRAM frequency */ + .regs = { + 0x00000003, /* RC */ + 0x00000007, /* RFC */ 0x00000003, /* RAS */ 0x00000003, /* RP */ 0x00000006, /* R2W */ @@ -249,7 +507,7 @@ static const struct tegra_emc_table stingray_emc_tables_elpida[] = { 0x00000003, /* QRST */ 0x00000008, /* QSAFE */ 0x0000000b, /* RDV */ - 0x000000a8, /* REFRESH */ + 0x0000009f, /* REFRESH */ 0x00000000, /* BURST_REFRESH_NUM */ 0x00000003, /* PDEX2WR */ 0x00000003, /* PDEX2RD */ @@ -257,20 +515,20 @@ static const struct tegra_emc_table stingray_emc_tables_elpida[] = { 0x00000008, /* ACT2PDEN */ 0x00000001, /* AR2PDEN */ 0x0000000a, /* RW2PDEN */ - 0x00000008, /* TXSR */ + 0x00000007, /* TXSR */ 0x00000003, /* TCKE */ 0x00000008, /* TFAW */ 0x00000004, /* TRPAB */ 0x00000006, /* TCLKSTABLE */ 0x00000002, /* TCLKSTOP */ - 0x000000e1, /* TREFBW */ + 0x000000d0, /* TREFBW */ 0x00000004, /* QUSE_EXTRA */ 0x00000000, /* FBIO_CFG6 */ 0x00000000, /* ODT_WRITE */ 0x00000000, /* ODT_READ */ 0x00000082, /* FBIO_CFG5 */ - 0xa06804ae, /* CFG_DIG_DLL */ - 0x00004810, /* DLL_XFORM_DQS */ + 0xa0ae04ae, /* CFG_DIG_DLL */ + 0x00070000, /* DLL_XFORM_DQS */ 0x00000000, /* DLL_XFORM_QUSE */ 0x00000000, /* ZCAL_REF_CNT */ 0x00000005, /* ZCAL_WAIT_CNT */ @@ -281,11 +539,11 @@ static const struct tegra_emc_table stingray_emc_tables_elpida[] = { } }, { - .rate = 120000, /* SDRAM frquency */ + .rate = 75000, /* SDRAM frequency */ .regs = { - 0x00000007, /* RC */ - 0x0000000f, /* RFC */ - 0x00000005, /* RAS */ + 0x00000005, /* RC */ + 0x0000000a, /* RFC */ + 0x00000004, /* RAS */ 0x00000003, /* RP */ 0x00000006, /* R2W */ 0x00000004, /* W2R */ @@ -300,7 +558,7 @@ static const struct tegra_emc_table stingray_emc_tables_elpida[] = { 0x00000003, /* QRST */ 0x00000008, /* QSAFE */ 0x0000000b, /* RDV */ - 0x0000017f, /* REFRESH */ + 0x000000ff, /* REFRESH */ 0x00000000, /* BURST_REFRESH_NUM */ 0x00000003, /* PDEX2WR */ 0x00000003, /* PDEX2RD */ @@ -308,23 +566,23 @@ static const struct tegra_emc_table stingray_emc_tables_elpida[] = { 0x00000008, /* ACT2PDEN */ 0x00000001, /* AR2PDEN */ 0x0000000a, /* RW2PDEN */ - 0x00000010, /* TXSR */ + 0x0000000b, /* TXSR */ 0x00000003, /* TCKE */ 0x00000008, /* TFAW */ 0x00000004, /* TRPAB */ 0x00000006, /* TCLKSTABLE */ 0x00000002, /* TCLKSTOP */ - 0x000001c2, /* TREFBW */ + 0x00000138, /* TREFBW */ 0x00000004, /* QUSE_EXTRA */ - 0x00000001, /* FBIO_CFG6 */ + 0x00000000, /* FBIO_CFG6 */ 0x00000000, /* ODT_WRITE */ 0x00000000, /* ODT_READ */ 0x00000082, /* FBIO_CFG5 */ - 0xa06804ae, /* CFG_DIG_DLL */ - 0x007fd010, /* DLL_XFORM_DQS */ + 0xa0ae04ae, /* CFG_DIG_DLL */ + 0x00070000, /* DLL_XFORM_DQS */ 0x00000000, /* DLL_XFORM_QUSE */ 0x00000000, /* ZCAL_REF_CNT */ - 0x0000000a, /* ZCAL_WAIT_CNT */ + 0x00000007, /* ZCAL_WAIT_CNT */ 0x00000000, /* AUTO_CAL_INTERVAL */ 0x00000000, /* CFG_CLKTRIM_0 */ 0x00000000, /* CFG_CLKTRIM_1 */ @@ -332,7 +590,7 @@ static const struct tegra_emc_table stingray_emc_tables_elpida[] = { } }, { - .rate = 200000, /* SDRAM frquency */ + .rate = 150000, /* SDRAM frequency */ .regs = { 0x00000009, /* RC */ 0x00000014, /* RFC */ @@ -371,8 +629,8 @@ static const struct tegra_emc_table stingray_emc_tables_elpida[] = { 0x00000000, /* ODT_WRITE */ 0x00000000, /* ODT_READ */ 0x00000082, /* FBIO_CFG5 */ - 0xa04c04ae, /* CFG_DIG_DLL */ - 0x007fe010, /* DLL_XFORM_DQS */ + 0xa07c04ae, /* CFG_DIG_DLL */ + 0x007de010, /* DLL_XFORM_DQS */ 0x00000000, /* DLL_XFORM_QUSE */ 0x00000000, /* ZCAL_REF_CNT */ 0x0000000e, /* ZCAL_WAIT_CNT */ @@ -383,7 +641,7 @@ static const struct tegra_emc_table stingray_emc_tables_elpida[] = { } }, { - .rate = 300000, /* SDRAM frquency */ + .rate = 300000, /* SDRAM frequency */ .regs = { 0x00000012, /* RC */ 0x00000027, /* RFC */ @@ -422,8 +680,8 @@ static const struct tegra_emc_table stingray_emc_tables_elpida[] = { 0x00000000, /* ODT_WRITE */ 0x00000000, /* ODT_READ */ 0x00000282, /* FBIO_CFG5 */ - 0xe03c048b, /* CFG_DIG_DLL */ - 0x007fb010, /* DLL_XFORM_DQS */ + 0xe059048b, /* CFG_DIG_DLL */ + 0x007e4010, /* DLL_XFORM_DQS */ 0x00000000, /* DLL_XFORM_QUSE */ 0x00000000, /* ZCAL_REF_CNT */ 0x0000001b, /* ZCAL_WAIT_CNT */ @@ -445,15 +703,24 @@ struct tegra_emc_chip stingray_emc_chips[] = { .table = stingray_emc_tables_samsung, .table_size = ARRAY_SIZE(stingray_emc_tables_samsung) }, + { + .description = "Elpida 40nm", + .mem_manufacturer_id = 0x0303, + .mem_revision_id1 = 0x0101, + .mem_revision_id2 = -1, + .mem_pid = 0x5454, + .table = stingray_emc_tables_elpida_40nm, + .table_size = ARRAY_SIZE(stingray_emc_tables_elpida_40nm) + }, { .description = "Elpida 50nm", .mem_manufacturer_id = 0x0303, .mem_revision_id1 = -1, .mem_revision_id2 = -1, .mem_pid = 0x5454, - .table = stingray_emc_tables_elpida, - .table_size = ARRAY_SIZE(stingray_emc_tables_elpida) - } + .table = stingray_emc_tables_elpida_50nm, + .table_size = ARRAY_SIZE(stingray_emc_tables_elpida_50nm) + }, }; void stingray_init_emc(void) -- 2.34.1