From 7d71a87aae80e04bba49b2c491e3c291325431a6 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Mon, 24 Sep 2012 20:35:36 +0800 Subject: [PATCH] rk30: no set gpu/vcodec/vio qos on init, which will reset after power domain on --- arch/arm/mach-rk30/common.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-rk30/common.c b/arch/arm/mach-rk30/common.c index 8c8635e57358..b72bf1174750 100755 --- a/arch/arm/mach-rk30/common.c +++ b/arch/arm/mach-rk30/common.c @@ -28,6 +28,7 @@ static void __init rk30_cpu_axi_init(void) #else writel_relaxed(0x0, RK30_CPU_AXI_BUS_BASE + 0x4008); // peri #endif +#if 0 writel_relaxed(0x0, RK30_CPU_AXI_BUS_BASE + 0x5008); // gpu writel_relaxed(0x0, RK30_CPU_AXI_BUS_BASE + 0x6008); // vpu writel_relaxed(0xa, RK30_CPU_AXI_BUS_BASE + 0x7008); // lcdc0 @@ -36,6 +37,7 @@ static void __init rk30_cpu_axi_init(void) writel_relaxed(0xa, RK30_CPU_AXI_BUS_BASE + 0x7188); // lcdc1 writel_relaxed(0x0, RK30_CPU_AXI_BUS_BASE + 0x7208); // cif1 writel_relaxed(0x0, RK30_CPU_AXI_BUS_BASE + 0x7288); // rga +#endif writel_relaxed(0x3f, RK30_CPU_AXI_BUS_BASE + 0x0014); // memory scheduler read latency dsb(); } -- 2.34.1