From 7d91eb51dc7ada831c88942c5bc36582f14043da Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E6=9E=97=E8=BE=89=E8=BE=89?= Date: Mon, 26 Apr 2010 07:43:24 +0000 Subject: [PATCH] add iomux driver --- arch/arm/mach-rk2818/Makefile | 2 +- arch/arm/mach-rk2818/board-midsdk.c | 3 +- arch/arm/mach-rk2818/include/mach/iomux.h | 225 ++++++++++++++++++++++ arch/arm/mach-rk2818/iomux.c | 129 +++++++++++++ drivers/serial/rk2818_serial.c | 5 +- 5 files changed, 360 insertions(+), 4 deletions(-) create mode 100644 arch/arm/mach-rk2818/include/mach/iomux.h create mode 100644 arch/arm/mach-rk2818/iomux.c diff --git a/arch/arm/mach-rk2818/Makefile b/arch/arm/mach-rk2818/Makefile index 78ffd575c806..d131022af38a 100644 --- a/arch/arm/mach-rk2818/Makefile +++ b/arch/arm/mach-rk2818/Makefile @@ -1,4 +1,4 @@ -obj-y += io.o idle.o irq.o timer.o +obj-y += io.o idle.o irq.o timer.o iomux.o obj-y += devices.o obj-y += proc_comm.o obj-y += vreg.o diff --git a/arch/arm/mach-rk2818/board-midsdk.c b/arch/arm/mach-rk2818/board-midsdk.c index 09bcd9b8b9ee..243bd7b040ce 100644 --- a/arch/arm/mach-rk2818/board-midsdk.c +++ b/arch/arm/mach-rk2818/board-midsdk.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -110,7 +111,7 @@ static void __init machine_rk2818_mapio(void) iotable_init(rk2818_io_desc, ARRAY_SIZE(rk2818_io_desc)); rk2818_clock_init(); printk("%s [%d]\n",__FUNCTION__,__LINE__); - //rk2818_iomux_init(); + rk2818_iomux_init(); } MACHINE_START(RK2818, "rk2818midsdk") diff --git a/arch/arm/mach-rk2818/include/mach/iomux.h b/arch/arm/mach-rk2818/include/mach/iomux.h new file mode 100644 index 000000000000..d64a2e5de641 --- /dev/null +++ b/arch/arm/mach-rk2818/include/mach/iomux.h @@ -0,0 +1,225 @@ +/* + * arch/arm/mach-rk2818/include/mach/iomux.h + * + *Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __RK2818_IOMUX_H__ +#define __RK2818_IOMUX_H__ + +//IOMUX_A_CON +#define IOMUXA_I2C0 (0) +#define IOMUXA_GPIO1_A45 (1) +#define IOMUXA_GPIO1_A67 (0) +#define IOMUXA_UART1_SIR (1) +#define IOMUXA_I2C1 (2) +#define IOMUXA_GPIO1_B1 (0) +#define IOMUXA_UART1_SOUT (1) +#define IOMUXA_CX_TIMER1_PMW (2) +#define IOMUXA_GPIO1_B0 (0) +#define IOMUXA_UART1_SIN (1) +#define IOMUXA_CX_TIMER0_PWM (2) +#define IOMUXA_GPIO1_C237 (0) +#define IOMUXA_SDMMC1_CMD_DATA0_CLKOUT (1) +#define IOMUXA_GPIO1_C456 (0) +#define IOMUXA_SDMMC1_DATA123 (1) +#define IOMUXA_GPIO1_A3B7 (0) +#define IOMUXA_SPI1_RXD_TXD (1) +#define IOMUXA_FLASH_CS67 (2) +#define IOMUXA_GPIO1_A12 (0) +#define IOMUXA_CLKIN_SSINN (1) +#define IOMUXA_FLASH_CS45 (2) (1) +#define IOMUXA_GPIO0_B0 (0) +#define IOMUXA_SPI0_CSN1 (1) +#define IOMUXA_SDMMC1_PWR_EN (2) +#define IOMUXA_GPIO1_C1 (0) +#define IOMUXA_UART0_SOUT (1) +#define IOMUXA_SDMMC1_WRITE_PRT (2) +#define IOMUXA_GPIO1_C0 (0) +#define IOMUXA_UART0_SIN (1) +#define IOMUXA_SDMMC1_DETECT_N (2) +#define IOMUXA_GPIO1_B4 (0) +#define IOMUXA_PWM2 (1) +#define IOMUXA_SDMMC0_WRITE_PRT (2) +#define IOMUXA_GPIO1_B3 (0) +#define IOMUXA_PWM1 (1) +#define IOMUXA_SDMMC0_DETECT_N (2) +#define IOMUXA_GPIO0_B1 (0) +#define IOMUXA_SM_CS1_N (1) +#define IOMUXA_SDMMC0_PWR_EN (2) +#define IOMUXA_GPIO1_D234 (0) +#define IOMUXA_SDMMC0_DATA123 (1) +#define IOMUXA_GPIO1_D015 (0) +#define IOMUXA_SDMMC0_CMD_DATA0_CLKOUT (1) +#define IOMUXA_GPIO0_B567 (0) +#define IOMUXA_SPI0 (1) +#define IOMUXA_SDMMC0_DATA567 (2) +#define IOMUXA_GPIO0_B4 (0) +#define IOMUXA_SPI0_CSN0 (1) +#define IOMUXA_SDMMC0_DATA4 (2) + +///IOMUX_B_CON +#define IOMUXB_GPIO1_B34 (0) +#define IOMUXB_UART3_IN_OUT (1) +#define IOMUXB_GPIO0_B01 (0) +#define IOMUXB_UART2_IN_OUT (1) +#define IOMUXB_GPIO0_A23 (0) +#define IOMUXB_UART2_CTS_RTS (1) +#define IOMUXB_GPIO2_22_23 (0) +#define IOMUXB_HSADC_DATA_Q89 (1) +#define IOMUXB_SM_WE_SM_OE (2) +#define IOMUXB_GPIO2_14_TO_21 (0) +#define IOMUXB_HSADC_DATA_Q7_TO_Q0 (1) +#define IOMUXB_HOST_DATA15_TO_8 (2) +#define IOMUXB_GPIO0_A1 (0) +#define IOMUXB_HOST_DATA17 (1) +#define IOMUXB_GPIO0_A0 (0) +#define IOMUXB_HOST_DATA16 (1) +#define IOMUXB_GPIO1_A0 (0) +#define IOMUXB_VIP_DATA0 (1) +#define IOMUXB_GPIO2_24 (0) +#define IOMUXB_GPS_CLK (1) +#define IOMUXB_HSADC_CLKOUT (2) +#define IOMUXB_HSADC_DATA_I98 (0) +#define IOMUXB_TS_FAIL_TS_VALID (1) +#define IOMUXB_GPIO0_A7 (0) +#define IOMUXB_FLASH_CS3 (1) +#define IOMUXB_GPIO0_A6 (0) +#define IOMUXB_FLASH_CS2 (1) +#define IOMUXB_GPIO0_A5 (0) +#define IOMUXB_FLASH_CS1 (1) +#define IOMUXB_GPIO1_B5 (0) +#define IOMUXB_PWM3 (1) +#define IOMUXB_DEMOD_PWM_OUT (2) +#define IOMUXB_GPIO0_B3 (0) +#define IOMUXB_UART0_RTS_N (1) +#define IOMUXB_GPIO0_B2 (0) +#define IOMUXB_UART0_CTS_N (1) +#define IOMUXB_GPIO1_B2 (0) +#define IOMUXB_PWM0 (1) +#define IOMUXB_GPIO0_D0_7 (0) +#define IOMUXB_LCDC_DATA8_15 (1) +#define IOMUXB_GPIO0_C2_7 (0) +#define IOMUXB_LCDC_DATA18_23 (1) +#define IOMUXB_GPIO0_C01 (0) +#define IOMUXB_LCDC_DATA16_17 (1) +#define IOMUXB_GPIO2_26 (0) +#define IOMUXB_LCDC_DENABLE (1) +#define IOMUXB_GPIO2_25 (0) +#define IOMUXB_LCDC_VSYNC (1) +#define IOMUXB_GPIO2_14_23 (0) +#define IOMUXB_HSADC_DATA9_0 (1) +#define IOMUXB_GPIO2_0_13 (0) +#define IOMUXB_HOST_INTERFACE (1) +#define IOMUXB_GPIO1_D7 (0) +#define IOMUXB_HSADC_CLKIN (1) +#define IOMUXB_GPIO1_D6 (0) +#define IOMUXB_EXT_IQ_INDEX (1) +#define IOMUXB_I2S_INTERFACE (0) +#define IOMUXB_GPIO2_27_31 (1) +#define IOMUXB_GPIO1_B6 (0) +#define IOMUXB_VIP_CLKOUT (1) + +#define DEFAULT 0 +#define INITIAL 1 + + + +#define GPIOE_I2C0_SEL_NAME "gpioe_i2c0_sel" +#define GPIOE_U1IR_I2C1_NAME "gpioe_u1ir_i2c1" +#define GPIOF1_UART1_CPWM1_NAME "gpiof1_uart1_cpwm1" +#define GPIOF0_UART1_CPWM0_NAME "gpiof0_uart1_cpwm0" +#define GPIOG_MMC1_SEL_NAME "gpiog_mmc1_sel" +#define GPIOG_MMC1D_SEL_NAME "gpiog_mmc1d_sel" +#define GPIOE_SPI1_FLASH_SEL_NAME "gpioe_spi1_flash2" +#define GPIOE_SPI1_FLASH_SEL1_NAME "gpioe_spi1_flash1" +#define GPIOB0_SPI0CSN1_MMC1PCA_NAME "gpiob0_spi0csn1_mmc1pca" +#define GPIOG1_UART0_MMC1WPT_NAME "gpiog1_uart0_mmc1wpt" +#define GPIOG0_UART0_MMC1DET_NAME "gpiog0_uart0_mmc1det" +#define GPIOF4_APWM2_MMC0WPT_NAME "gpiof4_apwm2_mmc0wpt" +#define GPIOF3_APWM1_MMC0DETN_NAME "gpiof3_apwm1_mmc0detn" +#define GPIOB1_SMCS1_MMC0PCA_NAME "gpiob1_smcs1_mmc0pca" +#define GPIOH_MMC0D_SEL_NAME "gpioh_mmc0d_sel" +#define GPIOH_MMC0_SEL_NAME "gpioh_mmc0_sel" +#define GPIOB_SPI0_MMC0_NAME "gpiob_spi0_mmc0" +#define GPIOB4_SPI0CS0_MMC0D4_NAME "gpiob4_spi0cs0_mmc0d4" + +#define GPIOF34_UART3_SEL_NAME "gpiof34_uart3" +#define GPIOF01_UART2_SEL_NAME "gpiof01_uart2" +#define GPIOA23_UART2_SEL_NAME "gpioa23_uart2" +#define CXGPIO_HSADC_NORFLASH_SEL_NAME "cxgpio_hsadc_norflash" +#define CXGPIO_HSADC_HIF_SEL_NAME "cxgpio_hsadc_hif" +#define GPIOA1_HOSTDATA17_SEL_NAME "gpioa1_hostdata17" +#define GPIOA0_HOSTDATA16_SEL_NAME "gpioa0_hostdata16" +#define GPIOE0_VIPDATA0_SEL_NAME "gpioe0_vipdata0" +#define CXGPIO_GPSCLK_HSADCCLKOUT_NAME "cxgpio_gpsclk_hsadcclkout" +#define HSADCDATA_TSCON_SEL_NAME "hsadcdata_tscon_sel" +#define GPIOA7_FLASHCS3_SEL_NAME "gpioa7_flashcs3_sel" +#define GPIOA6_FLASHCS2_SEL_NAME "gpioa6_flashcs2_sel" +#define GPIOA5_FLASHCS1_SEL_NAME "gpioa5_flashcs1_sel" +#define GPIOF5_APWM3_DPWM3_NAME "gpiof5_apwm3_dpwm" +#define GPIOB3_U0RTSN_SEL_NAME "gpiob3_u0rtsn_sel" +#define GPIOB2_U0CTSN_SEL_NAME "gpiob2_u0ctsn_sel" +#define GPIOF2_APWM0_SEL_NAME "gpiof2_apwm0_sel" +#define GPIOC_LCDC16BIT_SEL_NAME "gpiod_lcdc16bit_sel" +#define GPIOC_LCDC24BIT_SEL_NAME "gpioc_lcdc24bit_sel" +#define GPIOC_LCDC18BIT_SEL_NAME "gpioc_lcdc18bit_sel" +#define CXGPIO_LCDDEN_SEL_NAME "cxgpio_lcdden_sel" +#define CXGPIO_LCDVSYNC_SEL_NAME "cxgpio_lcdvsync_sel" +#define CXGPIO_HSADC_SEL_NAME "cxgpio_hsadc_sel" +#define CXGPIO_HOST_SEL_NAME "cxgpio_host_sel" +#define GPIOH7_HSADCCLK_SEL_NAME "gpioh7_hsadcclk_sel" +#define GPIOH6_IQ_SEL_NAME "gpioh6_iq_sel" +#define CXGPIO_I2S_SEL_NAME "cxgpio_i2s_sel" +#define GPIOF6_VIPCLK_SEL_NAME "gpiof6_vipclk_sel" + +#define CPU_APB_REG0 0x00 +#define CPU_APB_REG1 0x04 +#define CPU_APB_REG2 0x08 +#define CPU_APB_REG3 0x0c +#define CPU_APB_REG4 0x10 +#define CPU_APB_REG5 0x14 +#define CPU_APB_REG6 0x18 +#define CPU_APB_REG7 0x1c +#define IOMUX_A_CON 0x20 +#define IOMUX_B_CON 0x24 +#define GPIO0_AB_PU_CON 0x28 +#define GPIO0_CD_PU_CON 0x2c +#define GPIO1_AB_PU_CON 0x30 +#define GPIO1_CD_PU_CON 0x34 +#define OTGPHY_CON0 0x38 +#define OTGPHY_CON1 0x3c + + +#define MUX_CFG(desc,reg,off,interl,mux_mode,bflags) \ +{ \ + .name = desc, \ + .offset = off, \ + .interleave = interl, \ + .mux_reg = RK2818_IOMUX_##reg##_CON, \ + .mode = mux_mode, \ + .flags = bflags, \ +}, + +struct mux_config { + char *name; + const unsigned int offset; + unsigned int mode; + const unsigned int mux_reg; + const unsigned int interleave; + unsigned int flags; +}; + +extern int rk2818_iomux_init(void); +extern void rk2818_mux_api_set(char *name, unsigned int mode); +#endif + diff --git a/arch/arm/mach-rk2818/iomux.c b/arch/arm/mach-rk2818/iomux.c new file mode 100644 index 000000000000..dfa5022c7c46 --- /dev/null +++ b/arch/arm/mach-rk2818/iomux.c @@ -0,0 +1,129 @@ +/* + * arch/arm/mach-rk2818/iomux.c + * + *Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include +#include +#include +#include +#include + +#include +#include + + +#define RK2818_IOMUX_A_CON (RK2818_REGFILE_BASE + IOMUX_A_CON) +#define RK2818_IOMUX_B_CON (RK2818_REGFILE_BASE + IOMUX_B_CON) + +static struct mux_config __initdata_or_module rk2818_muxs[] = { +/* + * description mux mode mux mux + * reg offset inter mode + */ +MUX_CFG(GPIOE_I2C0_SEL_NAME, A, 30, 2, 0, DEFAULT) /* 0: i2c0_sda/scl gpioe_u1ir_i2c1 */ +MUX_CFG(GPIOE_U1IR_I2C1_NAME, A, 28, 2, 0, DEFAULT) /* 00 : gpio_e6/e7 01 gpiof1_uart1_cpwm1_out_n 10 : i2c1_sda/scl */ +MUX_CFG(GPIOF1_UART1_CPWM1_NAME, A, 26, 2, 1, DEFAULT) /* 00 : gpio_f1 01 : uart1_sout 10 : cx_timer1_pwm */ +MUX_CFG(GPIOF0_UART1_CPWM0_NAME, A, 24, 2, 1, DEFAULT) /* 00 : gpio_f0 01 : uart1_sin 10 : cx_timer0_pwm */ +MUX_CFG(GPIOG_MMC1_SEL_NAME, A, 23, 1, 0, DEFAULT) /* 0 : gpio_g2/g3/g7 1: sdmmc1_cmd/data0/clkout */ +MUX_CFG(GPIOG_MMC1D_SEL_NAME, A, 22, 1, 0, DEFAULT) /* 0 : gpio_g4/g5/g6 1 : sdmmc1_data1/data2/data3 */ +MUX_CFG(GPIOE_SPI1_FLASH_SEL_NAME, A, 20, 2, 0, DEFAULT) /* 00 : gpio_e1/e2/e3/f7 01 : spi1_clkin/spi1_ss_in_n/spi1_rxd/spi1_txd 10 :flash_cs6 / flash_cs7*/ +MUX_CFG(GPIOE_SPI1_FLASH_SEL1_NAME, A, 18, 2, 0, DEFAULT) /*00 : gpio1_a1/a2 01 : spi1_clkin/spi1_ss_in_n 10 : flash_cs4 / flash_cs5 */ +MUX_CFG(GPIOB0_SPI0CSN1_MMC1PCA_NAME, A, 16, 2, 0, DEFAULT) /* 00 : gpio_b0 01 : spi0_csn1 10 : sdmmc1_pwr_en */ +MUX_CFG(GPIOG1_UART0_MMC1WPT_NAME, A, 14, 2, 0, DEFAULT) /* 00 : gpio_g1 01 : uart0_sout 10 : sdmmc1_write_prt */ +MUX_CFG(GPIOG0_UART0_MMC1DET_NAME, A, 12, 2, 0, DEFAULT) /* 00 : gpio_g0 01 : uart0_sin 10 : sdmmc1_detect_n */ +MUX_CFG(GPIOF4_APWM2_MMC0WPT_NAME, A, 10, 2, 0, DEFAULT) /* 00 : gpio_f4 01 : pwm2 10 : sdmmc0_write_prt */ +MUX_CFG(GPIOF3_APWM1_MMC0DETN_NAME, A, 8, 2, 0, DEFAULT) /* 00 : gpio_f3 01 : pwm1 10 : sdmmc0_detect_n */ +MUX_CFG(GPIOB1_SMCS1_MMC0PCA_NAME, A, 6, 2, 0, DEFAULT) /* 00 : gpio_b1 01 : sm_cs1_n 10 : sdmmc0_pwr_en */ +MUX_CFG(GPIOH_MMC0D_SEL_NAME, A, 5, 1, 0, DEFAULT) /* 0 : gpio_h2/h3/h4 1 : sdmm0_data1/data2/data3 */ +MUX_CFG(GPIOH_MMC0_SEL_NAME, A, 4, 1, 0, DEFAULT) /* 0 : gpio_h0/h1/h5 1 : sdmmc0_cmd/data0/clkout */ +MUX_CFG(GPIOB_SPI0_MMC0_NAME, A, 2, 2, 0, DEFAULT) /* 00 : gpio_b5/b6/b7 01 : spi0_clkout/spi0_txd/spi0_rxd 10 : sdmmc0_data5/data6/data7 */ +MUX_CFG(GPIOB4_SPI0CS0_MMC0D4_NAME, A, 0, 2, 0, DEFAULT) /* 00 : gpio_b4 01 : spi0_csn0 10 : sdmmc0_data4 */ + +MUX_CFG(GPIOF34_UART3_SEL_NAME, B, 31, 1, 0, DEFAULT) /*0 : gpio1_b3 / gpio1_b4 function is decided by gpio1b3_apwm1_mmc0detn(IOMUX_A_CON[9:8]) and gpio1b4_apwm2_mmc0wpt(IOMUX_A_CON[11:10] separately 1 : uart3_sin / uart3_sout*/ +MUX_CFG(GPIOF01_UART2_SEL_NAME, B, 30, 1, 0, DEFAULT) /*0 : gpio0_b0 / gpio0_b1 function is decided by gpio0b0_spi0csn1_mmc1pca(IOMUX_A_CON [17:16]) and gpio0b1_smcs1_mmc0pca(IOMUX_A_CON [7:6] separately 1 : uart2_sin / uart2_sout */ +MUX_CFG(GPIOA23_UART2_SEL_NAME, B, 29, 1, 0, DEFAULT) /*0 : gpio0_a2/gpio0_a3 1 : uart2_cts_n / uart2_rts_n */ +MUX_CFG(CXGPIO_HSADC_NORFLASH_SEL_NAME, B, 27, 2, 0, DEFAULT) /*00 : gpio2_22 ~ gpio2_23 01 : hsadc_data_q[9:8] 10 : sm_we_n/sm_oe_n */ +MUX_CFG(CXGPIO_HSADC_HIF_SEL_NAME, B, 25, 2, 0, DEFAULT) /*00 : gpio2_14 ~ gpio2_21 01 : hsadc_data_q[7:0] 10 : host_data[15:8]*/ +MUX_CFG(GPIOA1_HOSTDATA17_SEL_NAME, B, 24, 1, 0, DEFAULT) /*0 : gpio0_a1 1: host data 17 */ +MUX_CFG(GPIOA0_HOSTDATA16_SEL_NAME, B, 23, 1, 0, DEFAULT) /*0 : gpio0_a0 1: host data 16 */ +MUX_CFG(GPIOE0_VIPDATA0_SEL_NAME, B, 22, 1, 0, DEFAULT) /*0: gpio1_a0 1: vip_data0 */ +MUX_CFG(CXGPIO_GPSCLK_HSADCCLKOUT_NAME, B, 20, 2, 0, DEFAULT) /* 00 : gpio2_24 01 : gps clk 10 : hsadc_clkout */ +MUX_CFG(HSADCDATA_TSCON_SEL_NAME, B, 19, 1, 0, DEFAULT) /* 0: hsadc_data_i[9:8] 1: ts_fail / ts_valid */ +MUX_CFG(GPIOA7_FLASHCS3_SEL_NAME, B, 18, 1, 0, DEFAULT) /* 0 : gpio_a7 1 : flash_cs3 */ +MUX_CFG(GPIOA6_FLASHCS2_SEL_NAME, B, 17, 1, 0, DEFAULT) /* 0 : gpio_a6 1 : flash_cs2 */ +MUX_CFG(GPIOA5_FLASHCS1_SEL_NAME, B, 16, 1, 0, DEFAULT) /* 0 : gpio_a5 1 : flash_cs1 */ +MUX_CFG(GPIOF5_APWM3_DPWM3_NAME, B, 14, 2, 0, DEFAULT) /* 00 : gpio_f5 01 : pwm3 10 : demod pwm out */ +MUX_CFG(GPIOB3_U0RTSN_SEL_NAME, B, 13, 1, 0, DEFAULT) /* 0 : gpio_b3 1 : uart0_rts_n */ +MUX_CFG(GPIOB2_U0CTSN_SEL_NAME, B, 12, 1, 0, DEFAULT) /* 0 : gpio_b2 1 : uart0_cts_n */ +MUX_CFG(GPIOF2_APWM0_SEL_NAME, B, 11, 1, 0, INITIAL) /* 0 : gpio_f2 1 : pwm0 */ +MUX_CFG(GPIOC_LCDC16BIT_SEL_NAME, B, 10, 1, 1, INITIAL) /* 0 : gpio_d0 ~ gpio_d7 1 : lcdc_data8 ~ lcdc_data15 */ +MUX_CFG(GPIOC_LCDC24BIT_SEL_NAME, B, 9, 1, 1, INITIAL) /* 0 : gpio_c2 ~ gpio_c7 1 : lcdc_data18 ~ lcdc_data23 */ +MUX_CFG(GPIOC_LCDC18BIT_SEL_NAME, B, 8, 1, 1, INITIAL) /* 0 : gpio_c0/c1 1 : lcdc_data16 ~ lcdc_data17 */ +MUX_CFG(CXGPIO_LCDDEN_SEL_NAME, B, 7, 1, 1, INITIAL) /* 0 : gpio2_26 1 : lcdc_denable */ +MUX_CFG(CXGPIO_LCDVSYNC_SEL_NAME, B, 6, 1, 1, INITIAL) /* 0 : gpio2_25 1 : lcdc_vsync */ +MUX_CFG(CXGPIO_HSADC_SEL_NAME, B, 5, 1, 0, DEFAULT) /* 0 : gpio2_14 ~ gpio2_23 1 : hsadc_data_q[9:0] */ +MUX_CFG(CXGPIO_HOST_SEL_NAME, B, 4, 1, 0, DEFAULT) /* 0 : gpio2_0 ~ gpio2_13 1 : host interface */ +MUX_CFG(GPIOH7_HSADCCLK_SEL_NAME, B, 3, 1, 0, DEFAULT) /* 0 : gpio_h7 1 : hsadc_clkin */ +MUX_CFG(GPIOH6_IQ_SEL_NAME, B, 2, 1, 0, DEFAULT) /* 0 : gpio_h6 1 : ext_iq_index */ +MUX_CFG(CXGPIO_I2S_SEL_NAME, B, 1, 1, 0, DEFAULT) /* 0 : i2s interface 1 : gpio2_27 ~ gpio2_31 */ +MUX_CFG(GPIOF6_VIPCLK_SEL_NAME, B, 0, 1, 0, DEFAULT) /* 0 : gpio_f6 1 : vip clkout */ +}; + +void rk2818_mux_set(struct mux_config *cfg) +{ + int regValue; + int mask; + + mask = ((1<<(cfg->interleave))-1)<offset; + regValue = readl(cfg->mux_reg); + regValue &=~mask; + regValue |=(cfg->mode<offset); + #ifdef DEBUG_LHH + printk("%s::regValue is %x,mask is %x\n",__FUNCTION__,regValue,mask); + #endif + writel(regValue,cfg->mux_reg); + + return; +} + +int rk2818_iomux_init(void) +{ + int i; + for(i=0;iname) + if (!strcmp(rk2818_muxs[i].name, name)) + { + rk2818_muxs[i].mode = mode; + rk2818_mux_set(&rk2818_muxs[i]); + break; + } + } +} +EXPORT_SYMBOL(rk2818_mux_api_set); diff --git a/drivers/serial/rk2818_serial.c b/drivers/serial/rk2818_serial.c index 1bdd67749698..2953271fcac8 100644 --- a/drivers/serial/rk2818_serial.c +++ b/drivers/serial/rk2818_serial.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "rk2818_serial.h" @@ -333,8 +334,8 @@ static void rk2818_serial_set_termios(struct uart_port *port, struct ktermios *t if(termios->c_cflag & CRTSCTS) { /*¿ªÆôuart0Ó²¼þÁ÷¿Ø*/ - //rk2818_mux_api_set(GPIOB2_U0CTSN_SEL_NAME, IOMUXB_UART0_CTS_N); - //rk2818_mux_api_set(GPIOB3_U0RTSN_SEL_NAME, IOMUXB_UART0_RTS_N); + rk2818_mux_api_set(GPIOB2_U0CTSN_SEL_NAME, IOMUXB_UART0_CTS_N); + rk2818_mux_api_set(GPIOB3_U0RTSN_SEL_NAME, IOMUXB_UART0_RTS_N); printk("start CRTSCTS control and baudrate is %d\n",baud); umcon=rk2818_uart_read(port,UART_MCR); printk("UART_GET_MCR umcon=0x%x\n",umcon); -- 2.34.1