From 7e1bf305cfecbaee859405468b769650efe68f1a Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 29 Sep 2010 00:27:46 +0000 Subject: [PATCH] Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115008 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.td | 37 +++++++++++++-------- lib/Target/ARM/ARMInstrThumb.td | 8 ++--- lib/Target/ARM/ARMInstrThumb2.td | 55 +++++++++++++++++++------------- lib/Target/ARM/ARMSchedule.td | 5 +++ lib/Target/ARM/ARMScheduleA8.td | 7 ++++ lib/Target/ARM/ARMScheduleA9.td | 7 ++++ lib/Target/ARM/ARMScheduleV6.td | 7 ++++ 7 files changed, 87 insertions(+), 39 deletions(-) diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index b4221fb1889..7ebfa8e5f52 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -452,26 +452,27 @@ include "ARMInstrFormats.td" /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a /// binop that produces a value. -multiclass AsI1_bin_irs opcod, string opc, PatFrag opnode, - bit Commutable = 0> { +multiclass AsI1_bin_irs opcod, string opc, + InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, + PatFrag opnode, bit Commutable = 0> { // The register-immediate version is re-materializable. This is useful // in particular for taking the address of a local. let isReMaterializable = 1 in { def ri : AsI1 { let Inst{25} = 1; } } def rr : AsI1 { let Inst{11-4} = 0b00000000; let Inst{25} = 0; let isCommutable = Commutable; } def rs : AsI1 { let Inst{25} = 0; } @@ -480,16 +481,17 @@ multiclass AsI1_bin_irs opcod, string opc, PatFrag opnode, /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the /// instruction modifies the CPSR register. let Defs = [CPSR] in { -multiclass AI1_bin_s_irs opcod, string opc, PatFrag opnode, - bit Commutable = 0> { +multiclass AI1_bin_s_irs opcod, string opc, + InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, + PatFrag opnode, bit Commutable = 0> { def ri : AI1 { let Inst{20} = 1; let Inst{25} = 1; } def rr : AI1 { let isCommutable = Commutable; let Inst{11-4} = 0b00000000; @@ -497,7 +499,7 @@ multiclass AI1_bin_s_irs opcod, string opc, PatFrag opnode, let Inst{25} = 0; } def rs : AI1 { let Inst{20} = 1; let Inst{25} = 0; @@ -1599,7 +1601,7 @@ defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; def SBFX : I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), - AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi, + AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iBITi, "sbfx", "\t$dst, $src, $lsb, $width", "", []>, Requires<[IsARM, HasV6T2]> { let Inst{27-21} = 0b0111101; @@ -1608,7 +1610,7 @@ def SBFX : I<(outs GPR:$dst), def UBFX : I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), - AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi, + AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iBITi, "ubfx", "\t$dst, $src, $lsb, $width", "", []>, Requires<[IsARM, HasV6T2]> { let Inst{27-21} = 0b0111111; @@ -1620,14 +1622,18 @@ def UBFX : I<(outs GPR:$dst), // defm ADD : AsI1_bin_irs<0b0100, "add", + IIC_iALUi, IIC_iALUr, IIC_iALUsr, BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; defm SUB : AsI1_bin_irs<0b0010, "sub", + IIC_iALUi, IIC_iALUr, IIC_iALUsr, BinOpFrag<(sub node:$LHS, node:$RHS)>>; // ADD and SUB with 's' bit set. defm ADDS : AI1_bin_s_irs<0b0100, "adds", + IIC_iALUi, IIC_iALUr, IIC_iALUsr, BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; defm SUBS : AI1_bin_s_irs<0b0010, "subs", + IIC_iALUi, IIC_iALUr, IIC_iALUsr, BinOpFrag<(subc node:$LHS, node:$RHS)>>; defm ADC : AI1_adde_sube_irs<0b0101, "adc", @@ -1855,14 +1861,19 @@ def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>; // defm AND : AsI1_bin_irs<0b0000, "and", + IIC_iBITi, IIC_iBITr, IIC_iBITsr, BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; defm ANDS : AI1_bin_s_irs<0b0000, "and", + IIC_iBITi, IIC_iBITr, IIC_iBITsr, BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>; defm ORR : AsI1_bin_irs<0b1100, "orr", + IIC_iBITi, IIC_iBITr, IIC_iBITsr, BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; defm EOR : AsI1_bin_irs<0b0001, "eor", + IIC_iBITi, IIC_iBITr, IIC_iBITsr, BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; defm BIC : AsI1_bin_irs<0b1110, "bic", + IIC_iBITi, IIC_iBITr, IIC_iBITsr, BinOpFrag<(and node:$LHS, (not node:$RHS))>>; def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), @@ -2287,7 +2298,7 @@ def asr_amt : PatLeaf<(i32 imm), [{ // will match the pattern below. def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, shift_imm:$sh), - IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2$sh", + IIC_iBITsi, "pkhtb", "\t$dst, $src1, $src2$sh", [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), (and (sra GPR:$src2, asr_amt:$sh), 0xFFFF)))]>, diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 015054b3da2..7c829da8040 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -604,7 +604,7 @@ def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, // And register let isCommutable = 1 in -def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, +def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr, "and", "\t$dst, $rhs", [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>, T1DataProcessing<0b0000>; @@ -622,7 +622,7 @@ def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, T1DataProcessing<0b0100>; // BIC register -def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, +def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr, "bic", "\t$dst, $rhs", [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>, T1DataProcessing<0b1110>; @@ -675,7 +675,7 @@ def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr, // XOR register let isCommutable = 1 in -def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, +def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr, "eor", "\t$dst, $rhs", [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>, T1DataProcessing<0b0001>; @@ -751,7 +751,7 @@ def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr, // bitwise or register let isCommutable = 1 in -def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, +def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr, "orr", "\t$dst, $rhs", [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>, T1DataProcessing<0b1100>; diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index aa12a92d357..4fea0550bb5 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -213,10 +213,11 @@ multiclass T2I_un_irs opcod, string opc, PatFrag opnode, /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a /// binary operation that produces a value. These are predicable and can be /// changed to modify CPSR. -multiclass T2I_bin_irs opcod, string opc, PatFrag opnode, - bit Commutable = 0, string wide = ""> { +multiclass T2I_bin_irs opcod, string opc, + InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, + PatFrag opnode, bit Commutable = 0, string wide = ""> { // shifted imm - def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, + def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), iii, opc, "\t$dst, $lhs, $rhs", [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> { let Inst{31-27} = 0b11110; @@ -226,7 +227,7 @@ multiclass T2I_bin_irs opcod, string opc, PatFrag opnode, let Inst{15} = 0; } // register - def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr, + def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), iir, opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> { let isCommutable = Commutable; @@ -239,7 +240,7 @@ multiclass T2I_bin_irs opcod, string opc, PatFrag opnode, let Inst{5-4} = 0b00; // type } // shifted register - def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, + def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), iis, opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> { let Inst{31-27} = 0b11101; @@ -251,9 +252,10 @@ multiclass T2I_bin_irs opcod, string opc, PatFrag opnode, /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need // the ".w" prefix to indicate that they are wide. -multiclass T2I_bin_w_irs opcod, string opc, PatFrag opnode, - bit Commutable = 0> : - T2I_bin_irs; +multiclass T2I_bin_w_irs opcod, string opc, + InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, + PatFrag opnode, bit Commutable = 0> : + T2I_bin_irs; /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are /// reversed. The 'rr' form is only defined for the disassembler; for codegen @@ -295,10 +297,11 @@ multiclass T2I_rbin_irs opcod, string opc, PatFrag opnode> { /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the /// instruction modifies the CPSR register. let Defs = [CPSR] in { -multiclass T2I_bin_s_irs opcod, string opc, PatFrag opnode, - bit Commutable = 0> { +multiclass T2I_bin_s_irs opcod, string opc, + InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, + PatFrag opnode, bit Commutable = 0> { // shifted imm - def ri : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, + def ri : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), iii, !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> { let Inst{31-27} = 0b11110; @@ -308,7 +311,7 @@ multiclass T2I_bin_s_irs opcod, string opc, PatFrag opnode, let Inst{15} = 0; } // register - def rr : T2I<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr, + def rr : T2I<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), iir, !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> { let isCommutable = Commutable; @@ -321,7 +324,7 @@ multiclass T2I_bin_s_irs opcod, string opc, PatFrag opnode, let Inst{5-4} = 0b00; // type } // shifted register - def rs : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, + def rs : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), iis, !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> { let Inst{31-27} = 0b11101; @@ -761,7 +764,7 @@ multiclass T2I_bin_rrot opcod, string opc, PatFrag opnode> { // DO variant - disassembly only, no pattern multiclass T2I_bin_rrot_DO opcod, string opc> { - def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iALUr, + def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iEXTAr, opc, "\t$dst, $LHS, $RHS", []> { let Inst{31-27} = 0b11111; let Inst{26-23} = 0b0100; @@ -771,7 +774,7 @@ multiclass T2I_bin_rrot_DO opcod, string opc> { let Inst{5-4} = 0b00; // rotate } def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot), - IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> { + IIC_iEXTAsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> { let Inst{31-27} = 0b11111; let Inst{26-23} = 0b0100; let Inst{22-20} = opcod; @@ -1387,8 +1390,10 @@ defm t2SUB : T2I_bin_ii12rs<0b101, "sub", // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. defm t2ADDS : T2I_bin_s_irs <0b1000, "add", + IIC_iALUi, IIC_iALUr, IIC_iALUsi, BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; defm t2SUBS : T2I_bin_s_irs <0b1101, "sub", + IIC_iALUi, IIC_iALUr, IIC_iALUsi, BinOpFrag<(subc node:$LHS, node:$RHS)>>; defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", @@ -1626,16 +1631,21 @@ def t2MOVsra_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi, // defm t2AND : T2I_bin_w_irs<0b0000, "and", + IIC_iBITi, IIC_iBITr, IIC_iBITsi, BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; defm t2ORR : T2I_bin_w_irs<0b0010, "orr", + IIC_iBITi, IIC_iBITr, IIC_iBITsi, BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; defm t2EOR : T2I_bin_w_irs<0b0100, "eor", + IIC_iBITi, IIC_iBITr, IIC_iBITsi, BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; defm t2BIC : T2I_bin_w_irs<0b0001, "bic", + IIC_iBITi, IIC_iBITr, IIC_iBITsi, BinOpFrag<(and node:$LHS, (not node:$RHS))>>; defm t2ANDS : T2I_bin_s_irs<0b0000, "and", + IIC_iBITi, IIC_iBITr, IIC_iBITsi, BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>; let Constraints = "$src = $dst" in @@ -1650,7 +1660,7 @@ def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm), } def t2SBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width), - IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> { + IIC_iBITi, "sbfx", "\t$dst, $src, $lsb, $width", []> { let Inst{31-27} = 0b11110; let Inst{25} = 1; let Inst{24-20} = 0b10100; @@ -1658,7 +1668,7 @@ def t2SBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width), } def t2UBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width), - IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> { + IIC_iBITi, "ubfx", "\t$dst, $src, $lsb, $width", []> { let Inst{31-27} = 0b11110; let Inst{25} = 1; let Inst{24-20} = 0b11100; @@ -1669,7 +1679,7 @@ def t2UBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width), let Constraints = "$src = $dst" in def t2BFI : T2I<(outs rGPR:$dst), (ins rGPR:$src, rGPR:$val, bf_inv_mask_imm:$imm), - IIC_iALUi, "bfi", "\t$dst, $val, $imm", + IIC_iBITi, "bfi", "\t$dst, $val, $imm", [(set rGPR:$dst, (ARMbfi rGPR:$src, rGPR:$val, bf_inv_mask_imm:$imm))]> { let Inst{31-27} = 0b11110; @@ -1678,8 +1688,9 @@ def t2BFI : T2I<(outs rGPR:$dst), let Inst{15} = 0; } -defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS, - (not node:$RHS))>, 0, "">; +defm t2ORN : T2I_bin_irs<0b0011, "orn", + IIC_iBITi, IIC_iBITr, IIC_iBITsi, + BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">; // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version let AddedComplexity = 1 in @@ -2095,7 +2106,7 @@ def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr, (shl rGPR:$src, (i32 8))), i16))]>; def t2PKHBT : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh), - IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2$sh", + IIC_iBITsi, "pkhbt", "\t$dst, $src1, $src2$sh", [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF), (and (shl rGPR:$src2, lsl_amt:$sh), 0xFFFF0000)))]>, @@ -2118,7 +2129,7 @@ def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)), // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and // will match the pattern below. def t2PKHTB : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh), - IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2$sh", + IIC_iBITsi, "pkhtb", "\t$dst, $src1, $src2$sh", [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF0000), (and (sra rGPR:$src2, asr_amt:$sh), 0xFFFF)))]>, diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td index 96c9fa0d0b9..e385ec7f6a2 100644 --- a/lib/Target/ARM/ARMSchedule.td +++ b/lib/Target/ARM/ARMSchedule.td @@ -15,10 +15,15 @@ def IIC_iALUi : InstrItinClass; def IIC_iALUr : InstrItinClass; def IIC_iALUsi : InstrItinClass; def IIC_iALUsr : InstrItinClass; +def IIC_iBITi : InstrItinClass; +def IIC_iBITr : InstrItinClass; +def IIC_iBITsi : InstrItinClass; +def IIC_iBITsr : InstrItinClass; def IIC_iUNAr : InstrItinClass; def IIC_iUNAsi : InstrItinClass; def IIC_iEXTr : InstrItinClass; def IIC_iEXTAr : InstrItinClass; +def IIC_iEXTAsr : InstrItinClass; def IIC_iCMPi : InstrItinClass; def IIC_iCMPr : InstrItinClass; def IIC_iCMPsi : InstrItinClass; diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td index 6bec63734d0..6b9b964e424 100644 --- a/lib/Target/ARM/ARMScheduleA8.td +++ b/lib/Target/ARM/ARMScheduleA8.td @@ -38,6 +38,12 @@ def CortexA8Itineraries : ProcessorItineraries< InstrItinData], [2, 2, 1]>, InstrItinData], [2, 2, 1, 1]>, // + // Bitwise Instructions that produce a result + InstrItinData], [2, 2]>, + InstrItinData], [2, 2, 2]>, + InstrItinData], [2, 2, 1]>, + InstrItinData], [2, 2, 1, 1]>, + // // Unary Instructions that produce a result InstrItinData], [2, 2]>, InstrItinData], [2, 1]>, @@ -45,6 +51,7 @@ def CortexA8Itineraries : ProcessorItineraries< // Zero and sign extension instructions InstrItinData], [1, 1]>, InstrItinData], [2, 2, 1]>, + InstrItinData],[2, 2, 1, 1]>, // // Compare instructions InstrItinData], [2]>, diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 1deb846f2d1..056aa599dd6 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -47,6 +47,12 @@ def CortexA9Itineraries : ProcessorItineraries< InstrItinData], [2, 2, 1]>, InstrItinData], [2, 2, 1, 1]>, // + // Bitwise Instructions that produce a result + InstrItinData], [2, 2]>, + InstrItinData], [2, 2, 2]>, + InstrItinData], [2, 2, 1]>, + InstrItinData], [2, 2, 1, 1]>, + // // Unary Instructions that produce a result InstrItinData], [2, 2]>, InstrItinData], [2, 1]>, @@ -54,6 +60,7 @@ def CortexA9Itineraries : ProcessorItineraries< // Zero and sign extension instructions InstrItinData], [2, 1]>, InstrItinData], [3, 1, 1]>, + InstrItinData],[3, 1, 1, 1]>, // // Compare instructions InstrItinData], [2]>, diff --git a/lib/Target/ARM/ARMScheduleV6.td b/lib/Target/ARM/ARMScheduleV6.td index 2e8a6a34055..51b915f4fdb 100644 --- a/lib/Target/ARM/ARMScheduleV6.td +++ b/lib/Target/ARM/ARMScheduleV6.td @@ -30,6 +30,12 @@ def ARMV6Itineraries : ProcessorItineraries< InstrItinData], [2, 2, 1]>, InstrItinData], [3, 3, 2, 1]>, // + // Bitwise Instructions that produce a result + InstrItinData], [2, 2]>, + InstrItinData], [2, 2, 2]>, + InstrItinData], [2, 2, 1]>, + InstrItinData], [3, 3, 2, 1]>, + // // Unary Instructions that produce a result InstrItinData], [2, 2]>, InstrItinData], [2, 1]>, @@ -37,6 +43,7 @@ def ARMV6Itineraries : ProcessorItineraries< // Zero and sign extension instructions InstrItinData], [1, 1]>, InstrItinData], [2, 2, 1]>, + InstrItinData], [3, 3, 2, 1]>, // // Compare instructions InstrItinData], [2]>, -- 2.34.1