From 7ea64f5d12ff475235838466bc2ae11c8964e56f Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Wed, 12 Jan 2005 01:28:00 +0000
Subject: [PATCH] Fold some more [mem] op= val  operators.  This allows us to
 things like this several times in 256.bzip2:

        mov %EAX, DWORD PTR [%ESP + 204]
-       mov %EAX, DWORD PTR [%EAX]
-       or %EAX, 2097152
-       mov %ECX, DWORD PTR [%ESP + 204]
-       mov DWORD PTR [%ECX], %EAX
+       or DWORD PTR [%EAX], 2097152


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19492 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86ISelPattern.cpp | 41 +++++++++++++++++++++++++++++--
 1 file changed, 39 insertions(+), 2 deletions(-)

diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index 358a0380dd9..f5f6c105617 100644
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -2129,11 +2129,46 @@ void ISel::Select(SDOperand N) {
             X86::ADD8mi, X86::ADD16mi, X86::ADD32mi,
             X86::ADD8mr, X86::ADD16mr, X86::ADD32mr, 0, 0,
           };
+          static const unsigned SUBTAB[] = {
+            X86::SUB8mi, X86::SUB16mi, X86::SUB32mi,
+            X86::SUB8mr, X86::SUB16mr, X86::SUB32mr, 0, 0,
+          };
+          static const unsigned ANDTAB[] = {
+            X86::AND8mi, X86::AND16mi, X86::AND32mi,
+            X86::AND8mr, X86::AND16mr, X86::AND32mr, 0, 0,
+          };
+          static const unsigned ORTAB[] = {
+            X86::OR8mi, X86::OR16mi, X86::OR32mi,
+            X86::OR8mr, X86::OR16mr, X86::OR32mr, 0, 0,
+          };
+          static const unsigned XORTAB[] = {
+            X86::XOR8mi, X86::XOR16mi, X86::XOR32mi,
+            X86::XOR8mr, X86::XOR16mr, X86::XOR32mr, 0, 0,
+          };
+          static const unsigned SHLTAB[] = {
+            X86::SHL8mi, X86::SHL16mi, X86::SHL32mi,
+            /*Have to put the reg in CL*/0, 0, 0, 0, 0,
+          };
+          static const unsigned SARTAB[] = {
+            X86::SAR8mi, X86::SAR16mi, X86::SAR32mi,
+            /*Have to put the reg in CL*/0, 0, 0, 0, 0,
+          };
+          static const unsigned SHRTAB[] = {
+            X86::SHR8mi, X86::SHR16mi, X86::SHR32mi,
+            /*Have to put the reg in CL*/0, 0, 0, 0, 0,
+          };
 
           const unsigned *TabPtr = 0;
           switch (Op.getOpcode()) {
-          default: break;
+          default: std::cerr << "CANNOT [mem] op= val: "; Op.Val->dump(); std::cerr << "\n"; break;
           case ISD::ADD: TabPtr = ADDTAB; break;
+          case ISD::SUB: TabPtr = SUBTAB; break;
+          case ISD::AND: TabPtr = ANDTAB; break;
+          case ISD:: OR: TabPtr =  ORTAB; break;
+          case ISD::XOR: TabPtr = XORTAB; break;
+          case ISD::SHL: TabPtr = SHLTAB; break;
+          case ISD::SRA: TabPtr = SARTAB; break;
+          case ISD::SRL: TabPtr = SHRTAB; break;
           }
           
           if (TabPtr) {
@@ -2166,7 +2201,9 @@ void ISel::Select(SDOperand N) {
             
             // If we have [mem] = V op [mem], try to turn it into:
             // [mem] = [mem] op V.
-            if (Op1 == TheLoad && 1 /*iscommutative*/)
+            if (Op1 == TheLoad && Op.getOpcode() != ISD::SUB &&
+                Op.getOpcode() != ISD::SHL && Op.getOpcode() != ISD::SRA &&
+                Op.getOpcode() != ISD::SRL)
               std::swap(Op0, Op1);
 
             if (Op0 == TheLoad) {
-- 
2.34.1