From 817c1a6dddadb4664738777d224bc7eae6e62cf3 Mon Sep 17 00:00:00 2001
From: Jim Grosbach <grosbach@apple.com>
Date: Fri, 19 Nov 2010 00:27:09 +0000
Subject: [PATCH] Minor cleanups to a few llvm_unreachable() calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119767 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMCodeEmitter.cpp   | 8 ++------
 lib/Target/ARM/ARMInstrInfo.td      | 5 +++--
 lib/Target/ARM/ARMMCCodeEmitter.cpp | 9 +++------
 3 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 8888420d2af..ef0ef80c898 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -378,12 +378,8 @@ unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
     emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
   else if (MO.isMBB())
     emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
-  else {
-#ifndef NDEBUG
-    errs() << MO;
-#endif
-    llvm_unreachable(0);
-  }
+  else
+    llvm_unreachable("Unable to encode MachineOperand!");
   return 0;
 }
 
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index fc542ea0601..98fc7fd303f 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1274,12 +1274,13 @@ let isCall = 1,
                 [(ARMcall GPR:$func)]>,
             Requires<[IsARM, HasV5T, IsNotDarwin]> {
     bits<4> func;
-    let Inst{27-4} = 0b000100101111111111110011;
+    let Inst{31-4} = 0b1110000100101111111111110011;
     let Inst{3-0}   = func;
   }
 
   // ARMv4T
   // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
+  // FIXME: x2 insn patterns like this need to be pseudo instructions.
   def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
                   IIC_Br, "mov\tlr, pc\n\tbx\t$func",
                   [(ARMcall_nolink tGPR:$func)]>,
@@ -1327,7 +1328,7 @@ let isCall = 1,
                 IIC_Br, "blx\t$func",
                 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
     bits<4> func;
-    let Inst{27-4} = 0b000100101111111111110011;
+    let Inst{31-4} = 0b1110000100101111111111110011;
     let Inst{3-0}   = func;
   }
 
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index 8cf31e70cb4..5ad117ec04e 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -316,10 +316,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
   }
 
-#ifndef NDEBUG
-  errs() << MO;
-#endif
-  llvm_unreachable(0);
+  llvm_unreachable("Unable to encode MCOperand!");
   return 0;
 }
 
@@ -421,8 +418,8 @@ getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
     }
     Fixups.push_back(MCFixup::Create(0, Expr, Kind));
     return 0;
-  }
-  llvm_unreachable("Unsupported MCExpr type in MCOperand");
+  };
+  llvm_unreachable("Unsupported MCExpr type in MCOperand!");
   return 0;
 }
 
-- 
2.34.1