From 82e57373cbd73fab5c2034a1bebc602ab958e04c Mon Sep 17 00:00:00 2001
From: wdc <wdc@rock-chips.com>
Date: Fri, 7 Mar 2014 09:32:27 +0800
Subject: [PATCH] 3288: update i2c dts

---
 arch/arm/boot/dts/rk3288.dtsi | 67 +++++++++++++++++------------------
 1 file changed, 33 insertions(+), 34 deletions(-)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 337410bb580d..276c8c75c77b 100755
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -13,6 +13,7 @@
 		i2c2 = &i2c2;
 		i2c3 = &i2c3;
 		i2c4 = &i2c4;
+		i2c5 = &i2c5;
 	};
 
 	cpus {
@@ -120,10 +121,8 @@
 		//pinctrl-1 = <&i2c1_gpio>;
 		//gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 		//clocks = <&clk_gates8 5>;
-	   rockchip,check-idle = <1>;	
-      status = "disabled";
-
-
+        rockchip,check-idle = <1>;
+        status = "disabled";
 	};
 
 	i2c2: i2c@ff660000 {
@@ -148,10 +147,10 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		//pinctrl-names = "default", "gpio";
-		//pinctrl-0 = <&i2c2_sda &i2c2_scl>;
-		//pinctrl-1 = <&i2c2_gpio>;
+		//pinctrl-0 = <&i2c3_sda &i2c3_scl>;
+		//pinctrl-1 = <&i2c3_gpio>;
 		//gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
-		//clocks = <&clk_gates8 6>;
+		//clocks = <&clk_gates8 7>;
 		rockchip,check-idle = <1>;
 		status = "disabled";
 	};
@@ -163,28 +162,28 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		//pinctrl-names = "default", "gpio";
-		//pinctrl-0 = <&i2c3_sda &i2c3_scl>;
-		//pinctrl-1 = <&i2c3_gpio>;
+		//pinctrl-0 = <&i2c4_sda &i2c4_scl>;
+		//pinctrl-1 = <&i2c4_gpio>;
 		//gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
-		//clocks = <&clk_gates8 7>;
+		//clocks = <&clk_gates8 8>;
 		rockchip,check-idle = <1>;
 		status = "disabled";
 	};
 	
 
-   i2c5: i2c@ff170000 {
-       compatible = "rockchip,rk30-i2c";
-       reg = <0xff170000 0x1000>;
-       interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-       #address-cells = <1>;
-       #size-cells = <0>;
-		//pinctrl-names = "default", "gpio";
-		//pinctrl-0 = <&i2c4_sda &i2c4_scl>;
-		//pinctrl-1 = <&i2c4_gpio>;
-		//gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
-		//clocks = <&clk_gates8 8>;
-       rockchip,check-idle = <1>;
-       status = "disabled";
+    i2c5: i2c@ff170000 {
+        compatible = "rockchip,rk30-i2c";
+        reg = <0xff170000 0x1000>;
+        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        //pinctrl-names = "default", "gpio";
+        //pinctrl-0 = <&i2c5_sda &i2c5_scl>;
+        //pinctrl-1 = <&i2c5_gpio>;
+        //gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
+        //clocks = <&clk_gates8 8>;
+        rockchip,check-idle = <1>;
+        status = "disabled";
     };
 
 	edp: edp@ff970000 {
@@ -205,17 +204,17 @@
 		status = "disabled";
          };
 
-    adc: adc@ff100000 {
-        compatible = "rockchip,saradc";
-        reg = <0xff100000 0x100>;
-        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-        #io-channel-cells = <1>;
-        io-channel-ranges;
-        rockchip,adc-vref = <1800>;
-        clock-frequency = <1000000>;
-        clock-names = "saradc", "pclk_saradc"; 
-        status = "disabled";
-    };
+        adc: adc@ff100000 {
+                compatible = "rockchip,saradc";
+                reg = <0xff100000 0x100>;
+                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                #io-channel-cells = <1>;
+                io-channel-ranges;
+                rockchip,adc-vref = <1800>;
+                clock-frequency = <1000000>;
+                clock-names = "saradc", "pclk_saradc";
+                status = "disabled";
+         };
 	
 	rga@ff920000 {
 		compatible = "rockchip,rga";
-- 
2.34.1