From 84a568df720c4a7bcd068becf0175b4d5848c92b Mon Sep 17 00:00:00 2001
From: =?utf8?q?=E9=82=B1=E5=BB=BA=E6=96=8C?= <qjb@rock-chips.com>
Date: Fri, 4 Mar 2011 14:31:56 +0800
Subject: [PATCH] =?utf8?q?=E6=B7=BB=E5=8A=A0wm8994=E9=A9=B1=E5=8A=A8?=
=?utf8?q?=E6=94=AF=E6=8C=81?=
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit
---
arch/arm/configs/rk29_phonesdk_defconfig | 36 +-
arch/arm/mach-rk29/board-rk29-phonesdk.c | 7 +
drivers/gpio/Kconfig | 7 +
drivers/gpio/Makefile | 2 +
drivers/gpio/wm8994-gpio.c | 205 +
drivers/mfd/Kconfig | 12 +
drivers/mfd/Makefile | 3 +
drivers/mfd/wm8994-core.c | 538 ++
drivers/regulator/Kconfig | 8 +
drivers/regulator/Makefile | 2 +
drivers/regulator/wm8994-regulator.c | 308 ++
include/linux/mfd/wm8994/core.h | 54 +
include/linux/mfd/wm8994/gpio.h | 72 +
include/linux/mfd/wm8994/pdata.h | 97 +
include/linux/mfd/wm8994/registers.h | 4292 +++++++++++++++
include/sound/soc-dapm.h | 10 +
sound/soc/codecs/Kconfig | 4 +-
sound/soc/codecs/wm8994.c | 6388 +++++++++++++---------
sound/soc/codecs/wm8994.h | 71 +-
sound/soc/codecs/wm_hubs.c | 228 +-
sound/soc/codecs/wm_hubs.h | 12 +
sound/soc/rk29/Kconfig | 9 +
sound/soc/rk29/rk29_pcm.c | 4 +-
sound/soc/rk29/rk29_wm8994.c | 207 +
sound/soc/soc-dapm.c | 88 +
25 files changed, 9882 insertions(+), 2782 deletions(-)
mode change 100755 => 100644 arch/arm/configs/rk29_phonesdk_defconfig
create mode 100644 drivers/gpio/wm8994-gpio.c
create mode 100755 drivers/mfd/wm8994-core.c
create mode 100644 drivers/regulator/wm8994-regulator.c
create mode 100644 include/linux/mfd/wm8994/core.h
create mode 100644 include/linux/mfd/wm8994/gpio.h
create mode 100644 include/linux/mfd/wm8994/pdata.h
create mode 100644 include/linux/mfd/wm8994/registers.h
mode change 100644 => 100755 sound/soc/codecs/wm_hubs.c
mode change 100644 => 100755 sound/soc/codecs/wm_hubs.h
create mode 100755 sound/soc/rk29/rk29_wm8994.c
diff --git a/arch/arm/configs/rk29_phonesdk_defconfig b/arch/arm/configs/rk29_phonesdk_defconfig
old mode 100755
new mode 100644
index 7e119811ff7c..60abf165f3a4
--- a/arch/arm/configs/rk29_phonesdk_defconfig
+++ b/arch/arm/configs/rk29_phonesdk_defconfig
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32.27
-# Wed Jan 26 18:10:12 2011
+# Fri Mar 4 11:17:59 2011
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -198,6 +198,7 @@ CONFIG_ARCH_RK29=y
CONFIG_WIFI_CONTROL_FUNC=y
# CONFIG_MACH_RK29SDK is not set
# CONFIG_MACH_RK29WINACCORD is not set
+# CONFIG_MACH_RK29FIH is not set
# CONFIG_MACH_RK29_AIGO is not set
# CONFIG_MACH_RK29_MALATA is not set
CONFIG_MACH_RK29_PHONESDK=y
@@ -607,6 +608,14 @@ CONFIG_APANIC_PLABEL="kpanic"
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_RK29_SUPPORT_MODEM is not set
+# CONFIG_RK29_GPS is not set
+
+#
+# Motion Sensors Support
+#
+# CONFIG_MPU_NONE is not set
+# CONFIG_SENSORS_MPU3050 is not set
+# CONFIG_SENSORS_MPU6000 is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
@@ -766,6 +775,7 @@ CONFIG_KEYS_RK29=y
# CONFIG_QT2160 is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_WM831X_GPIO is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_NEWTON is not set
@@ -803,6 +813,7 @@ CONFIG_TOUCHSCREEN_XPT2046_SPI_NOCHOOSE=y
# CONFIG_TOUCHSCREEN_TSC2007 is not set
# CONFIG_TOUCHSCREEN_W90X900 is not set
# CONFIG_HANNSTAR_P1003 is not set
+# CONFIG_ATMEL_MXT224 is not set
# CONFIG_SINTEK_3FA16 is not set
CONFIG_EETI_EGALAX=y
CONFIG_EETI_EGALAX_MAX_X=1087
@@ -812,6 +823,8 @@ CONFIG_EETI_EGALAX_MAX_Y=800
CONFIG_INPUT_MISC=y
CONFIG_INPUT_LPSENSOR_ISL29028=y
# CONFIG_INPUT_LPSENSOR_CM3602 is not set
+# CONFIG_INPUT_LSENSOR_CM3623 is not set
+# CONFIG_INPUT_MPU3050 is not set
# CONFIG_INPUT_ATI_REMOTE is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYCHORD is not set
@@ -825,6 +838,7 @@ CONFIG_INPUT_LPSENSOR_ISL29028=y
CONFIG_G_SENSOR_DEVICE=y
# CONFIG_GS_MMA7660 is not set
CONFIG_GS_MMA8452=y
+CONFIG_GS_FIH=y
# CONFIG_INPUT_JOGBALL is not set
#
@@ -928,6 +942,7 @@ CONFIG_GPIOLIB=y
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_WM8994 is not set
#
# PCI GPIO expanders:
@@ -973,20 +988,22 @@ CONFIG_SSB_POSSIBLE=y
#
# Multifunction device drivers
#
-# CONFIG_MFD_CORE is not set
+CONFIG_MFD_CORE=y
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_TPS65010 is not set
# CONFIG_TWL4030_CORE is not set
+# CONFIG_TPS65910_CORE is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_PMIC_DA903X is not set
+CONFIG_MFD_WM8994=y
# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_AB3100_CORE is not set
@@ -997,6 +1014,7 @@ CONFIG_REGULATOR=y
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_BQ24022 is not set
# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_WM8994 is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
@@ -1049,6 +1067,7 @@ CONFIG_SOC_CAMERA=y
# CONFIG_SOC_CAMERA_MT9M111 is not set
# CONFIG_SOC_CAMERA_MT9T031 is not set
# CONFIG_SOC_CAMERA_MT9P111 is not set
+# CONFIG_SOC_CAMERA_MT9D112 is not set
# CONFIG_SOC_CAMERA_MT9V022 is not set
# CONFIG_SOC_CAMERA_TW9910 is not set
# CONFIG_SOC_CAMERA_PLATFORM is not set
@@ -1162,6 +1181,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y
# Frame buffer hardware drivers
#
# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_TMIO is not set
# CONFIG_FB_RK2818 is not set
CONFIG_FB_RK29=y
# CONFIG_FB_VIRTUAL is not set
@@ -1258,12 +1278,14 @@ CONFIG_SND_RK29_SOC_I2S=y
# CONFIG_SND_RK29_SOC_I2S_2CH is not set
CONFIG_SND_RK29_SOC_I2S_8CH=y
# CONFIG_SND_RK29_SOC_WM8988 is not set
-CONFIG_SND_RK29_SOC_WM8900=y
-# CONFIG_SND_RK29_CODEC_SOC_MASTER is not set
-CONFIG_SND_RK29_CODEC_SOC_SLAVE=y
+# CONFIG_SND_RK29_SOC_WM8900 is not set
+CONFIG_SND_RK29_SOC_WM8994=y
+CONFIG_SND_RK29_CODEC_SOC_MASTER=y
+# CONFIG_SND_RK29_CODEC_SOC_SLAVE is not set
CONFIG_SND_SOC_I2C_AND_SPI=y
# CONFIG_SND_SOC_ALL_CODECS is not set
-CONFIG_SND_SOC_WM8900=y
+CONFIG_SND_SOC_WM_HUBS=y
+CONFIG_SND_SOC_WM8994=y
# CONFIG_SOUND_PRIME is not set
# CONFIG_HID_SUPPORT is not set
CONFIG_USB_SUPPORT=y
diff --git a/arch/arm/mach-rk29/board-rk29-phonesdk.c b/arch/arm/mach-rk29/board-rk29-phonesdk.c
index f83130c8f5c4..92b32224ac89 100755
--- a/arch/arm/mach-rk29/board-rk29-phonesdk.c
+++ b/arch/arm/mach-rk29/board-rk29-phonesdk.c
@@ -1295,6 +1295,13 @@ static struct i2c_board_info __initdata board_i2c0_devices[] = {
.flags = 0,
},
#endif
+#if defined (CONFIG_SND_SOC_WM8994)
+ {
+ .type = "wm8994",
+ .addr = 0x1A,
+ .flags = 0,
+ },
+#endif
#if defined (CONFIG_BATTERY_STC3100)
{
.type = "stc3100",
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index f6f188669374..196c7a0bea93 100755
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -161,6 +161,13 @@ config GPIO_TPS65910
help
Say yes here to access the GPIO signal of TPS65910x multi-function
power management chips from Texas Instruments.
+#add by qjb
+config GPIO_WM8994
+ tristate "WM8994 GPIOs"
+ depends on MFD_WM8994
+ help
+ Say yes here to access the GPIO signals of WM8994 audio hub
+ CODECs from Wolfson Microelectronics.
config GPIO_WM831X
tristate "WM831x GPIOs"
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index e0b37e098e76..48f149c93604 100755
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -23,3 +23,5 @@ obj-$(CONFIG_GPIO_WM831X) += wm831x-gpio.o
obj-$(CONFIG_GPIO_PCA9554) += pca9554.o
obj-$(CONFIG_IOEXTEND_TCA6424) += tca6424.o
obj-$(CONFIG_EXPAND_GPIO_SOFT_INTERRUPT) += expand_gpio_soft_interrupt.o
+#add by qjb
+obj-$(CONFIG_GPIO_WM8994) += wm8994-gpio.o
\ No newline at end of file
diff --git a/drivers/gpio/wm8994-gpio.c b/drivers/gpio/wm8994-gpio.c
new file mode 100644
index 000000000000..7607cc61e1dd
--- /dev/null
+++ b/drivers/gpio/wm8994-gpio.c
@@ -0,0 +1,205 @@
+/*
+ * wm8994-gpio.c -- gpiolib support for Wolfson WM8994
+ *
+ * Copyright 2009 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/mfd/core.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+
+#include <linux/mfd/wm8994/core.h>
+#include <linux/mfd/wm8994/pdata.h>
+#include <linux/mfd/wm8994/gpio.h>
+#include <linux/mfd/wm8994/registers.h>
+
+struct wm8994_gpio {
+ struct wm8994 *wm8994;
+ struct gpio_chip gpio_chip;
+};
+
+static inline struct wm8994_gpio *to_wm8994_gpio(struct gpio_chip *chip)
+{
+ return container_of(chip, struct wm8994_gpio, gpio_chip);
+}
+
+static int wm8994_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
+{
+ struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip);
+ struct wm8994 *wm8994 = wm8994_gpio->wm8994;
+
+ return wm8994_set_bits(wm8994, WM8994_GPIO_1 + offset,
+ WM8994_GPN_DIR, WM8994_GPN_DIR);
+}
+
+static int wm8994_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip);
+ struct wm8994 *wm8994 = wm8994_gpio->wm8994;
+ int ret;
+
+ ret = wm8994_reg_read(wm8994, WM8994_GPIO_1 + offset);
+ if (ret < 0)
+ return ret;
+
+ if (ret & WM8994_GPN_LVL)
+ return 1;
+ else
+ return 0;
+}
+
+static int wm8994_gpio_direction_out(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip);
+ struct wm8994 *wm8994 = wm8994_gpio->wm8994;
+
+ return wm8994_set_bits(wm8994, WM8994_GPIO_1 + offset,
+ WM8994_GPN_DIR, 0);
+}
+
+static void wm8994_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip);
+ struct wm8994 *wm8994 = wm8994_gpio->wm8994;
+
+ if (value)
+ value = WM8994_GPN_LVL;
+
+ wm8994_set_bits(wm8994, WM8994_GPIO_1 + offset, WM8994_GPN_LVL, value);
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void wm8994_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+ struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip);
+ struct wm8994 *wm8994 = wm8994_gpio->wm8994;
+ int i;
+
+ for (i = 0; i < chip->ngpio; i++) {
+ int gpio = i + chip->base;
+ int reg;
+ const char *label;
+
+ /* We report the GPIO even if it's not requested since
+ * we're also reporting things like alternate
+ * functions which apply even when the GPIO is not in
+ * use as a GPIO.
+ */
+ label = gpiochip_is_requested(chip, i);
+ if (!label)
+ label = "Unrequested";
+
+ seq_printf(s, " gpio-%-3d (%-20.20s) ", gpio, label);
+
+ reg = wm8994_reg_read(wm8994, WM8994_GPIO_1 + i);
+ if (reg < 0) {
+ dev_err(wm8994->dev,
+ "GPIO control %d read failed: %d\n",
+ gpio, reg);
+ seq_printf(s, "\n");
+ continue;
+ }
+
+ /* No decode yet; note that GPIO2 is special */
+ seq_printf(s, "(%x)\n", reg);
+ }
+}
+#else
+#define wm8994_gpio_dbg_show NULL
+#endif
+
+static struct gpio_chip template_chip = {
+ .label = "wm8994",
+ .owner = THIS_MODULE,
+ .direction_input = wm8994_gpio_direction_in,
+ .get = wm8994_gpio_get,
+ .direction_output = wm8994_gpio_direction_out,
+ .set = wm8994_gpio_set,
+ .dbg_show = wm8994_gpio_dbg_show,
+ .can_sleep = 1,
+};
+
+static int __devinit wm8994_gpio_probe(struct platform_device *pdev)
+{
+ struct wm8994 *wm8994 = dev_get_drvdata(pdev->dev.parent);
+ struct wm8994_pdata *pdata = wm8994->dev->platform_data;
+ struct wm8994_gpio *wm8994_gpio;
+ int ret;
+
+ wm8994_gpio = kzalloc(sizeof(*wm8994_gpio), GFP_KERNEL);
+ if (wm8994_gpio == NULL)
+ return -ENOMEM;
+
+ wm8994_gpio->wm8994 = wm8994;
+ wm8994_gpio->gpio_chip = template_chip;
+ wm8994_gpio->gpio_chip.ngpio = WM8994_GPIO_MAX;
+ wm8994_gpio->gpio_chip.dev = &pdev->dev;
+ if (pdata && pdata->gpio_base)
+ wm8994_gpio->gpio_chip.base = pdata->gpio_base;
+ else
+ wm8994_gpio->gpio_chip.base = -1;
+
+ ret = gpiochip_add(&wm8994_gpio->gpio_chip);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Could not register gpiochip, %d\n",
+ ret);
+ goto err;
+ }
+
+ platform_set_drvdata(pdev, wm8994_gpio);
+
+ return ret;
+
+err:
+ kfree(wm8994_gpio);
+ return ret;
+}
+
+static int __devexit wm8994_gpio_remove(struct platform_device *pdev)
+{
+ struct wm8994_gpio *wm8994_gpio = platform_get_drvdata(pdev);
+ int ret;
+
+ ret = gpiochip_remove(&wm8994_gpio->gpio_chip);
+ if (ret == 0)
+ kfree(wm8994_gpio);
+
+ return ret;
+}
+
+static struct platform_driver wm8994_gpio_driver = {
+ .driver.name = "wm8994-gpio",
+ .driver.owner = THIS_MODULE,
+ .probe = wm8994_gpio_probe,
+ .remove = __devexit_p(wm8994_gpio_remove),
+};
+
+static int __init wm8994_gpio_init(void)
+{
+ return platform_driver_register(&wm8994_gpio_driver);
+}
+subsys_initcall(wm8994_gpio_init);
+
+static void __exit wm8994_gpio_exit(void)
+{
+ platform_driver_unregister(&wm8994_gpio_driver);
+}
+module_exit(wm8994_gpio_exit);
+
+MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
+MODULE_DESCRIPTION("GPIO interface for WM8994");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:wm8994-gpio");
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index cc4cf1274a3e..8bc5dcc200b2 100755
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -171,6 +171,18 @@ config PMIC_DA903X
the I2C driver and the core APIs _only_, you have to select
individual components like LCD backlight, voltage regulators,
LEDs and battery-charger under the corresponding menus.
+##and by qjb
+config MFD_WM8994
+ tristate "Support Wolfson Microelectronics WM8994"
+ select MFD_CORE
+ depends on I2C
+ help
+ The WM8994 is a highly integrated hi-fi CODEC designed for
+ smartphone applicatiosn. As well as audio functionality it
+ has on board GPIO and regulator functionality which is
+ supported via the relevant subsystems. This driver provides
+ core support for the WM8994, in order to use the actual
+ functionaltiy of the device other drivers must be enabled.
config MFD_WM8400
tristate "Support Wolfson Microelectronics WM8400"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9b2463df22b7..d26a4631ec3c 100755
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -54,3 +54,6 @@ obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o
obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o
obj-$(CONFIG_AB3100_CORE) += ab3100-core.o
obj-$(CONFIG_AB3100_OTP) += ab3100-otp.o
+#add by qjb
+obj-$(CONFIG_MFD_WM8994) += wm8994-core.o
+
diff --git a/drivers/mfd/wm8994-core.c b/drivers/mfd/wm8994-core.c
new file mode 100755
index 000000000000..3d48497ccedf
--- /dev/null
+++ b/drivers/mfd/wm8994-core.c
@@ -0,0 +1,538 @@
+/*
+ * wm8994-core.c -- Device access for Wolfson WM8994
+ *
+ * Copyright 2009 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/mfd/core.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/machine.h>
+
+#include <linux/mfd/wm8994/core.h>
+#include <linux/mfd/wm8994/pdata.h>
+#include <linux/mfd/wm8994/registers.h>
+
+static int wm8994_read(struct wm8994 *wm8994, unsigned short reg,
+ int bytes, void *dest)
+{
+ int ret, i;
+ u16 *buf = dest;
+
+ BUG_ON(bytes % 2);
+ BUG_ON(bytes <= 0);
+
+ ret = wm8994->read_dev(wm8994, reg, bytes, dest);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < bytes / 2; i++) {
+ buf[i] = be16_to_cpu(buf[i]);
+
+ dev_vdbg(wm8994->dev, "Read %04x from R%d(0x%x)\n",
+ buf[i], reg + i, reg + i);
+ }
+
+ return 0;
+}
+
+/**
+ * wm8994_reg_read: Read a single WM8994 register.
+ *
+ * @wm8994: Device to read from.
+ * @reg: Register to read.
+ */
+int wm8994_reg_read(struct wm8994 *wm8994, unsigned short reg)
+{
+ unsigned short val;
+ int ret;
+
+ mutex_lock(&wm8994->io_lock);
+
+ ret = wm8994_read(wm8994, reg, 2, &val);
+
+ mutex_unlock(&wm8994->io_lock);
+
+ if (ret < 0)
+ return ret;
+ else
+ return val;
+}
+EXPORT_SYMBOL_GPL(wm8994_reg_read);
+
+/**
+ * wm8994_bulk_read: Read multiple WM8994 registers
+ *
+ * @wm8994: Device to read from
+ * @reg: First register
+ * @count: Number of registers
+ * @buf: Buffer to fill.
+ */
+int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg,
+ int count, u16 *buf)
+{
+ int ret;
+
+ mutex_lock(&wm8994->io_lock);
+
+ ret = wm8994_read(wm8994, reg, count * 2, buf);
+
+ mutex_unlock(&wm8994->io_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(wm8994_bulk_read);
+
+static int wm8994_write(struct wm8994 *wm8994, unsigned short reg,
+ int bytes, void *src)
+{
+ u16 *buf = src;
+ int i;
+
+ BUG_ON(bytes % 2);
+ BUG_ON(bytes <= 0);
+
+ for (i = 0; i < bytes / 2; i++) {
+ dev_vdbg(wm8994->dev, "Write %04x to R%d(0x%x)\n",
+ buf[i], reg + i, reg + i);
+
+ buf[i] = cpu_to_be16(buf[i]);
+ }
+
+ return wm8994->write_dev(wm8994, reg, bytes, src);
+}
+
+/**
+ * wm8994_reg_write: Write a single WM8994 register.
+ *
+ * @wm8994: Device to write to.
+ * @reg: Register to write to.
+ * @val: Value to write.
+ */
+int wm8994_reg_write(struct wm8994 *wm8994, unsigned short reg,
+ unsigned short val)
+{
+ int ret;
+
+ mutex_lock(&wm8994->io_lock);
+
+ ret = wm8994_write(wm8994, reg, 2, &val);
+
+ mutex_unlock(&wm8994->io_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(wm8994_reg_write);
+
+/**
+ * wm8994_set_bits: Set the value of a bitfield in a WM8994 register
+ *
+ * @wm8994: Device to write to.
+ * @reg: Register to write to.
+ * @mask: Mask of bits to set.
+ * @val: Value to set (unshifted)
+ */
+int wm8994_set_bits(struct wm8994 *wm8994, unsigned short reg,
+ unsigned short mask, unsigned short val)
+{
+ int ret;
+ u16 r;
+
+ mutex_lock(&wm8994->io_lock);
+
+ ret = wm8994_read(wm8994, reg, 2, &r);
+ if (ret < 0)
+ goto out;
+
+ r &= ~mask;
+ r |= val;
+
+ ret = wm8994_write(wm8994, reg, 2, &r);
+
+out:
+ mutex_unlock(&wm8994->io_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(wm8994_set_bits);
+
+static struct mfd_cell wm8994_regulator_devs[] = {
+ { .name = "wm8994-ldo", .id = 1 },
+ { .name = "wm8994-ldo", .id = 2 },
+};
+
+static struct mfd_cell wm8994_devs[] = {
+ { .name = "wm8994-codec" },
+ { .name = "wm8994-gpio" },
+};
+
+/*
+ * Supplies for the main bulk of CODEC; the LDO supplies are ignored
+ * and should be handled via the standard regulator API supply
+ * management.
+ */
+static const char *wm8994_main_supplies[] = {
+ // "DBVDD",
+ // "DCVDD",
+ // "AVDD1",
+ // "AVDD2",
+ // "CPVDD",
+ // "SPKVDD1",
+ // "SPKVDD2",
+};
+
+#ifdef CONFIG_PM
+static int wm8994_device_suspend(struct device *dev)
+{
+ struct wm8994 *wm8994 = dev_get_drvdata(dev);
+ int ret;
+
+ /* GPIO configuration state is saved here since we may be configuring
+ * the GPIO alternate functions even if we're not using the gpiolib
+ * driver for them.
+ */
+ ret = wm8994_read(wm8994, WM8994_GPIO_1, WM8994_NUM_GPIO_REGS * 2,
+ &wm8994->gpio_regs);
+ if (ret < 0)
+ dev_err(dev, "Failed to save GPIO registers: %d\n", ret);
+
+ /* For similar reasons we also stash the regulator states */
+ ret = wm8994_read(wm8994, WM8994_LDO_1, WM8994_NUM_LDO_REGS * 2,
+ &wm8994->ldo_regs);
+ if (ret < 0)
+ dev_err(dev, "Failed to save LDO registers: %d\n", ret);
+
+ ret = regulator_bulk_disable(ARRAY_SIZE(wm8994_main_supplies),
+ wm8994->supplies);
+ if (ret != 0) {
+ dev_err(dev, "Failed to disable supplies: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int wm8994_device_resume(struct device *dev)
+{
+ struct wm8994 *wm8994 = dev_get_drvdata(dev);
+ int ret;
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(wm8994_main_supplies),
+ wm8994->supplies);
+ if (ret != 0) {
+ dev_err(dev, "Failed to enable supplies: %d\n", ret);
+ return ret;
+ }
+
+ ret = wm8994_write(wm8994, WM8994_LDO_1, WM8994_NUM_LDO_REGS * 2,
+ &wm8994->ldo_regs);
+ if (ret < 0)
+ dev_err(dev, "Failed to restore LDO registers: %d\n", ret);
+
+ ret = wm8994_write(wm8994, WM8994_GPIO_1, WM8994_NUM_GPIO_REGS * 2,
+ &wm8994->gpio_regs);
+ if (ret < 0)
+ dev_err(dev, "Failed to restore GPIO registers: %d\n", ret);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_REGULATOR
+static int wm8994_ldo_in_use(struct wm8994_pdata *pdata, int ldo)
+{
+ struct wm8994_ldo_pdata *ldo_pdata;
+
+ if (!pdata)
+ return 0;
+
+ ldo_pdata = &pdata->ldo[ldo];
+
+ if (!ldo_pdata->init_data)
+ return 0;
+
+ return ldo_pdata->init_data->num_consumer_supplies != 0;
+}
+#else
+static int wm8994_ldo_in_use(struct wm8994_pdata *pdata, int ldo)
+{
+ return 0;
+}
+#endif
+
+/*
+ * Instantiate the generic non-control parts of the device.
+ */
+static int wm8994_device_init(struct wm8994 *wm8994, unsigned long id, int irq)
+{
+ struct wm8994_pdata *pdata = wm8994->dev->platform_data;
+ int ret, i;
+
+ mutex_init(&wm8994->io_lock);
+ dev_set_drvdata(wm8994->dev, wm8994);
+
+ /* Add the on-chip regulators first for bootstrapping */
+ ret = mfd_add_devices(wm8994->dev, -1,
+ wm8994_regulator_devs,
+ ARRAY_SIZE(wm8994_regulator_devs),
+ NULL, 0);
+ if (ret != 0) {
+ dev_err(wm8994->dev, "Failed to add children: %d\n", ret);
+ goto err;
+ }
+
+ wm8994->supplies = kzalloc(sizeof(struct regulator_bulk_data) *
+ ARRAY_SIZE(wm8994_main_supplies),
+ GFP_KERNEL);
+ if (!wm8994->supplies)
+ goto err;
+
+ for (i = 0; i < ARRAY_SIZE(wm8994_main_supplies); i++)
+ wm8994->supplies[i].supply = wm8994_main_supplies[i];
+
+ ret = regulator_bulk_get(wm8994->dev, ARRAY_SIZE(wm8994_main_supplies),
+ wm8994->supplies);
+ if (ret != 0) {
+ dev_err(wm8994->dev, "Failed to get supplies: %d\n", ret);
+ goto err_supplies;
+ }
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(wm8994_main_supplies),
+ wm8994->supplies);
+ if (ret != 0) {
+ dev_err(wm8994->dev, "Failed to enable supplies: %d\n", ret);
+ goto err_get;
+ }
+
+ ret = wm8994_reg_read(wm8994, WM8994_SOFTWARE_RESET);
+ if (ret < 0) {
+ dev_err(wm8994->dev, "Failed to read ID register\n");
+ goto err_enable;
+ }
+ if (ret != 0x8994) {
+ dev_err(wm8994->dev, "Device is not a WM8994, ID is %x\n",
+ ret);
+ ret = -EINVAL;
+ goto err_enable;
+ }
+
+ ret = wm8994_reg_read(wm8994, WM8994_CHIP_REVISION);
+ if (ret < 0) {
+ dev_err(wm8994->dev, "Failed to read revision register: %d\n",
+ ret);
+ goto err_enable;
+ }
+
+ switch (ret) {
+ case 0:
+ case 1:
+ dev_warn(wm8994->dev, "revision %c not fully supported\n",
+ 'A' + ret);
+ break;
+ default:
+ dev_info(wm8994->dev, "revision %c\n", 'A' + ret);
+ break;
+ }
+
+
+ if (pdata) {
+ wm8994->gpio_base = pdata->gpio_base;
+
+ /* GPIO configuration is only applied if it's non-zero */
+ for (i = 0; i < ARRAY_SIZE(pdata->gpio_defaults); i++) {
+ if (pdata->gpio_defaults[i]) {
+ wm8994_set_bits(wm8994, WM8994_GPIO_1 + i,
+ 0xffff,
+ pdata->gpio_defaults[i]);
+ }
+ }
+ }
+
+ /* In some system designs where the regulators are not in use,
+ * we can achieve a small reduction in leakage currents by
+ * floating LDO outputs. This bit makes no difference if the
+ * LDOs are enabled, it only affects cases where the LDOs were
+ * in operation and are then disabled.
+ */
+ for (i = 0; i < WM8994_NUM_LDO_REGS; i++) {
+ if (wm8994_ldo_in_use(pdata, i))
+ wm8994_set_bits(wm8994, WM8994_LDO_1 + i,
+ WM8994_LDO1_DISCH, WM8994_LDO1_DISCH);
+ else
+ wm8994_set_bits(wm8994, WM8994_LDO_1 + i,
+ WM8994_LDO1_DISCH, 0);
+ }
+
+ ret = mfd_add_devices(wm8994->dev, -1,
+ wm8994_devs, ARRAY_SIZE(wm8994_devs),
+ NULL, 0);
+ if (ret != 0) {
+ dev_err(wm8994->dev, "Failed to add children: %d\n", ret);
+ goto err_enable;
+ }
+
+ return 0;
+
+err_enable:
+ regulator_bulk_disable(ARRAY_SIZE(wm8994_main_supplies),
+ wm8994->supplies);
+err_get:
+ regulator_bulk_free(ARRAY_SIZE(wm8994_main_supplies), wm8994->supplies);
+err_supplies:
+ kfree(wm8994->supplies);
+err:
+ mfd_remove_devices(wm8994->dev);
+ kfree(wm8994);
+ return ret;
+}
+
+static void wm8994_device_exit(struct wm8994 *wm8994)
+{
+ mfd_remove_devices(wm8994->dev);
+ regulator_bulk_disable(ARRAY_SIZE(wm8994_main_supplies),
+ wm8994->supplies);
+ regulator_bulk_free(ARRAY_SIZE(wm8994_main_supplies), wm8994->supplies);
+ kfree(wm8994->supplies);
+ kfree(wm8994);
+}
+
+static int wm8994_i2c_read_device(struct wm8994 *wm8994, unsigned short reg,
+ int bytes, void *dest)
+{
+ struct i2c_client *i2c = wm8994->control_data;
+ int ret;
+ u16 r = cpu_to_be16(reg);
+
+ ret = i2c_master_send(i2c, (unsigned char *)&r, 2);
+ if (ret < 0)
+ return ret;
+ if (ret != 2)
+ return -EIO;
+
+ ret = i2c_master_recv(i2c, dest, bytes);
+ if (ret < 0)
+ return ret;
+ if (ret != bytes)
+ return -EIO;
+ return 0;
+}
+
+/* Currently we allocate the write buffer on the stack; this is OK for
+ * small writes - if we need to do large writes this will need to be
+ * revised.
+ */
+static int wm8994_i2c_write_device(struct wm8994 *wm8994, unsigned short reg,
+ int bytes, void *src)
+{
+ struct i2c_client *i2c = wm8994->control_data;
+ unsigned char msg[bytes + 2];
+ int ret;
+
+ reg = cpu_to_be16(reg);
+ memcpy(&msg[0], ®, 2);
+ memcpy(&msg[2], src, bytes);
+
+ ret = i2c_master_send(i2c, msg, bytes + 2);
+ if (ret < 0)
+ return ret;
+ if (ret < bytes + 2)
+ return -EIO;
+
+ return 0;
+}
+
+static int wm8994_i2c_probe(struct i2c_client *i2c,
+ const struct i2c_device_id *id)
+{
+ struct wm8994 *wm8994;
+
+ wm8994 = kzalloc(sizeof(struct wm8994), GFP_KERNEL);
+ if (wm8994 == NULL) {
+ kfree(i2c);
+ return -ENOMEM;
+ }
+
+ i2c_set_clientdata(i2c, wm8994);
+ wm8994->dev = &i2c->dev;
+ wm8994->control_data = i2c;
+ wm8994->read_dev = wm8994_i2c_read_device;
+ wm8994->write_dev = wm8994_i2c_write_device;
+
+ return wm8994_device_init(wm8994, id->driver_data, i2c->irq);
+}
+
+static int wm8994_i2c_remove(struct i2c_client *i2c)
+{
+ struct wm8994 *wm8994 = i2c_get_clientdata(i2c);
+
+ wm8994_device_exit(wm8994);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int wm8994_i2c_suspend(struct i2c_client *i2c, pm_message_t state)
+{
+ return wm8994_device_suspend(&i2c->dev);
+}
+
+static int wm8994_i2c_resume(struct i2c_client *i2c)
+{
+ return wm8994_device_resume(&i2c->dev);
+}
+#else
+#define wm8994_i2c_suspend NULL
+#define wm8994_i2c_resume NULL
+#endif
+
+static const struct i2c_device_id wm8994_i2c_id[] = {
+ { "wm8994", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, wm8994_i2c_id);
+
+static struct i2c_driver wm8994_i2c_driver = {
+ .driver = {
+ .name = "wm8994",
+ .owner = THIS_MODULE,
+ },
+ .probe = wm8994_i2c_probe,
+ .remove = wm8994_i2c_remove,
+ .suspend = wm8994_i2c_suspend,
+ .resume = wm8994_i2c_resume,
+ .id_table = wm8994_i2c_id,
+};
+
+static int __init wm8994_i2c_init(void)
+{
+ int ret;
+
+ ret = i2c_add_driver(&wm8994_i2c_driver);
+ if (ret != 0)
+ pr_err("Failed to register wm8994 I2C driver: %d\n", ret);
+
+ return ret;
+}
+module_init(wm8994_i2c_init);
+
+static void __exit wm8994_i2c_exit(void)
+{
+ i2c_del_driver(&wm8994_i2c_driver);
+}
+module_exit(wm8994_i2c_exit);
+
+MODULE_DESCRIPTION("Core support for the WM8994 audio CODEC");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 9c24042e6952..b78010ca3c6b 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -83,6 +83,14 @@ config REGULATOR_TPS65910
This driver supports the voltage regulators provided by
this family of companion chips.
+#add by qjb
+config REGULATOR_WM8994
+ tristate "Wolfson Microelectronics WM8994 CODEC"
+ depends on MFD_WM8994
+ help
+ This driver provides support for the voltage regulators on the
+ WM8994 CODEC.
+
config REGULATOR_WM831X
tristate "Wolfson Microelcronics WM831x PMIC regulators"
depends on MFD_WM831X
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index ec0e204b5541..e8bf0fa9945e 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -29,5 +29,7 @@ obj-$(CONFIG_RK29_PWM_REGULATOR) += rk29-pwm-regulator.o
obj-$(CONFIG_REGULATOR_TPS65023) += tps65023-regulator.o
obj-$(CONFIG_REGULATOR_TPS6507X) += tps6507x-regulator.o
+#add by qjb
+obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o
ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/wm8994-regulator.c b/drivers/regulator/wm8994-regulator.c
new file mode 100644
index 000000000000..7ce826066da0
--- /dev/null
+++ b/drivers/regulator/wm8994-regulator.c
@@ -0,0 +1,308 @@
+/*
+ * wm8994-regulator.c -- Regulator driver for the WM8994
+ *
+ * Copyright 2009 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/gpio.h>
+#include <linux/slab.h>
+
+#include <linux/mfd/wm8994/core.h>
+#include <linux/mfd/wm8994/registers.h>
+#include <linux/mfd/wm8994/pdata.h>
+
+struct wm8994_ldo {
+ int enable;
+ bool is_enabled;
+ struct regulator_dev *regulator;
+ struct wm8994 *wm8994;
+};
+
+#define WM8994_LDO1_MAX_SELECTOR 0x7
+#define WM8994_LDO2_MAX_SELECTOR 0x3
+
+static int wm8994_ldo_enable(struct regulator_dev *rdev)
+{
+ struct wm8994_ldo *ldo = rdev_get_drvdata(rdev);
+
+ /* If we have no soft control assume that the LDO is always enabled. */
+ if (!ldo->enable)
+ return 0;
+
+ gpio_set_value(ldo->enable, 1);
+ ldo->is_enabled = true;
+
+ return 0;
+}
+
+static int wm8994_ldo_disable(struct regulator_dev *rdev)
+{
+ struct wm8994_ldo *ldo = rdev_get_drvdata(rdev);
+
+ /* If we have no soft control assume that the LDO is always enabled. */
+ if (!ldo->enable)
+ return -EINVAL;
+
+ gpio_set_value(ldo->enable, 0);
+ ldo->is_enabled = false;
+
+ return 0;
+}
+
+static int wm8994_ldo_is_enabled(struct regulator_dev *rdev)
+{
+ struct wm8994_ldo *ldo = rdev_get_drvdata(rdev);
+
+ return ldo->is_enabled;
+}
+
+static int wm8994_ldo_enable_time(struct regulator_dev *rdev)
+{
+ /* 3ms is fairly conservative but this shouldn't be too performance
+ * critical; can be tweaked per-system if required. */
+ return 3000;
+}
+
+static int wm8994_ldo1_list_voltage(struct regulator_dev *rdev,
+ unsigned int selector)
+{
+ if (selector > WM8994_LDO1_MAX_SELECTOR)
+ return -EINVAL;
+
+ return (selector * 100000) + 2400000;
+}
+
+static int wm8994_ldo1_get_voltage(struct regulator_dev *rdev)
+{
+ struct wm8994_ldo *ldo = rdev_get_drvdata(rdev);
+ int val;
+
+ val = wm8994_reg_read(ldo->wm8994, WM8994_LDO_1);
+ if (val < 0)
+ return val;
+
+ val = (val & WM8994_LDO1_VSEL_MASK) >> WM8994_LDO1_VSEL_SHIFT;
+
+ return wm8994_ldo1_list_voltage(rdev, val);
+}
+
+static int wm8994_ldo1_set_voltage(struct regulator_dev *rdev,
+ int min_uV, int max_uV)
+{
+ struct wm8994_ldo *ldo = rdev_get_drvdata(rdev);
+ int selector, v;
+
+ selector = (min_uV - 2400000) / 100000;
+ v = wm8994_ldo1_list_voltage(rdev, selector);
+ if (v < 0 || v > max_uV)
+ return -EINVAL;
+
+ selector <<= WM8994_LDO1_VSEL_SHIFT;
+
+ return wm8994_set_bits(ldo->wm8994, WM8994_LDO_1,
+ WM8994_LDO1_VSEL_MASK, selector);
+}
+
+static struct regulator_ops wm8994_ldo1_ops = {
+ .enable = wm8994_ldo_enable,
+ .disable = wm8994_ldo_disable,
+ .is_enabled = wm8994_ldo_is_enabled,
+// .enable_time = wm8994_ldo_enable_time,
+
+ .list_voltage = wm8994_ldo1_list_voltage,
+ .get_voltage = wm8994_ldo1_get_voltage,
+ .set_voltage = wm8994_ldo1_set_voltage,
+};
+
+static int wm8994_ldo2_list_voltage(struct regulator_dev *rdev,
+ unsigned int selector)
+{
+ if (selector > WM8994_LDO2_MAX_SELECTOR)
+ return -EINVAL;
+
+ return (selector * 100000) + 900000;
+}
+
+static int wm8994_ldo2_get_voltage(struct regulator_dev *rdev)
+{
+ struct wm8994_ldo *ldo = rdev_get_drvdata(rdev);
+ int val;
+
+ val = wm8994_reg_read(ldo->wm8994, WM8994_LDO_2);
+ if (val < 0)
+ return val;
+
+ val = (val & WM8994_LDO2_VSEL_MASK) >> WM8994_LDO2_VSEL_SHIFT;
+
+ return wm8994_ldo2_list_voltage(rdev, val);
+}
+
+static int wm8994_ldo2_set_voltage(struct regulator_dev *rdev,
+ int min_uV, int max_uV)
+{
+ struct wm8994_ldo *ldo = rdev_get_drvdata(rdev);
+ int selector, v;
+
+ selector = (min_uV - 900000) / 100000;
+ v = wm8994_ldo2_list_voltage(rdev, selector);
+ if (v < 0 || v > max_uV)
+ return -EINVAL;
+
+ selector <<= WM8994_LDO2_VSEL_SHIFT;
+
+ return wm8994_set_bits(ldo->wm8994, WM8994_LDO_2,
+ WM8994_LDO2_VSEL_MASK, selector);
+}
+
+static struct regulator_ops wm8994_ldo2_ops = {
+ .enable = wm8994_ldo_enable,
+ .disable = wm8994_ldo_disable,
+ .is_enabled = wm8994_ldo_is_enabled,
+// .enable_time = wm8994_ldo_enable_time,
+
+ .list_voltage = wm8994_ldo2_list_voltage,
+ .get_voltage = wm8994_ldo2_get_voltage,
+ .set_voltage = wm8994_ldo2_set_voltage,
+};
+
+static struct regulator_desc wm8994_ldo_desc[] = {
+ {
+ .name = "LDO1",
+ .id = 1,
+ .type = REGULATOR_VOLTAGE,
+ .n_voltages = WM8994_LDO1_MAX_SELECTOR + 1,
+ .ops = &wm8994_ldo1_ops,
+ .owner = THIS_MODULE,
+ },
+ {
+ .name = "LDO2",
+ .id = 2,
+ .type = REGULATOR_VOLTAGE,
+ .n_voltages = WM8994_LDO2_MAX_SELECTOR + 1,
+ .ops = &wm8994_ldo2_ops,
+ .owner = THIS_MODULE,
+ },
+};
+
+static __devinit int wm8994_ldo_probe(struct platform_device *pdev)
+{
+ struct wm8994 *wm8994 = dev_get_drvdata(pdev->dev.parent);
+ struct wm8994_pdata *pdata = wm8994->dev->platform_data;
+ int id = pdev->id % ARRAY_SIZE(pdata->ldo);
+ struct wm8994_ldo *ldo;
+ int ret;
+
+ dev_dbg(&pdev->dev, "Probing LDO%d\n", id + 1);
+
+ if (!pdata)
+ return -ENODEV;
+
+ ldo = kzalloc(sizeof(struct wm8994_ldo), GFP_KERNEL);
+ if (ldo == NULL) {
+ dev_err(&pdev->dev, "Unable to allocate private data\n");
+ return -ENOMEM;
+ }
+
+ ldo->wm8994 = wm8994;
+
+ ldo->is_enabled = true;
+
+ if (pdata->ldo[id].enable && gpio_is_valid(pdata->ldo[id].enable)) {
+ ldo->enable = pdata->ldo[id].enable;
+
+ ret = gpio_request(ldo->enable, "WM8994 LDO enable");
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to get enable GPIO: %d\n",
+ ret);
+ goto err;
+ }
+
+ ret = gpio_direction_output(ldo->enable, ldo->is_enabled);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to set GPIO up: %d\n",
+ ret);
+ goto err_gpio;
+ }
+ }
+
+ ldo->regulator = regulator_register(&wm8994_ldo_desc[id], &pdev->dev,
+ pdata->ldo[id].init_data, ldo);
+ if (IS_ERR(ldo->regulator)) {
+ ret = PTR_ERR(ldo->regulator);
+ dev_err(wm8994->dev, "Failed to register LDO%d: %d\n",
+ id + 1, ret);
+ goto err_gpio;
+ }
+
+ platform_set_drvdata(pdev, ldo);
+
+ return 0;
+
+err_gpio:
+ if (gpio_is_valid(ldo->enable))
+ gpio_free(ldo->enable);
+err:
+ kfree(ldo);
+ return ret;
+}
+
+static __devexit int wm8994_ldo_remove(struct platform_device *pdev)
+{
+ struct wm8994_ldo *ldo = platform_get_drvdata(pdev);
+
+ platform_set_drvdata(pdev, NULL);
+
+ regulator_unregister(ldo->regulator);
+ if (gpio_is_valid(ldo->enable))
+ gpio_free(ldo->enable);
+ kfree(ldo);
+
+ return 0;
+}
+
+static struct platform_driver wm8994_ldo_driver = {
+ .probe = wm8994_ldo_probe,
+ .remove = __devexit_p(wm8994_ldo_remove),
+ .driver = {
+ .name = "wm8994-ldo",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init wm8994_ldo_init(void)
+{
+ int ret;
+
+ ret = platform_driver_register(&wm8994_ldo_driver);
+ if (ret != 0)
+ pr_err("Failed to register Wm8994 GP LDO driver: %d\n", ret);
+
+ return ret;
+}
+subsys_initcall(wm8994_ldo_init);
+
+static void __exit wm8994_ldo_exit(void)
+{
+ platform_driver_unregister(&wm8994_ldo_driver);
+}
+module_exit(wm8994_ldo_exit);
+
+/* Module information */
+MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
+MODULE_DESCRIPTION("WM8994 LDO driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:wm8994-ldo");
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h
new file mode 100644
index 000000000000..b06ff2846748
--- /dev/null
+++ b/include/linux/mfd/wm8994/core.h
@@ -0,0 +1,54 @@
+/*
+ * include/linux/mfd/wm8994/core.h -- Core interface for WM8994
+ *
+ * Copyright 2009 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MFD_WM8994_CORE_H__
+#define __MFD_WM8994_CORE_H__
+
+struct regulator_dev;
+struct regulator_bulk_data;
+
+#define WM8994_NUM_GPIO_REGS 11
+#define WM8994_NUM_LDO_REGS 2
+
+struct wm8994 {
+ struct mutex io_lock;
+
+ struct device *dev;
+ int (*read_dev)(struct wm8994 *wm8994, unsigned short reg,
+ int bytes, void *dest);
+ int (*write_dev)(struct wm8994 *wm8994, unsigned short reg,
+ int bytes, void *src);
+
+ void *control_data;
+
+ int gpio_base;
+
+ /* Used over suspend/resume */
+ u16 ldo_regs[WM8994_NUM_LDO_REGS];
+ u16 gpio_regs[WM8994_NUM_GPIO_REGS];
+
+ struct regulator_dev *dbvdd;
+ struct regulator_bulk_data *supplies;
+};
+
+/* Device I/O API */
+int wm8994_reg_read(struct wm8994 *wm8994, unsigned short reg);
+int wm8994_reg_write(struct wm8994 *wm8994, unsigned short reg,
+ unsigned short val);
+int wm8994_set_bits(struct wm8994 *wm8994, unsigned short reg,
+ unsigned short mask, unsigned short val);
+int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg,
+ int count, u16 *buf);
+
+#endif
diff --git a/include/linux/mfd/wm8994/gpio.h b/include/linux/mfd/wm8994/gpio.h
new file mode 100644
index 000000000000..b4d4c22991e8
--- /dev/null
+++ b/include/linux/mfd/wm8994/gpio.h
@@ -0,0 +1,72 @@
+/*
+ * include/linux/mfd/wm8994/gpio.h - GPIO configuration for WM8994
+ *
+ * Copyright 2009 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MFD_WM8994_GPIO_H__
+#define __MFD_WM8994_GPIO_H__
+
+#define WM8994_GPIO_MAX 11
+
+#define WM8994_GP_FN_PIN_SPECIFIC 0
+#define WM8994_GP_FN_GPIO 1
+#define WM8994_GP_FN_SDOUT 2
+#define WM8994_GP_FN_IRQ 3
+#define WM8994_GP_FN_TEMPERATURE 4
+#define WM8994_GP_FN_MICBIAS1_DET 5
+#define WM8994_GP_FN_MICBIAS1_SHORT 6
+#define WM8994_GP_FN_MICBIAS2_DET 7
+#define WM8994_GP_FN_MICBIAS2_SHORT 8
+#define WM8994_GP_FN_FLL1_LOCK 9
+#define WM8994_GP_FN_FLL2_LOCK 10
+#define WM8994_GP_FN_SRC1_LOCK 11
+#define WM8994_GP_FN_SRC2_LOCK 12
+#define WM8994_GP_FN_DRC1_ACT 13
+#define WM8994_GP_FN_DRC2_ACT 14
+#define WM8994_GP_FN_DRC3_ACT 15
+#define WM8994_GP_FN_WSEQ_STATUS 16
+#define WM8994_GP_FN_FIFO_ERROR 17
+#define WM8994_GP_FN_OPCLK 18
+
+#define WM8994_GPN_DIR 0x8000 /* GPN_DIR */
+#define WM8994_GPN_DIR_MASK 0x8000 /* GPN_DIR */
+#define WM8994_GPN_DIR_SHIFT 15 /* GPN_DIR */
+#define WM8994_GPN_DIR_WIDTH 1 /* GPN_DIR */
+#define WM8994_GPN_PU 0x4000 /* GPN_PU */
+#define WM8994_GPN_PU_MASK 0x4000 /* GPN_PU */
+#define WM8994_GPN_PU_SHIFT 14 /* GPN_PU */
+#define WM8994_GPN_PU_WIDTH 1 /* GPN_PU */
+#define WM8994_GPN_PD 0x2000 /* GPN_PD */
+#define WM8994_GPN_PD_MASK 0x2000 /* GPN_PD */
+#define WM8994_GPN_PD_SHIFT 13 /* GPN_PD */
+#define WM8994_GPN_PD_WIDTH 1 /* GPN_PD */
+#define WM8994_GPN_POL 0x0400 /* GPN_POL */
+#define WM8994_GPN_POL_MASK 0x0400 /* GPN_POL */
+#define WM8994_GPN_POL_SHIFT 10 /* GPN_POL */
+#define WM8994_GPN_POL_WIDTH 1 /* GPN_POL */
+#define WM8994_GPN_OP_CFG 0x0200 /* GPN_OP_CFG */
+#define WM8994_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */
+#define WM8994_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */
+#define WM8994_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */
+#define WM8994_GPN_DB 0x0100 /* GPN_DB */
+#define WM8994_GPN_DB_MASK 0x0100 /* GPN_DB */
+#define WM8994_GPN_DB_SHIFT 8 /* GPN_DB */
+#define WM8994_GPN_DB_WIDTH 1 /* GPN_DB */
+#define WM8994_GPN_LVL 0x0040 /* GPN_LVL */
+#define WM8994_GPN_LVL_MASK 0x0040 /* GPN_LVL */
+#define WM8994_GPN_LVL_SHIFT 6 /* GPN_LVL */
+#define WM8994_GPN_LVL_WIDTH 1 /* GPN_LVL */
+#define WM8994_GPN_FN_MASK 0x001F /* GPN_FN - [4:0] */
+#define WM8994_GPN_FN_SHIFT 0 /* GPN_FN - [4:0] */
+#define WM8994_GPN_FN_WIDTH 5 /* GPN_FN - [4:0] */
+
+#endif
diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h
new file mode 100644
index 000000000000..70d6a8687dc5
--- /dev/null
+++ b/include/linux/mfd/wm8994/pdata.h
@@ -0,0 +1,97 @@
+/*
+ * include/linux/mfd/wm8994/pdata.h -- Platform data for WM8994
+ *
+ * Copyright 2009 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MFD_WM8994_PDATA_H__
+#define __MFD_WM8994_PDATA_H__
+
+#define WM8994_NUM_LDO 2
+#define WM8994_NUM_GPIO 11
+
+struct wm8994_ldo_pdata {
+ /** GPIOs to enable regulator, 0 or less if not available */
+ int enable;
+
+ const char *supply;
+ struct regulator_init_data *init_data;
+};
+
+#define WM8994_CONFIGURE_GPIO 0x8000
+
+#define WM8994_DRC_REGS 5
+#define WM8994_EQ_REGS 19
+
+/**
+ * DRC configurations are specified with a label and a set of register
+ * values to write (the enable bits will be ignored). At runtime an
+ * enumerated control will be presented for each DRC block allowing
+ * the user to choose the configration to use.
+ *
+ * Configurations may be generated by hand or by using the DRC control
+ * panel provided by the WISCE - see http://www.wolfsonmicro.com/wisce/
+ * for details.
+ */
+struct wm8994_drc_cfg {
+ const char *name;
+ u16 regs[WM8994_DRC_REGS];
+};
+
+/**
+ * ReTune Mobile configurations are specified with a label, sample
+ * rate and set of values to write (the enable bits will be ignored).
+ *
+ * Configurations are expected to be generated using the ReTune Mobile
+ * control panel in WISCE - see http://www.wolfsonmicro.com/wisce/
+ */
+struct wm8994_retune_mobile_cfg {
+ const char *name;
+ unsigned int rate;
+ u16 regs[WM8994_EQ_REGS];
+};
+
+struct wm8994_pdata {
+ int gpio_base;
+
+ /**
+ * Default values for GPIOs if non-zero, WM8994_CONFIGURE_GPIO
+ * can be used for all zero values.
+ */
+ int gpio_defaults[WM8994_NUM_GPIO];
+
+ struct wm8994_ldo_pdata ldo[WM8994_NUM_LDO];
+
+
+ int num_drc_cfgs;
+ struct wm8994_drc_cfg *drc_cfgs;
+
+ int num_retune_mobile_cfgs;
+ struct wm8994_retune_mobile_cfg *retune_mobile_cfgs;
+
+ /* LINEOUT can be differential or single ended */
+ unsigned int lineout1_diff:1;
+ unsigned int lineout2_diff:1;
+
+ /* Common mode feedback */
+ unsigned int lineout1fb:1;
+ unsigned int lineout2fb:1;
+
+ /* Microphone biases: 0=0.9*AVDD1 1=0.65*AVVD1 */
+ unsigned int micbias1_lvl:1;
+ unsigned int micbias2_lvl:1;
+
+ /* Jack detect threashold levels, see datasheet for values */
+ unsigned int jd_scthr:2;
+ unsigned int jd_thr:2;
+};
+
+#endif
diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h
new file mode 100644
index 000000000000..967f62f54159
--- /dev/null
+++ b/include/linux/mfd/wm8994/registers.h
@@ -0,0 +1,4292 @@
+/*
+ * include/linux/mfd/wm8994/registers.h -- Register definitions for WM8994
+ *
+ * Copyright 2009 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MFD_WM8994_REGISTERS_H__
+#define __MFD_WM8994_REGISTERS_H__
+
+/*
+ * Register values.
+ */
+#define WM8994_SOFTWARE_RESET 0x00
+#define WM8994_POWER_MANAGEMENT_1 0x01
+#define WM8994_POWER_MANAGEMENT_2 0x02
+#define WM8994_POWER_MANAGEMENT_3 0x03
+#define WM8994_POWER_MANAGEMENT_4 0x04
+#define WM8994_POWER_MANAGEMENT_5 0x05
+#define WM8994_POWER_MANAGEMENT_6 0x06
+#define WM8994_INPUT_MIXER_1 0x15
+#define WM8994_LEFT_LINE_INPUT_1_2_VOLUME 0x18
+#define WM8994_LEFT_LINE_INPUT_3_4_VOLUME 0x19
+#define WM8994_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A
+#define WM8994_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B
+#define WM8994_LEFT_OUTPUT_VOLUME 0x1C
+#define WM8994_RIGHT_OUTPUT_VOLUME 0x1D
+#define WM8994_LINE_OUTPUTS_VOLUME 0x1E
+#define WM8994_HPOUT2_VOLUME 0x1F
+#define WM8994_LEFT_OPGA_VOLUME 0x20
+#define WM8994_RIGHT_OPGA_VOLUME 0x21
+#define WM8994_SPKMIXL_ATTENUATION 0x22
+#define WM8994_SPKMIXR_ATTENUATION 0x23
+#define WM8994_SPKOUT_MIXERS 0x24
+#define WM8994_CLASSD 0x25
+#define WM8994_SPEAKER_VOLUME_LEFT 0x26
+#define WM8994_SPEAKER_VOLUME_RIGHT 0x27
+#define WM8994_INPUT_MIXER_2 0x28
+#define WM8994_INPUT_MIXER_3 0x29
+#define WM8994_INPUT_MIXER_4 0x2A
+#define WM8994_INPUT_MIXER_5 0x2B
+#define WM8994_INPUT_MIXER_6 0x2C
+#define WM8994_OUTPUT_MIXER_1 0x2D
+#define WM8994_OUTPUT_MIXER_2 0x2E
+#define WM8994_OUTPUT_MIXER_3 0x2F
+#define WM8994_OUTPUT_MIXER_4 0x30
+#define WM8994_OUTPUT_MIXER_5 0x31
+#define WM8994_OUTPUT_MIXER_6 0x32
+#define WM8994_HPOUT2_MIXER 0x33
+#define WM8994_LINE_MIXER_1 0x34
+#define WM8994_LINE_MIXER_2 0x35
+#define WM8994_SPEAKER_MIXER 0x36
+#define WM8994_ADDITIONAL_CONTROL 0x37
+#define WM8994_ANTIPOP_1 0x38
+#define WM8994_ANTIPOP_2 0x39
+#define WM8994_MICBIAS 0x3A
+#define WM8994_LDO_1 0x3B
+#define WM8994_LDO_2 0x3C
+#define WM8994_CHARGE_PUMP_1 0x4C
+#define WM8994_CLASS_W_1 0x51
+#define WM8994_DC_SERVO_1 0x54
+#define WM8994_DC_SERVO_2 0x55
+#define WM8994_DC_SERVO_4 0x57
+#define WM8994_DC_SERVO_READBACK 0x58
+#define WM8994_ANALOGUE_HP_1 0x60
+#define WM8994_CHIP_REVISION 0x100
+#define WM8994_CONTROL_INTERFACE 0x101
+#define WM8994_WRITE_SEQUENCER_CTRL_1 0x110
+#define WM8994_WRITE_SEQUENCER_CTRL_2 0x111
+#define WM8994_AIF1_CLOCKING_1 0x200
+#define WM8994_AIF1_CLOCKING_2 0x201
+#define WM8994_AIF2_CLOCKING_1 0x204
+#define WM8994_AIF2_CLOCKING_2 0x205
+#define WM8994_CLOCKING_1 0x208
+#define WM8994_CLOCKING_2 0x209
+#define WM8994_AIF1_RATE 0x210
+#define WM8994_AIF2_RATE 0x211
+#define WM8994_RATE_STATUS 0x212
+#define WM8994_FLL1_CONTROL_1 0x220
+#define WM8994_FLL1_CONTROL_2 0x221
+#define WM8994_FLL1_CONTROL_3 0x222
+#define WM8994_FLL1_CONTROL_4 0x223
+#define WM8994_FLL1_CONTROL_5 0x224
+#define WM8994_FLL2_CONTROL_1 0x240
+#define WM8994_FLL2_CONTROL_2 0x241
+#define WM8994_FLL2_CONTROL_3 0x242
+#define WM8994_FLL2_CONTROL_4 0x243
+#define WM8994_FLL2_CONTROL_5 0x244
+#define WM8994_AIF1_CONTROL_1 0x300
+#define WM8994_AIF1_CONTROL_2 0x301
+#define WM8994_AIF1_MASTER_SLAVE 0x302
+#define WM8994_AIF1_BCLK 0x303
+#define WM8994_AIF1ADC_LRCLK 0x304
+#define WM8994_AIF1DAC_LRCLK 0x305
+#define WM8994_AIF1DAC_DATA 0x306
+#define WM8994_AIF1ADC_DATA 0x307
+#define WM8994_AIF2_CONTROL_1 0x310
+#define WM8994_AIF2_CONTROL_2 0x311
+#define WM8994_AIF2_MASTER_SLAVE 0x312
+#define WM8994_AIF2_BCLK 0x313
+#define WM8994_AIF2ADC_LRCLK 0x314
+#define WM8994_AIF2DAC_LRCLK 0x315
+#define WM8994_AIF2DAC_DATA 0x316
+#define WM8994_AIF2ADC_DATA 0x317
+#define WM8994_AIF1_ADC1_LEFT_VOLUME 0x400
+#define WM8994_AIF1_ADC1_RIGHT_VOLUME 0x401
+#define WM8994_AIF1_DAC1_LEFT_VOLUME 0x402
+#define WM8994_AIF1_DAC1_RIGHT_VOLUME 0x403
+#define WM8994_AIF1_ADC2_LEFT_VOLUME 0x404
+#define WM8994_AIF1_ADC2_RIGHT_VOLUME 0x405
+#define WM8994_AIF1_DAC2_LEFT_VOLUME 0x406
+#define WM8994_AIF1_DAC2_RIGHT_VOLUME 0x407
+#define WM8994_AIF1_ADC1_FILTERS 0x410
+#define WM8994_AIF1_ADC2_FILTERS 0x411
+#define WM8994_AIF1_DAC1_FILTERS_1 0x420
+#define WM8994_AIF1_DAC1_FILTERS_2 0x421
+#define WM8994_AIF1_DAC2_FILTERS_1 0x422
+#define WM8994_AIF1_DAC2_FILTERS_2 0x423
+#define WM8994_AIF1_DRC1_1 0x440
+#define WM8994_AIF1_DRC1_2 0x441
+#define WM8994_AIF1_DRC1_3 0x442
+#define WM8994_AIF1_DRC1_4 0x443
+#define WM8994_AIF1_DRC1_5 0x444
+#define WM8994_AIF1_DRC2_1 0x450
+#define WM8994_AIF1_DRC2_2 0x451
+#define WM8994_AIF1_DRC2_3 0x452
+#define WM8994_AIF1_DRC2_4 0x453
+#define WM8994_AIF1_DRC2_5 0x454
+#define WM8994_AIF1_DAC1_EQ_GAINS_1 0x480
+#define WM8994_AIF1_DAC1_EQ_GAINS_2 0x481
+#define WM8994_AIF1_DAC1_EQ_BAND_1_A 0x482
+#define WM8994_AIF1_DAC1_EQ_BAND_1_B 0x483
+#define WM8994_AIF1_DAC1_EQ_BAND_1_PG 0x484
+#define WM8994_AIF1_DAC1_EQ_BAND_2_A 0x485
+#define WM8994_AIF1_DAC1_EQ_BAND_2_B 0x486
+#define WM8994_AIF1_DAC1_EQ_BAND_2_C 0x487
+#define WM8994_AIF1_DAC1_EQ_BAND_2_PG 0x488
+#define WM8994_AIF1_DAC1_EQ_BAND_3_A 0x489
+#define WM8994_AIF1_DAC1_EQ_BAND_3_B 0x48A
+#define WM8994_AIF1_DAC1_EQ_BAND_3_C 0x48B
+#define WM8994_AIF1_DAC1_EQ_BAND_3_PG 0x48C
+#define WM8994_AIF1_DAC1_EQ_BAND_4_A 0x48D
+#define WM8994_AIF1_DAC1_EQ_BAND_4_B 0x48E
+#define WM8994_AIF1_DAC1_EQ_BAND_4_C 0x48F
+#define WM8994_AIF1_DAC1_EQ_BAND_4_PG 0x490
+#define WM8994_AIF1_DAC1_EQ_BAND_5_A 0x491
+#define WM8994_AIF1_DAC1_EQ_BAND_5_B 0x492
+#define WM8994_AIF1_DAC1_EQ_BAND_5_PG 0x493
+#define WM8994_AIF1_DAC2_EQ_GAINS_1 0x4A0
+#define WM8994_AIF1_DAC2_EQ_GAINS_2 0x4A1
+#define WM8994_AIF1_DAC2_EQ_BAND_1_A 0x4A2
+#define WM8994_AIF1_DAC2_EQ_BAND_1_B 0x4A3
+#define WM8994_AIF1_DAC2_EQ_BAND_1_PG 0x4A4
+#define WM8994_AIF1_DAC2_EQ_BAND_2_A 0x4A5
+#define WM8994_AIF1_DAC2_EQ_BAND_2_B 0x4A6
+#define WM8994_AIF1_DAC2_EQ_BAND_2_C 0x4A7
+#define WM8994_AIF1_DAC2_EQ_BAND_2_PG 0x4A8
+#define WM8994_AIF1_DAC2_EQ_BAND_3_A 0x4A9
+#define WM8994_AIF1_DAC2_EQ_BAND_3_B 0x4AA
+#define WM8994_AIF1_DAC2_EQ_BAND_3_C 0x4AB
+#define WM8994_AIF1_DAC2_EQ_BAND_3_PG 0x4AC
+#define WM8994_AIF1_DAC2_EQ_BAND_4_A 0x4AD
+#define WM8994_AIF1_DAC2_EQ_BAND_4_B 0x4AE
+#define WM8994_AIF1_DAC2_EQ_BAND_4_C 0x4AF
+#define WM8994_AIF1_DAC2_EQ_BAND_4_PG 0x4B0
+#define WM8994_AIF1_DAC2_EQ_BAND_5_A 0x4B1
+#define WM8994_AIF1_DAC2_EQ_BAND_5_B 0x4B2
+#define WM8994_AIF1_DAC2_EQ_BAND_5_PG 0x4B3
+#define WM8994_AIF2_ADC_LEFT_VOLUME 0x500
+#define WM8994_AIF2_ADC_RIGHT_VOLUME 0x501
+#define WM8994_AIF2_DAC_LEFT_VOLUME 0x502
+#define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503
+#define WM8994_AIF2_ADC_FILTERS 0x510
+#define WM8994_AIF2_DAC_FILTERS_1 0x520
+#define WM8994_AIF2_DAC_FILTERS_2 0x521
+#define WM8994_AIF2_DRC_1 0x540
+#define WM8994_AIF2_DRC_2 0x541
+#define WM8994_AIF2_DRC_3 0x542
+#define WM8994_AIF2_DRC_4 0x543
+#define WM8994_AIF2_DRC_5 0x544
+#define WM8994_AIF2_EQ_GAINS_1 0x580
+#define WM8994_AIF2_EQ_GAINS_2 0x581
+#define WM8994_AIF2_EQ_BAND_1_A 0x582
+#define WM8994_AIF2_EQ_BAND_1_B 0x583
+#define WM8994_AIF2_EQ_BAND_1_PG 0x584
+#define WM8994_AIF2_EQ_BAND_2_A 0x585
+#define WM8994_AIF2_EQ_BAND_2_B 0x586
+#define WM8994_AIF2_EQ_BAND_2_C 0x587
+#define WM8994_AIF2_EQ_BAND_2_PG 0x588
+#define WM8994_AIF2_EQ_BAND_3_A 0x589
+#define WM8994_AIF2_EQ_BAND_3_B 0x58A
+#define WM8994_AIF2_EQ_BAND_3_C 0x58B
+#define WM8994_AIF2_EQ_BAND_3_PG 0x58C
+#define WM8994_AIF2_EQ_BAND_4_A 0x58D
+#define WM8994_AIF2_EQ_BAND_4_B 0x58E
+#define WM8994_AIF2_EQ_BAND_4_C 0x58F
+#define WM8994_AIF2_EQ_BAND_4_PG 0x590
+#define WM8994_AIF2_EQ_BAND_5_A 0x591
+#define WM8994_AIF2_EQ_BAND_5_B 0x592
+#define WM8994_AIF2_EQ_BAND_5_PG 0x593
+#define WM8994_DAC1_MIXER_VOLUMES 0x600
+#define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601
+#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602
+#define WM8994_DAC2_MIXER_VOLUMES 0x603
+#define WM8994_DAC2_LEFT_MIXER_ROUTING 0x604
+#define WM8994_DAC2_RIGHT_MIXER_ROUTING 0x605
+#define WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING 0x606
+#define WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING 0x607
+#define WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING 0x608
+#define WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING 0x609
+#define WM8994_DAC1_LEFT_VOLUME 0x610
+#define WM8994_DAC1_RIGHT_VOLUME 0x611
+#define WM8994_DAC2_LEFT_VOLUME 0x612
+#define WM8994_DAC2_RIGHT_VOLUME 0x613
+#define WM8994_DAC_SOFTMUTE 0x614
+#define WM8994_OVERSAMPLING 0x620
+#define WM8994_SIDETONE 0x621
+#define WM8994_GPIO_1 0x700
+#define WM8994_GPIO_2 0x701
+#define WM8994_GPIO_3 0x702
+#define WM8994_GPIO_4 0x703
+#define WM8994_GPIO_5 0x704
+#define WM8994_GPIO_6 0x705
+#define WM8994_GPIO_7 0x706
+#define WM8994_GPIO_8 0x707
+#define WM8994_GPIO_9 0x708
+#define WM8994_GPIO_10 0x709
+#define WM8994_GPIO_11 0x70A
+#define WM8994_PULL_CONTROL_1 0x720
+#define WM8994_PULL_CONTROL_2 0x721
+#define WM8994_INTERRUPT_STATUS_1 0x730
+#define WM8994_INTERRUPT_STATUS_2 0x731
+#define WM8994_INTERRUPT_RAW_STATUS_2 0x732
+#define WM8994_INTERRUPT_STATUS_1_MASK 0x738
+#define WM8994_INTERRUPT_STATUS_2_MASK 0x739
+#define WM8994_INTERRUPT_CONTROL 0x740
+#define WM8994_IRQ_DEBOUNCE 0x748
+#define WM8994_WRITE_SEQUENCER_0 0x3000
+#define WM8994_WRITE_SEQUENCER_1 0x3001
+#define WM8994_WRITE_SEQUENCER_2 0x3002
+#define WM8994_WRITE_SEQUENCER_3 0x3003
+#define WM8994_WRITE_SEQUENCER_4 0x3004
+#define WM8994_WRITE_SEQUENCER_5 0x3005
+#define WM8994_WRITE_SEQUENCER_6 0x3006
+#define WM8994_WRITE_SEQUENCER_7 0x3007
+#define WM8994_WRITE_SEQUENCER_8 0x3008
+#define WM8994_WRITE_SEQUENCER_9 0x3009
+#define WM8994_WRITE_SEQUENCER_10 0x300A
+#define WM8994_WRITE_SEQUENCER_11 0x300B
+#define WM8994_WRITE_SEQUENCER_12 0x300C
+#define WM8994_WRITE_SEQUENCER_13 0x300D
+#define WM8994_WRITE_SEQUENCER_14 0x300E
+#define WM8994_WRITE_SEQUENCER_15 0x300F
+#define WM8994_WRITE_SEQUENCER_16 0x3010
+#define WM8994_WRITE_SEQUENCER_17 0x3011
+#define WM8994_WRITE_SEQUENCER_18 0x3012
+#define WM8994_WRITE_SEQUENCER_19 0x3013
+#define WM8994_WRITE_SEQUENCER_20 0x3014
+#define WM8994_WRITE_SEQUENCER_21 0x3015
+#define WM8994_WRITE_SEQUENCER_22 0x3016
+#define WM8994_WRITE_SEQUENCER_23 0x3017
+#define WM8994_WRITE_SEQUENCER_24 0x3018
+#define WM8994_WRITE_SEQUENCER_25 0x3019
+#define WM8994_WRITE_SEQUENCER_26 0x301A
+#define WM8994_WRITE_SEQUENCER_27 0x301B
+#define WM8994_WRITE_SEQUENCER_28 0x301C
+#define WM8994_WRITE_SEQUENCER_29 0x301D
+#define WM8994_WRITE_SEQUENCER_30 0x301E
+#define WM8994_WRITE_SEQUENCER_31 0x301F
+#define WM8994_WRITE_SEQUENCER_32 0x3020
+#define WM8994_WRITE_SEQUENCER_33 0x3021
+#define WM8994_WRITE_SEQUENCER_34 0x3022
+#define WM8994_WRITE_SEQUENCER_35 0x3023
+#define WM8994_WRITE_SEQUENCER_36 0x3024
+#define WM8994_WRITE_SEQUENCER_37 0x3025
+#define WM8994_WRITE_SEQUENCER_38 0x3026
+#define WM8994_WRITE_SEQUENCER_39 0x3027
+#define WM8994_WRITE_SEQUENCER_40 0x3028
+#define WM8994_WRITE_SEQUENCER_41 0x3029
+#define WM8994_WRITE_SEQUENCER_42 0x302A
+#define WM8994_WRITE_SEQUENCER_43 0x302B
+#define WM8994_WRITE_SEQUENCER_44 0x302C
+#define WM8994_WRITE_SEQUENCER_45 0x302D
+#define WM8994_WRITE_SEQUENCER_46 0x302E
+#define WM8994_WRITE_SEQUENCER_47 0x302F
+#define WM8994_WRITE_SEQUENCER_48 0x3030
+#define WM8994_WRITE_SEQUENCER_49 0x3031
+#define WM8994_WRITE_SEQUENCER_50 0x3032
+#define WM8994_WRITE_SEQUENCER_51 0x3033
+#define WM8994_WRITE_SEQUENCER_52 0x3034
+#define WM8994_WRITE_SEQUENCER_53 0x3035
+#define WM8994_WRITE_SEQUENCER_54 0x3036
+#define WM8994_WRITE_SEQUENCER_55 0x3037
+#define WM8994_WRITE_SEQUENCER_56 0x3038
+#define WM8994_WRITE_SEQUENCER_57 0x3039
+#define WM8994_WRITE_SEQUENCER_58 0x303A
+#define WM8994_WRITE_SEQUENCER_59 0x303B
+#define WM8994_WRITE_SEQUENCER_60 0x303C
+#define WM8994_WRITE_SEQUENCER_61 0x303D
+#define WM8994_WRITE_SEQUENCER_62 0x303E
+#define WM8994_WRITE_SEQUENCER_63 0x303F
+#define WM8994_WRITE_SEQUENCER_64 0x3040
+#define WM8994_WRITE_SEQUENCER_65 0x3041
+#define WM8994_WRITE_SEQUENCER_66 0x3042
+#define WM8994_WRITE_SEQUENCER_67 0x3043
+#define WM8994_WRITE_SEQUENCER_68 0x3044
+#define WM8994_WRITE_SEQUENCER_69 0x3045
+#define WM8994_WRITE_SEQUENCER_70 0x3046
+#define WM8994_WRITE_SEQUENCER_71 0x3047
+#define WM8994_WRITE_SEQUENCER_72 0x3048
+#define WM8994_WRITE_SEQUENCER_73 0x3049
+#define WM8994_WRITE_SEQUENCER_74 0x304A
+#define WM8994_WRITE_SEQUENCER_75 0x304B
+#define WM8994_WRITE_SEQUENCER_76 0x304C
+#define WM8994_WRITE_SEQUENCER_77 0x304D
+#define WM8994_WRITE_SEQUENCER_78 0x304E
+#define WM8994_WRITE_SEQUENCER_79 0x304F
+#define WM8994_WRITE_SEQUENCER_80 0x3050
+#define WM8994_WRITE_SEQUENCER_81 0x3051
+#define WM8994_WRITE_SEQUENCER_82 0x3052
+#define WM8994_WRITE_SEQUENCER_83 0x3053
+#define WM8994_WRITE_SEQUENCER_84 0x3054
+#define WM8994_WRITE_SEQUENCER_85 0x3055
+#define WM8994_WRITE_SEQUENCER_86 0x3056
+#define WM8994_WRITE_SEQUENCER_87 0x3057
+#define WM8994_WRITE_SEQUENCER_88 0x3058
+#define WM8994_WRITE_SEQUENCER_89 0x3059
+#define WM8994_WRITE_SEQUENCER_90 0x305A
+#define WM8994_WRITE_SEQUENCER_91 0x305B
+#define WM8994_WRITE_SEQUENCER_92 0x305C
+#define WM8994_WRITE_SEQUENCER_93 0x305D
+#define WM8994_WRITE_SEQUENCER_94 0x305E
+#define WM8994_WRITE_SEQUENCER_95 0x305F
+#define WM8994_WRITE_SEQUENCER_96 0x3060
+#define WM8994_WRITE_SEQUENCER_97 0x3061
+#define WM8994_WRITE_SEQUENCER_98 0x3062
+#define WM8994_WRITE_SEQUENCER_99 0x3063
+#define WM8994_WRITE_SEQUENCER_100 0x3064
+#define WM8994_WRITE_SEQUENCER_101 0x3065
+#define WM8994_WRITE_SEQUENCER_102 0x3066
+#define WM8994_WRITE_SEQUENCER_103 0x3067
+#define WM8994_WRITE_SEQUENCER_104 0x3068
+#define WM8994_WRITE_SEQUENCER_105 0x3069
+#define WM8994_WRITE_SEQUENCER_106 0x306A
+#define WM8994_WRITE_SEQUENCER_107 0x306B
+#define WM8994_WRITE_SEQUENCER_108 0x306C
+#define WM8994_WRITE_SEQUENCER_109 0x306D
+#define WM8994_WRITE_SEQUENCER_110 0x306E
+#define WM8994_WRITE_SEQUENCER_111 0x306F
+#define WM8994_WRITE_SEQUENCER_112 0x3070
+#define WM8994_WRITE_SEQUENCER_113 0x3071
+#define WM8994_WRITE_SEQUENCER_114 0x3072
+#define WM8994_WRITE_SEQUENCER_115 0x3073
+#define WM8994_WRITE_SEQUENCER_116 0x3074
+#define WM8994_WRITE_SEQUENCER_117 0x3075
+#define WM8994_WRITE_SEQUENCER_118 0x3076
+#define WM8994_WRITE_SEQUENCER_119 0x3077
+#define WM8994_WRITE_SEQUENCER_120 0x3078
+#define WM8994_WRITE_SEQUENCER_121 0x3079
+#define WM8994_WRITE_SEQUENCER_122 0x307A
+#define WM8994_WRITE_SEQUENCER_123 0x307B
+#define WM8994_WRITE_SEQUENCER_124 0x307C
+#define WM8994_WRITE_SEQUENCER_125 0x307D
+#define WM8994_WRITE_SEQUENCER_126 0x307E
+#define WM8994_WRITE_SEQUENCER_127 0x307F
+#define WM8994_WRITE_SEQUENCER_128 0x3080
+#define WM8994_WRITE_SEQUENCER_129 0x3081
+#define WM8994_WRITE_SEQUENCER_130 0x3082
+#define WM8994_WRITE_SEQUENCER_131 0x3083
+#define WM8994_WRITE_SEQUENCER_132 0x3084
+#define WM8994_WRITE_SEQUENCER_133 0x3085
+#define WM8994_WRITE_SEQUENCER_134 0x3086
+#define WM8994_WRITE_SEQUENCER_135 0x3087
+#define WM8994_WRITE_SEQUENCER_136 0x3088
+#define WM8994_WRITE_SEQUENCER_137 0x3089
+#define WM8994_WRITE_SEQUENCER_138 0x308A
+#define WM8994_WRITE_SEQUENCER_139 0x308B
+#define WM8994_WRITE_SEQUENCER_140 0x308C
+#define WM8994_WRITE_SEQUENCER_141 0x308D
+#define WM8994_WRITE_SEQUENCER_142 0x308E
+#define WM8994_WRITE_SEQUENCER_143 0x308F
+#define WM8994_WRITE_SEQUENCER_144 0x3090
+#define WM8994_WRITE_SEQUENCER_145 0x3091
+#define WM8994_WRITE_SEQUENCER_146 0x3092
+#define WM8994_WRITE_SEQUENCER_147 0x3093
+#define WM8994_WRITE_SEQUENCER_148 0x3094
+#define WM8994_WRITE_SEQUENCER_149 0x3095
+#define WM8994_WRITE_SEQUENCER_150 0x3096
+#define WM8994_WRITE_SEQUENCER_151 0x3097
+#define WM8994_WRITE_SEQUENCER_152 0x3098
+#define WM8994_WRITE_SEQUENCER_153 0x3099
+#define WM8994_WRITE_SEQUENCER_154 0x309A
+#define WM8994_WRITE_SEQUENCER_155 0x309B
+#define WM8994_WRITE_SEQUENCER_156 0x309C
+#define WM8994_WRITE_SEQUENCER_157 0x309D
+#define WM8994_WRITE_SEQUENCER_158 0x309E
+#define WM8994_WRITE_SEQUENCER_159 0x309F
+#define WM8994_WRITE_SEQUENCER_160 0x30A0
+#define WM8994_WRITE_SEQUENCER_161 0x30A1
+#define WM8994_WRITE_SEQUENCER_162 0x30A2
+#define WM8994_WRITE_SEQUENCER_163 0x30A3
+#define WM8994_WRITE_SEQUENCER_164 0x30A4
+#define WM8994_WRITE_SEQUENCER_165 0x30A5
+#define WM8994_WRITE_SEQUENCER_166 0x30A6
+#define WM8994_WRITE_SEQUENCER_167 0x30A7
+#define WM8994_WRITE_SEQUENCER_168 0x30A8
+#define WM8994_WRITE_SEQUENCER_169 0x30A9
+#define WM8994_WRITE_SEQUENCER_170 0x30AA
+#define WM8994_WRITE_SEQUENCER_171 0x30AB
+#define WM8994_WRITE_SEQUENCER_172 0x30AC
+#define WM8994_WRITE_SEQUENCER_173 0x30AD
+#define WM8994_WRITE_SEQUENCER_174 0x30AE
+#define WM8994_WRITE_SEQUENCER_175 0x30AF
+#define WM8994_WRITE_SEQUENCER_176 0x30B0
+#define WM8994_WRITE_SEQUENCER_177 0x30B1
+#define WM8994_WRITE_SEQUENCER_178 0x30B2
+#define WM8994_WRITE_SEQUENCER_179 0x30B3
+#define WM8994_WRITE_SEQUENCER_180 0x30B4
+#define WM8994_WRITE_SEQUENCER_181 0x30B5
+#define WM8994_WRITE_SEQUENCER_182 0x30B6
+#define WM8994_WRITE_SEQUENCER_183 0x30B7
+#define WM8994_WRITE_SEQUENCER_184 0x30B8
+#define WM8994_WRITE_SEQUENCER_185 0x30B9
+#define WM8994_WRITE_SEQUENCER_186 0x30BA
+#define WM8994_WRITE_SEQUENCER_187 0x30BB
+#define WM8994_WRITE_SEQUENCER_188 0x30BC
+#define WM8994_WRITE_SEQUENCER_189 0x30BD
+#define WM8994_WRITE_SEQUENCER_190 0x30BE
+#define WM8994_WRITE_SEQUENCER_191 0x30BF
+#define WM8994_WRITE_SEQUENCER_192 0x30C0
+#define WM8994_WRITE_SEQUENCER_193 0x30C1
+#define WM8994_WRITE_SEQUENCER_194 0x30C2
+#define WM8994_WRITE_SEQUENCER_195 0x30C3
+#define WM8994_WRITE_SEQUENCER_196 0x30C4
+#define WM8994_WRITE_SEQUENCER_197 0x30C5
+#define WM8994_WRITE_SEQUENCER_198 0x30C6
+#define WM8994_WRITE_SEQUENCER_199 0x30C7
+#define WM8994_WRITE_SEQUENCER_200 0x30C8
+#define WM8994_WRITE_SEQUENCER_201 0x30C9
+#define WM8994_WRITE_SEQUENCER_202 0x30CA
+#define WM8994_WRITE_SEQUENCER_203 0x30CB
+#define WM8994_WRITE_SEQUENCER_204 0x30CC
+#define WM8994_WRITE_SEQUENCER_205 0x30CD
+#define WM8994_WRITE_SEQUENCER_206 0x30CE
+#define WM8994_WRITE_SEQUENCER_207 0x30CF
+#define WM8994_WRITE_SEQUENCER_208 0x30D0
+#define WM8994_WRITE_SEQUENCER_209 0x30D1
+#define WM8994_WRITE_SEQUENCER_210 0x30D2
+#define WM8994_WRITE_SEQUENCER_211 0x30D3
+#define WM8994_WRITE_SEQUENCER_212 0x30D4
+#define WM8994_WRITE_SEQUENCER_213 0x30D5
+#define WM8994_WRITE_SEQUENCER_214 0x30D6
+#define WM8994_WRITE_SEQUENCER_215 0x30D7
+#define WM8994_WRITE_SEQUENCER_216 0x30D8
+#define WM8994_WRITE_SEQUENCER_217 0x30D9
+#define WM8994_WRITE_SEQUENCER_218 0x30DA
+#define WM8994_WRITE_SEQUENCER_219 0x30DB
+#define WM8994_WRITE_SEQUENCER_220 0x30DC
+#define WM8994_WRITE_SEQUENCER_221 0x30DD
+#define WM8994_WRITE_SEQUENCER_222 0x30DE
+#define WM8994_WRITE_SEQUENCER_223 0x30DF
+#define WM8994_WRITE_SEQUENCER_224 0x30E0
+#define WM8994_WRITE_SEQUENCER_225 0x30E1
+#define WM8994_WRITE_SEQUENCER_226 0x30E2
+#define WM8994_WRITE_SEQUENCER_227 0x30E3
+#define WM8994_WRITE_SEQUENCER_228 0x30E4
+#define WM8994_WRITE_SEQUENCER_229 0x30E5
+#define WM8994_WRITE_SEQUENCER_230 0x30E6
+#define WM8994_WRITE_SEQUENCER_231 0x30E7
+#define WM8994_WRITE_SEQUENCER_232 0x30E8
+#define WM8994_WRITE_SEQUENCER_233 0x30E9
+#define WM8994_WRITE_SEQUENCER_234 0x30EA
+#define WM8994_WRITE_SEQUENCER_235 0x30EB
+#define WM8994_WRITE_SEQUENCER_236 0x30EC
+#define WM8994_WRITE_SEQUENCER_237 0x30ED
+#define WM8994_WRITE_SEQUENCER_238 0x30EE
+#define WM8994_WRITE_SEQUENCER_239 0x30EF
+#define WM8994_WRITE_SEQUENCER_240 0x30F0
+#define WM8994_WRITE_SEQUENCER_241 0x30F1
+#define WM8994_WRITE_SEQUENCER_242 0x30F2
+#define WM8994_WRITE_SEQUENCER_243 0x30F3
+#define WM8994_WRITE_SEQUENCER_244 0x30F4
+#define WM8994_WRITE_SEQUENCER_245 0x30F5
+#define WM8994_WRITE_SEQUENCER_246 0x30F6
+#define WM8994_WRITE_SEQUENCER_247 0x30F7
+#define WM8994_WRITE_SEQUENCER_248 0x30F8
+#define WM8994_WRITE_SEQUENCER_249 0x30F9
+#define WM8994_WRITE_SEQUENCER_250 0x30FA
+#define WM8994_WRITE_SEQUENCER_251 0x30FB
+#define WM8994_WRITE_SEQUENCER_252 0x30FC
+#define WM8994_WRITE_SEQUENCER_253 0x30FD
+#define WM8994_WRITE_SEQUENCER_254 0x30FE
+#define WM8994_WRITE_SEQUENCER_255 0x30FF
+#define WM8994_WRITE_SEQUENCER_256 0x3100
+#define WM8994_WRITE_SEQUENCER_257 0x3101
+#define WM8994_WRITE_SEQUENCER_258 0x3102
+#define WM8994_WRITE_SEQUENCER_259 0x3103
+#define WM8994_WRITE_SEQUENCER_260 0x3104
+#define WM8994_WRITE_SEQUENCER_261 0x3105
+#define WM8994_WRITE_SEQUENCER_262 0x3106
+#define WM8994_WRITE_SEQUENCER_263 0x3107
+#define WM8994_WRITE_SEQUENCER_264 0x3108
+#define WM8994_WRITE_SEQUENCER_265 0x3109
+#define WM8994_WRITE_SEQUENCER_266 0x310A
+#define WM8994_WRITE_SEQUENCER_267 0x310B
+#define WM8994_WRITE_SEQUENCER_268 0x310C
+#define WM8994_WRITE_SEQUENCER_269 0x310D
+#define WM8994_WRITE_SEQUENCER_270 0x310E
+#define WM8994_WRITE_SEQUENCER_271 0x310F
+#define WM8994_WRITE_SEQUENCER_272 0x3110
+#define WM8994_WRITE_SEQUENCER_273 0x3111
+#define WM8994_WRITE_SEQUENCER_274 0x3112
+#define WM8994_WRITE_SEQUENCER_275 0x3113
+#define WM8994_WRITE_SEQUENCER_276 0x3114
+#define WM8994_WRITE_SEQUENCER_277 0x3115
+#define WM8994_WRITE_SEQUENCER_278 0x3116
+#define WM8994_WRITE_SEQUENCER_279 0x3117
+#define WM8994_WRITE_SEQUENCER_280 0x3118
+#define WM8994_WRITE_SEQUENCER_281 0x3119
+#define WM8994_WRITE_SEQUENCER_282 0x311A
+#define WM8994_WRITE_SEQUENCER_283 0x311B
+#define WM8994_WRITE_SEQUENCER_284 0x311C
+#define WM8994_WRITE_SEQUENCER_285 0x311D
+#define WM8994_WRITE_SEQUENCER_286 0x311E
+#define WM8994_WRITE_SEQUENCER_287 0x311F
+#define WM8994_WRITE_SEQUENCER_288 0x3120
+#define WM8994_WRITE_SEQUENCER_289 0x3121
+#define WM8994_WRITE_SEQUENCER_290 0x3122
+#define WM8994_WRITE_SEQUENCER_291 0x3123
+#define WM8994_WRITE_SEQUENCER_292 0x3124
+#define WM8994_WRITE_SEQUENCER_293 0x3125
+#define WM8994_WRITE_SEQUENCER_294 0x3126
+#define WM8994_WRITE_SEQUENCER_295 0x3127
+#define WM8994_WRITE_SEQUENCER_296 0x3128
+#define WM8994_WRITE_SEQUENCER_297 0x3129
+#define WM8994_WRITE_SEQUENCER_298 0x312A
+#define WM8994_WRITE_SEQUENCER_299 0x312B
+#define WM8994_WRITE_SEQUENCER_300 0x312C
+#define WM8994_WRITE_SEQUENCER_301 0x312D
+#define WM8994_WRITE_SEQUENCER_302 0x312E
+#define WM8994_WRITE_SEQUENCER_303 0x312F
+#define WM8994_WRITE_SEQUENCER_304 0x3130
+#define WM8994_WRITE_SEQUENCER_305 0x3131
+#define WM8994_WRITE_SEQUENCER_306 0x3132
+#define WM8994_WRITE_SEQUENCER_307 0x3133
+#define WM8994_WRITE_SEQUENCER_308 0x3134
+#define WM8994_WRITE_SEQUENCER_309 0x3135
+#define WM8994_WRITE_SEQUENCER_310 0x3136
+#define WM8994_WRITE_SEQUENCER_311 0x3137
+#define WM8994_WRITE_SEQUENCER_312 0x3138
+#define WM8994_WRITE_SEQUENCER_313 0x3139
+#define WM8994_WRITE_SEQUENCER_314 0x313A
+#define WM8994_WRITE_SEQUENCER_315 0x313B
+#define WM8994_WRITE_SEQUENCER_316 0x313C
+#define WM8994_WRITE_SEQUENCER_317 0x313D
+#define WM8994_WRITE_SEQUENCER_318 0x313E
+#define WM8994_WRITE_SEQUENCER_319 0x313F
+#define WM8994_WRITE_SEQUENCER_320 0x3140
+#define WM8994_WRITE_SEQUENCER_321 0x3141
+#define WM8994_WRITE_SEQUENCER_322 0x3142
+#define WM8994_WRITE_SEQUENCER_323 0x3143
+#define WM8994_WRITE_SEQUENCER_324 0x3144
+#define WM8994_WRITE_SEQUENCER_325 0x3145
+#define WM8994_WRITE_SEQUENCER_326 0x3146
+#define WM8994_WRITE_SEQUENCER_327 0x3147
+#define WM8994_WRITE_SEQUENCER_328 0x3148
+#define WM8994_WRITE_SEQUENCER_329 0x3149
+#define WM8994_WRITE_SEQUENCER_330 0x314A
+#define WM8994_WRITE_SEQUENCER_331 0x314B
+#define WM8994_WRITE_SEQUENCER_332 0x314C
+#define WM8994_WRITE_SEQUENCER_333 0x314D
+#define WM8994_WRITE_SEQUENCER_334 0x314E
+#define WM8994_WRITE_SEQUENCER_335 0x314F
+#define WM8994_WRITE_SEQUENCER_336 0x3150
+#define WM8994_WRITE_SEQUENCER_337 0x3151
+#define WM8994_WRITE_SEQUENCER_338 0x3152
+#define WM8994_WRITE_SEQUENCER_339 0x3153
+#define WM8994_WRITE_SEQUENCER_340 0x3154
+#define WM8994_WRITE_SEQUENCER_341 0x3155
+#define WM8994_WRITE_SEQUENCER_342 0x3156
+#define WM8994_WRITE_SEQUENCER_343 0x3157
+#define WM8994_WRITE_SEQUENCER_344 0x3158
+#define WM8994_WRITE_SEQUENCER_345 0x3159
+#define WM8994_WRITE_SEQUENCER_346 0x315A
+#define WM8994_WRITE_SEQUENCER_347 0x315B
+#define WM8994_WRITE_SEQUENCER_348 0x315C
+#define WM8994_WRITE_SEQUENCER_349 0x315D
+#define WM8994_WRITE_SEQUENCER_350 0x315E
+#define WM8994_WRITE_SEQUENCER_351 0x315F
+#define WM8994_WRITE_SEQUENCER_352 0x3160
+#define WM8994_WRITE_SEQUENCER_353 0x3161
+#define WM8994_WRITE_SEQUENCER_354 0x3162
+#define WM8994_WRITE_SEQUENCER_355 0x3163
+#define WM8994_WRITE_SEQUENCER_356 0x3164
+#define WM8994_WRITE_SEQUENCER_357 0x3165
+#define WM8994_WRITE_SEQUENCER_358 0x3166
+#define WM8994_WRITE_SEQUENCER_359 0x3167
+#define WM8994_WRITE_SEQUENCER_360 0x3168
+#define WM8994_WRITE_SEQUENCER_361 0x3169
+#define WM8994_WRITE_SEQUENCER_362 0x316A
+#define WM8994_WRITE_SEQUENCER_363 0x316B
+#define WM8994_WRITE_SEQUENCER_364 0x316C
+#define WM8994_WRITE_SEQUENCER_365 0x316D
+#define WM8994_WRITE_SEQUENCER_366 0x316E
+#define WM8994_WRITE_SEQUENCER_367 0x316F
+#define WM8994_WRITE_SEQUENCER_368 0x3170
+#define WM8994_WRITE_SEQUENCER_369 0x3171
+#define WM8994_WRITE_SEQUENCER_370 0x3172
+#define WM8994_WRITE_SEQUENCER_371 0x3173
+#define WM8994_WRITE_SEQUENCER_372 0x3174
+#define WM8994_WRITE_SEQUENCER_373 0x3175
+#define WM8994_WRITE_SEQUENCER_374 0x3176
+#define WM8994_WRITE_SEQUENCER_375 0x3177
+#define WM8994_WRITE_SEQUENCER_376 0x3178
+#define WM8994_WRITE_SEQUENCER_377 0x3179
+#define WM8994_WRITE_SEQUENCER_378 0x317A
+#define WM8994_WRITE_SEQUENCER_379 0x317B
+#define WM8994_WRITE_SEQUENCER_380 0x317C
+#define WM8994_WRITE_SEQUENCER_381 0x317D
+#define WM8994_WRITE_SEQUENCER_382 0x317E
+#define WM8994_WRITE_SEQUENCER_383 0x317F
+#define WM8994_WRITE_SEQUENCER_384 0x3180
+#define WM8994_WRITE_SEQUENCER_385 0x3181
+#define WM8994_WRITE_SEQUENCER_386 0x3182
+#define WM8994_WRITE_SEQUENCER_387 0x3183
+#define WM8994_WRITE_SEQUENCER_388 0x3184
+#define WM8994_WRITE_SEQUENCER_389 0x3185
+#define WM8994_WRITE_SEQUENCER_390 0x3186
+#define WM8994_WRITE_SEQUENCER_391 0x3187
+#define WM8994_WRITE_SEQUENCER_392 0x3188
+#define WM8994_WRITE_SEQUENCER_393 0x3189
+#define WM8994_WRITE_SEQUENCER_394 0x318A
+#define WM8994_WRITE_SEQUENCER_395 0x318B
+#define WM8994_WRITE_SEQUENCER_396 0x318C
+#define WM8994_WRITE_SEQUENCER_397 0x318D
+#define WM8994_WRITE_SEQUENCER_398 0x318E
+#define WM8994_WRITE_SEQUENCER_399 0x318F
+#define WM8994_WRITE_SEQUENCER_400 0x3190
+#define WM8994_WRITE_SEQUENCER_401 0x3191
+#define WM8994_WRITE_SEQUENCER_402 0x3192
+#define WM8994_WRITE_SEQUENCER_403 0x3193
+#define WM8994_WRITE_SEQUENCER_404 0x3194
+#define WM8994_WRITE_SEQUENCER_405 0x3195
+#define WM8994_WRITE_SEQUENCER_406 0x3196
+#define WM8994_WRITE_SEQUENCER_407 0x3197
+#define WM8994_WRITE_SEQUENCER_408 0x3198
+#define WM8994_WRITE_SEQUENCER_409 0x3199
+#define WM8994_WRITE_SEQUENCER_410 0x319A
+#define WM8994_WRITE_SEQUENCER_411 0x319B
+#define WM8994_WRITE_SEQUENCER_412 0x319C
+#define WM8994_WRITE_SEQUENCER_413 0x319D
+#define WM8994_WRITE_SEQUENCER_414 0x319E
+#define WM8994_WRITE_SEQUENCER_415 0x319F
+#define WM8994_WRITE_SEQUENCER_416 0x31A0
+#define WM8994_WRITE_SEQUENCER_417 0x31A1
+#define WM8994_WRITE_SEQUENCER_418 0x31A2
+#define WM8994_WRITE_SEQUENCER_419 0x31A3
+#define WM8994_WRITE_SEQUENCER_420 0x31A4
+#define WM8994_WRITE_SEQUENCER_421 0x31A5
+#define WM8994_WRITE_SEQUENCER_422 0x31A6
+#define WM8994_WRITE_SEQUENCER_423 0x31A7
+#define WM8994_WRITE_SEQUENCER_424 0x31A8
+#define WM8994_WRITE_SEQUENCER_425 0x31A9
+#define WM8994_WRITE_SEQUENCER_426 0x31AA
+#define WM8994_WRITE_SEQUENCER_427 0x31AB
+#define WM8994_WRITE_SEQUENCER_428 0x31AC
+#define WM8994_WRITE_SEQUENCER_429 0x31AD
+#define WM8994_WRITE_SEQUENCER_430 0x31AE
+#define WM8994_WRITE_SEQUENCER_431 0x31AF
+#define WM8994_WRITE_SEQUENCER_432 0x31B0
+#define WM8994_WRITE_SEQUENCER_433 0x31B1
+#define WM8994_WRITE_SEQUENCER_434 0x31B2
+#define WM8994_WRITE_SEQUENCER_435 0x31B3
+#define WM8994_WRITE_SEQUENCER_436 0x31B4
+#define WM8994_WRITE_SEQUENCER_437 0x31B5
+#define WM8994_WRITE_SEQUENCER_438 0x31B6
+#define WM8994_WRITE_SEQUENCER_439 0x31B7
+#define WM8994_WRITE_SEQUENCER_440 0x31B8
+#define WM8994_WRITE_SEQUENCER_441 0x31B9
+#define WM8994_WRITE_SEQUENCER_442 0x31BA
+#define WM8994_WRITE_SEQUENCER_443 0x31BB
+#define WM8994_WRITE_SEQUENCER_444 0x31BC
+#define WM8994_WRITE_SEQUENCER_445 0x31BD
+#define WM8994_WRITE_SEQUENCER_446 0x31BE
+#define WM8994_WRITE_SEQUENCER_447 0x31BF
+#define WM8994_WRITE_SEQUENCER_448 0x31C0
+#define WM8994_WRITE_SEQUENCER_449 0x31C1
+#define WM8994_WRITE_SEQUENCER_450 0x31C2
+#define WM8994_WRITE_SEQUENCER_451 0x31C3
+#define WM8994_WRITE_SEQUENCER_452 0x31C4
+#define WM8994_WRITE_SEQUENCER_453 0x31C5
+#define WM8994_WRITE_SEQUENCER_454 0x31C6
+#define WM8994_WRITE_SEQUENCER_455 0x31C7
+#define WM8994_WRITE_SEQUENCER_456 0x31C8
+#define WM8994_WRITE_SEQUENCER_457 0x31C9
+#define WM8994_WRITE_SEQUENCER_458 0x31CA
+#define WM8994_WRITE_SEQUENCER_459 0x31CB
+#define WM8994_WRITE_SEQUENCER_460 0x31CC
+#define WM8994_WRITE_SEQUENCER_461 0x31CD
+#define WM8994_WRITE_SEQUENCER_462 0x31CE
+#define WM8994_WRITE_SEQUENCER_463 0x31CF
+#define WM8994_WRITE_SEQUENCER_464 0x31D0
+#define WM8994_WRITE_SEQUENCER_465 0x31D1
+#define WM8994_WRITE_SEQUENCER_466 0x31D2
+#define WM8994_WRITE_SEQUENCER_467 0x31D3
+#define WM8994_WRITE_SEQUENCER_468 0x31D4
+#define WM8994_WRITE_SEQUENCER_469 0x31D5
+#define WM8994_WRITE_SEQUENCER_470 0x31D6
+#define WM8994_WRITE_SEQUENCER_471 0x31D7
+#define WM8994_WRITE_SEQUENCER_472 0x31D8
+#define WM8994_WRITE_SEQUENCER_473 0x31D9
+#define WM8994_WRITE_SEQUENCER_474 0x31DA
+#define WM8994_WRITE_SEQUENCER_475 0x31DB
+#define WM8994_WRITE_SEQUENCER_476 0x31DC
+#define WM8994_WRITE_SEQUENCER_477 0x31DD
+#define WM8994_WRITE_SEQUENCER_478 0x31DE
+#define WM8994_WRITE_SEQUENCER_479 0x31DF
+#define WM8994_WRITE_SEQUENCER_480 0x31E0
+#define WM8994_WRITE_SEQUENCER_481 0x31E1
+#define WM8994_WRITE_SEQUENCER_482 0x31E2
+#define WM8994_WRITE_SEQUENCER_483 0x31E3
+#define WM8994_WRITE_SEQUENCER_484 0x31E4
+#define WM8994_WRITE_SEQUENCER_485 0x31E5
+#define WM8994_WRITE_SEQUENCER_486 0x31E6
+#define WM8994_WRITE_SEQUENCER_487 0x31E7
+#define WM8994_WRITE_SEQUENCER_488 0x31E8
+#define WM8994_WRITE_SEQUENCER_489 0x31E9
+#define WM8994_WRITE_SEQUENCER_490 0x31EA
+#define WM8994_WRITE_SEQUENCER_491 0x31EB
+#define WM8994_WRITE_SEQUENCER_492 0x31EC
+#define WM8994_WRITE_SEQUENCER_493 0x31ED
+#define WM8994_WRITE_SEQUENCER_494 0x31EE
+#define WM8994_WRITE_SEQUENCER_495 0x31EF
+#define WM8994_WRITE_SEQUENCER_496 0x31F0
+#define WM8994_WRITE_SEQUENCER_497 0x31F1
+#define WM8994_WRITE_SEQUENCER_498 0x31F2
+#define WM8994_WRITE_SEQUENCER_499 0x31F3
+#define WM8994_WRITE_SEQUENCER_500 0x31F4
+#define WM8994_WRITE_SEQUENCER_501 0x31F5
+#define WM8994_WRITE_SEQUENCER_502 0x31F6
+#define WM8994_WRITE_SEQUENCER_503 0x31F7
+#define WM8994_WRITE_SEQUENCER_504 0x31F8
+#define WM8994_WRITE_SEQUENCER_505 0x31F9
+#define WM8994_WRITE_SEQUENCER_506 0x31FA
+#define WM8994_WRITE_SEQUENCER_507 0x31FB
+#define WM8994_WRITE_SEQUENCER_508 0x31FC
+#define WM8994_WRITE_SEQUENCER_509 0x31FD
+#define WM8994_WRITE_SEQUENCER_510 0x31FE
+#define WM8994_WRITE_SEQUENCER_511 0x31FF
+
+#define WM8994_REGISTER_COUNT 736
+#define WM8994_MAX_REGISTER 0x31FF
+#define WM8994_MAX_CACHED_REGISTER 0x749
+
+/*
+ * Field Definitions.
+ */
+
+/*
+ * R0 (0x00) - Software Reset
+ */
+#define WM8994_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */
+#define WM8994_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */
+#define WM8994_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */
+
+/*
+ * R1 (0x01) - Power Management (1)
+ */
+#define WM8994_SPKOUTR_ENA 0x2000 /* SPKOUTR_ENA */
+#define WM8994_SPKOUTR_ENA_MASK 0x2000 /* SPKOUTR_ENA */
+#define WM8994_SPKOUTR_ENA_SHIFT 13 /* SPKOUTR_ENA */
+#define WM8994_SPKOUTR_ENA_WIDTH 1 /* SPKOUTR_ENA */
+#define WM8994_SPKOUTL_ENA 0x1000 /* SPKOUTL_ENA */
+#define WM8994_SPKOUTL_ENA_MASK 0x1000 /* SPKOUTL_ENA */
+#define WM8994_SPKOUTL_ENA_SHIFT 12 /* SPKOUTL_ENA */
+#define WM8994_SPKOUTL_ENA_WIDTH 1 /* SPKOUTL_ENA */
+#define WM8994_HPOUT2_ENA 0x0800 /* HPOUT2_ENA */
+#define WM8994_HPOUT2_ENA_MASK 0x0800 /* HPOUT2_ENA */
+#define WM8994_HPOUT2_ENA_SHIFT 11 /* HPOUT2_ENA */
+#define WM8994_HPOUT2_ENA_WIDTH 1 /* HPOUT2_ENA */
+#define WM8994_HPOUT1L_ENA 0x0200 /* HPOUT1L_ENA */
+#define WM8994_HPOUT1L_ENA_MASK 0x0200 /* HPOUT1L_ENA */
+#define WM8994_HPOUT1L_ENA_SHIFT 9 /* HPOUT1L_ENA */
+#define WM8994_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */
+#define WM8994_HPOUT1R_ENA 0x0100 /* HPOUT1R_ENA */
+#define WM8994_HPOUT1R_ENA_MASK 0x0100 /* HPOUT1R_ENA */
+#define WM8994_HPOUT1R_ENA_SHIFT 8 /* HPOUT1R_ENA */
+#define WM8994_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */
+#define WM8994_MICB2_ENA 0x0020 /* MICB2_ENA */
+#define WM8994_MICB2_ENA_MASK 0x0020 /* MICB2_ENA */
+#define WM8994_MICB2_ENA_SHIFT 5 /* MICB2_ENA */
+#define WM8994_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
+#define WM8994_MICB1_ENA 0x0010 /* MICB1_ENA */
+#define WM8994_MICB1_ENA_MASK 0x0010 /* MICB1_ENA */
+#define WM8994_MICB1_ENA_SHIFT 4 /* MICB1_ENA */
+#define WM8994_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
+#define WM8994_VMID_SEL_MASK 0x0006 /* VMID_SEL - [2:1] */
+#define WM8994_VMID_SEL_SHIFT 1 /* VMID_SEL - [2:1] */
+#define WM8994_VMID_SEL_WIDTH 2 /* VMID_SEL - [2:1] */
+#define WM8994_BIAS_ENA 0x0001 /* BIAS_ENA */
+#define WM8994_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */
+#define WM8994_BIAS_ENA_SHIFT 0 /* BIAS_ENA */
+#define WM8994_BIAS_ENA_WIDTH 1 /* BIAS_ENA */
+
+/*
+ * R2 (0x02) - Power Management (2)
+ */
+#define WM8994_TSHUT_ENA 0x4000 /* TSHUT_ENA */
+#define WM8994_TSHUT_ENA_MASK 0x4000 /* TSHUT_ENA */
+#define WM8994_TSHUT_ENA_SHIFT 14 /* TSHUT_ENA */
+#define WM8994_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */
+#define WM8994_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */
+#define WM8994_TSHUT_OPDIS_MASK 0x2000 /* TSHUT_OPDIS */
+#define WM8994_TSHUT_OPDIS_SHIFT 13 /* TSHUT_OPDIS */
+#define WM8994_TSHUT_OPDIS_WIDTH 1 /* TSHUT_OPDIS */
+#define WM8994_OPCLK_ENA 0x0800 /* OPCLK_ENA */
+#define WM8994_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */
+#define WM8994_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */
+#define WM8994_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
+#define WM8994_MIXINL_ENA 0x0200 /* MIXINL_ENA */
+#define WM8994_MIXINL_ENA_MASK 0x0200 /* MIXINL_ENA */
+#define WM8994_MIXINL_ENA_SHIFT 9 /* MIXINL_ENA */
+#define WM8994_MIXINL_ENA_WIDTH 1 /* MIXINL_ENA */
+#define WM8994_MIXINR_ENA 0x0100 /* MIXINR_ENA */
+#define WM8994_MIXINR_ENA_MASK 0x0100 /* MIXINR_ENA */
+#define WM8994_MIXINR_ENA_SHIFT 8 /* MIXINR_ENA */
+#define WM8994_MIXINR_ENA_WIDTH 1 /* MIXINR_ENA */
+#define WM8994_IN2L_ENA 0x0080 /* IN2L_ENA */
+#define WM8994_IN2L_ENA_MASK 0x0080 /* IN2L_ENA */
+#define WM8994_IN2L_ENA_SHIFT 7 /* IN2L_ENA */
+#define WM8994_IN2L_ENA_WIDTH 1 /* IN2L_ENA */
+#define WM8994_IN1L_ENA 0x0040 /* IN1L_ENA */
+#define WM8994_IN1L_ENA_MASK 0x0040 /* IN1L_ENA */
+#define WM8994_IN1L_ENA_SHIFT 6 /* IN1L_ENA */
+#define WM8994_IN1L_ENA_WIDTH 1 /* IN1L_ENA */
+#define WM8994_IN2R_ENA 0x0020 /* IN2R_ENA */
+#define WM8994_IN2R_ENA_MASK 0x0020 /* IN2R_ENA */
+#define WM8994_IN2R_ENA_SHIFT 5 /* IN2R_ENA */
+#define WM8994_IN2R_ENA_WIDTH 1 /* IN2R_ENA */
+#define WM8994_IN1R_ENA 0x0010 /* IN1R_ENA */
+#define WM8994_IN1R_ENA_MASK 0x0010 /* IN1R_ENA */
+#define WM8994_IN1R_ENA_SHIFT 4 /* IN1R_ENA */
+#define WM8994_IN1R_ENA_WIDTH 1 /* IN1R_ENA */
+
+/*
+ * R3 (0x03) - Power Management (3)
+ */
+#define WM8994_LINEOUT1N_ENA 0x2000 /* LINEOUT1N_ENA */
+#define WM8994_LINEOUT1N_ENA_MASK 0x2000 /* LINEOUT1N_ENA */
+#define WM8994_LINEOUT1N_ENA_SHIFT 13 /* LINEOUT1N_ENA */
+#define WM8994_LINEOUT1N_ENA_WIDTH 1 /* LINEOUT1N_ENA */
+#define WM8994_LINEOUT1P_ENA 0x1000 /* LINEOUT1P_ENA */
+#define WM8994_LINEOUT1P_ENA_MASK 0x1000 /* LINEOUT1P_ENA */
+#define WM8994_LINEOUT1P_ENA_SHIFT 12 /* LINEOUT1P_ENA */
+#define WM8994_LINEOUT1P_ENA_WIDTH 1 /* LINEOUT1P_ENA */
+#define WM8994_LINEOUT2N_ENA 0x0800 /* LINEOUT2N_ENA */
+#define WM8994_LINEOUT2N_ENA_MASK 0x0800 /* LINEOUT2N_ENA */
+#define WM8994_LINEOUT2N_ENA_SHIFT 11 /* LINEOUT2N_ENA */
+#define WM8994_LINEOUT2N_ENA_WIDTH 1 /* LINEOUT2N_ENA */
+#define WM8994_LINEOUT2P_ENA 0x0400 /* LINEOUT2P_ENA */
+#define WM8994_LINEOUT2P_ENA_MASK 0x0400 /* LINEOUT2P_ENA */
+#define WM8994_LINEOUT2P_ENA_SHIFT 10 /* LINEOUT2P_ENA */
+#define WM8994_LINEOUT2P_ENA_WIDTH 1 /* LINEOUT2P_ENA */
+#define WM8994_SPKRVOL_ENA 0x0200 /* SPKRVOL_ENA */
+#define WM8994_SPKRVOL_ENA_MASK 0x0200 /* SPKRVOL_ENA */
+#define WM8994_SPKRVOL_ENA_SHIFT 9 /* SPKRVOL_ENA */
+#define WM8994_SPKRVOL_ENA_WIDTH 1 /* SPKRVOL_ENA */
+#define WM8994_SPKLVOL_ENA 0x0100 /* SPKLVOL_ENA */
+#define WM8994_SPKLVOL_ENA_MASK 0x0100 /* SPKLVOL_ENA */
+#define WM8994_SPKLVOL_ENA_SHIFT 8 /* SPKLVOL_ENA */
+#define WM8994_SPKLVOL_ENA_WIDTH 1 /* SPKLVOL_ENA */
+#define WM8994_MIXOUTLVOL_ENA 0x0080 /* MIXOUTLVOL_ENA */
+#define WM8994_MIXOUTLVOL_ENA_MASK 0x0080 /* MIXOUTLVOL_ENA */
+#define WM8994_MIXOUTLVOL_ENA_SHIFT 7 /* MIXOUTLVOL_ENA */
+#define WM8994_MIXOUTLVOL_ENA_WIDTH 1 /* MIXOUTLVOL_ENA */
+#define WM8994_MIXOUTRVOL_ENA 0x0040 /* MIXOUTRVOL_ENA */
+#define WM8994_MIXOUTRVOL_ENA_MASK 0x0040 /* MIXOUTRVOL_ENA */
+#define WM8994_MIXOUTRVOL_ENA_SHIFT 6 /* MIXOUTRVOL_ENA */
+#define WM8994_MIXOUTRVOL_ENA_WIDTH 1 /* MIXOUTRVOL_ENA */
+#define WM8994_MIXOUTL_ENA 0x0020 /* MIXOUTL_ENA */
+#define WM8994_MIXOUTL_ENA_MASK 0x0020 /* MIXOUTL_ENA */
+#define WM8994_MIXOUTL_ENA_SHIFT 5 /* MIXOUTL_ENA */
+#define WM8994_MIXOUTL_ENA_WIDTH 1 /* MIXOUTL_ENA */
+#define WM8994_MIXOUTR_ENA 0x0010 /* MIXOUTR_ENA */
+#define WM8994_MIXOUTR_ENA_MASK 0x0010 /* MIXOUTR_ENA */
+#define WM8994_MIXOUTR_ENA_SHIFT 4 /* MIXOUTR_ENA */
+#define WM8994_MIXOUTR_ENA_WIDTH 1 /* MIXOUTR_ENA */
+
+/*
+ * R4 (0x04) - Power Management (4)
+ */
+#define WM8994_AIF2ADCL_ENA 0x2000 /* AIF2ADCL_ENA */
+#define WM8994_AIF2ADCL_ENA_MASK 0x2000 /* AIF2ADCL_ENA */
+#define WM8994_AIF2ADCL_ENA_SHIFT 13 /* AIF2ADCL_ENA */
+#define WM8994_AIF2ADCL_ENA_WIDTH 1 /* AIF2ADCL_ENA */
+#define WM8994_AIF2ADCR_ENA 0x1000 /* AIF2ADCR_ENA */
+#define WM8994_AIF2ADCR_ENA_MASK 0x1000 /* AIF2ADCR_ENA */
+#define WM8994_AIF2ADCR_ENA_SHIFT 12 /* AIF2ADCR_ENA */
+#define WM8994_AIF2ADCR_ENA_WIDTH 1 /* AIF2ADCR_ENA */
+#define WM8994_AIF1ADC2L_ENA 0x0800 /* AIF1ADC2L_ENA */
+#define WM8994_AIF1ADC2L_ENA_MASK 0x0800 /* AIF1ADC2L_ENA */
+#define WM8994_AIF1ADC2L_ENA_SHIFT 11 /* AIF1ADC2L_ENA */
+#define WM8994_AIF1ADC2L_ENA_WIDTH 1 /* AIF1ADC2L_ENA */
+#define WM8994_AIF1ADC2R_ENA 0x0400 /* AIF1ADC2R_ENA */
+#define WM8994_AIF1ADC2R_ENA_MASK 0x0400 /* AIF1ADC2R_ENA */
+#define WM8994_AIF1ADC2R_ENA_SHIFT 10 /* AIF1ADC2R_ENA */
+#define WM8994_AIF1ADC2R_ENA_WIDTH 1 /* AIF1ADC2R_ENA */
+#define WM8994_AIF1ADC1L_ENA 0x0200 /* AIF1ADC1L_ENA */
+#define WM8994_AIF1ADC1L_ENA_MASK 0x0200 /* AIF1ADC1L_ENA */
+#define WM8994_AIF1ADC1L_ENA_SHIFT 9 /* AIF1ADC1L_ENA */
+#define WM8994_AIF1ADC1L_ENA_WIDTH 1 /* AIF1ADC1L_ENA */
+#define WM8994_AIF1ADC1R_ENA 0x0100 /* AIF1ADC1R_ENA */
+#define WM8994_AIF1ADC1R_ENA_MASK 0x0100 /* AIF1ADC1R_ENA */
+#define WM8994_AIF1ADC1R_ENA_SHIFT 8 /* AIF1ADC1R_ENA */
+#define WM8994_AIF1ADC1R_ENA_WIDTH 1 /* AIF1ADC1R_ENA */
+#define WM8994_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */
+#define WM8994_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */
+#define WM8994_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */
+#define WM8994_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */
+#define WM8994_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */
+#define WM8994_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */
+#define WM8994_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */
+#define WM8994_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */
+#define WM8994_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */
+#define WM8994_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */
+#define WM8994_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */
+#define WM8994_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */
+#define WM8994_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */
+#define WM8994_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */
+#define WM8994_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */
+#define WM8994_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */
+#define WM8994_ADCL_ENA 0x0002 /* ADCL_ENA */
+#define WM8994_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */
+#define WM8994_ADCL_ENA_SHIFT 1 /* ADCL_ENA */
+#define WM8994_ADCL_ENA_WIDTH 1 /* ADCL_ENA */
+#define WM8994_ADCR_ENA 0x0001 /* ADCR_ENA */
+#define WM8994_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
+#define WM8994_ADCR_ENA_SHIFT 0 /* ADCR_ENA */
+#define WM8994_ADCR_ENA_WIDTH 1 /* ADCR_ENA */
+
+/*
+ * R5 (0x05) - Power Management (5)
+ */
+#define WM8994_AIF2DACL_ENA 0x2000 /* AIF2DACL_ENA */
+#define WM8994_AIF2DACL_ENA_MASK 0x2000 /* AIF2DACL_ENA */
+#define WM8994_AIF2DACL_ENA_SHIFT 13 /* AIF2DACL_ENA */
+#define WM8994_AIF2DACL_ENA_WIDTH 1 /* AIF2DACL_ENA */
+#define WM8994_AIF2DACR_ENA 0x1000 /* AIF2DACR_ENA */
+#define WM8994_AIF2DACR_ENA_MASK 0x1000 /* AIF2DACR_ENA */
+#define WM8994_AIF2DACR_ENA_SHIFT 12 /* AIF2DACR_ENA */
+#define WM8994_AIF2DACR_ENA_WIDTH 1 /* AIF2DACR_ENA */
+#define WM8994_AIF1DAC2L_ENA 0x0800 /* AIF1DAC2L_ENA */
+#define WM8994_AIF1DAC2L_ENA_MASK 0x0800 /* AIF1DAC2L_ENA */
+#define WM8994_AIF1DAC2L_ENA_SHIFT 11 /* AIF1DAC2L_ENA */
+#define WM8994_AIF1DAC2L_ENA_WIDTH 1 /* AIF1DAC2L_ENA */
+#define WM8994_AIF1DAC2R_ENA 0x0400 /* AIF1DAC2R_ENA */
+#define WM8994_AIF1DAC2R_ENA_MASK 0x0400 /* AIF1DAC2R_ENA */
+#define WM8994_AIF1DAC2R_ENA_SHIFT 10 /* AIF1DAC2R_ENA */
+#define WM8994_AIF1DAC2R_ENA_WIDTH 1 /* AIF1DAC2R_ENA */
+#define WM8994_AIF1DAC1L_ENA 0x0200 /* AIF1DAC1L_ENA */
+#define WM8994_AIF1DAC1L_ENA_MASK 0x0200 /* AIF1DAC1L_ENA */
+#define WM8994_AIF1DAC1L_ENA_SHIFT 9 /* AIF1DAC1L_ENA */
+#define WM8994_AIF1DAC1L_ENA_WIDTH 1 /* AIF1DAC1L_ENA */
+#define WM8994_AIF1DAC1R_ENA 0x0100 /* AIF1DAC1R_ENA */
+#define WM8994_AIF1DAC1R_ENA_MASK 0x0100 /* AIF1DAC1R_ENA */
+#define WM8994_AIF1DAC1R_ENA_SHIFT 8 /* AIF1DAC1R_ENA */
+#define WM8994_AIF1DAC1R_ENA_WIDTH 1 /* AIF1DAC1R_ENA */
+#define WM8994_DAC2L_ENA 0x0008 /* DAC2L_ENA */
+#define WM8994_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */
+#define WM8994_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */
+#define WM8994_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */
+#define WM8994_DAC2R_ENA 0x0004 /* DAC2R_ENA */
+#define WM8994_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */
+#define WM8994_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */
+#define WM8994_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */
+#define WM8994_DAC1L_ENA 0x0002 /* DAC1L_ENA */
+#define WM8994_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */
+#define WM8994_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */
+#define WM8994_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */
+#define WM8994_DAC1R_ENA 0x0001 /* DAC1R_ENA */
+#define WM8994_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */
+#define WM8994_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */
+#define WM8994_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */
+
+/*
+ * R6 (0x06) - Power Management (6)
+ */
+#define WM8994_AIF3_TRI 0x0020 /* AIF3_TRI */
+#define WM8994_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */
+#define WM8994_AIF3_TRI_SHIFT 5 /* AIF3_TRI */
+#define WM8994_AIF3_TRI_WIDTH 1 /* AIF3_TRI */
+#define WM8994_AIF3_ADCDAT_SRC_MASK 0x0018 /* AIF3_ADCDAT_SRC - [4:3] */
+#define WM8994_AIF3_ADCDAT_SRC_SHIFT 3 /* AIF3_ADCDAT_SRC - [4:3] */
+#define WM8994_AIF3_ADCDAT_SRC_WIDTH 2 /* AIF3_ADCDAT_SRC - [4:3] */
+#define WM8994_AIF2_ADCDAT_SRC 0x0004 /* AIF2_ADCDAT_SRC */
+#define WM8994_AIF2_ADCDAT_SRC_MASK 0x0004 /* AIF2_ADCDAT_SRC */
+#define WM8994_AIF2_ADCDAT_SRC_SHIFT 2 /* AIF2_ADCDAT_SRC */
+#define WM8994_AIF2_ADCDAT_SRC_WIDTH 1 /* AIF2_ADCDAT_SRC */
+#define WM8994_AIF2_DACDAT_SRC 0x0002 /* AIF2_DACDAT_SRC */
+#define WM8994_AIF2_DACDAT_SRC_MASK 0x0002 /* AIF2_DACDAT_SRC */
+#define WM8994_AIF2_DACDAT_SRC_SHIFT 1 /* AIF2_DACDAT_SRC */
+#define WM8994_AIF2_DACDAT_SRC_WIDTH 1 /* AIF2_DACDAT_SRC */
+#define WM8994_AIF1_DACDAT_SRC 0x0001 /* AIF1_DACDAT_SRC */
+#define WM8994_AIF1_DACDAT_SRC_MASK 0x0001 /* AIF1_DACDAT_SRC */
+#define WM8994_AIF1_DACDAT_SRC_SHIFT 0 /* AIF1_DACDAT_SRC */
+#define WM8994_AIF1_DACDAT_SRC_WIDTH 1 /* AIF1_DACDAT_SRC */
+
+/*
+ * R21 (0x15) - Input Mixer (1)
+ */
+#define WM8994_IN1RP_MIXINR_BOOST 0x0100 /* IN1RP_MIXINR_BOOST */
+#define WM8994_IN1RP_MIXINR_BOOST_MASK 0x0100 /* IN1RP_MIXINR_BOOST */
+#define WM8994_IN1RP_MIXINR_BOOST_SHIFT 8 /* IN1RP_MIXINR_BOOST */
+#define WM8994_IN1RP_MIXINR_BOOST_WIDTH 1 /* IN1RP_MIXINR_BOOST */
+#define WM8994_IN1LP_MIXINL_BOOST 0x0080 /* IN1LP_MIXINL_BOOST */
+#define WM8994_IN1LP_MIXINL_BOOST_MASK 0x0080 /* IN1LP_MIXINL_BOOST */
+#define WM8994_IN1LP_MIXINL_BOOST_SHIFT 7 /* IN1LP_MIXINL_BOOST */
+#define WM8994_IN1LP_MIXINL_BOOST_WIDTH 1 /* IN1LP_MIXINL_BOOST */
+#define WM8994_INPUTS_CLAMP 0x0040 /* INPUTS_CLAMP */
+#define WM8994_INPUTS_CLAMP_MASK 0x0040 /* INPUTS_CLAMP */
+#define WM8994_INPUTS_CLAMP_SHIFT 6 /* INPUTS_CLAMP */
+#define WM8994_INPUTS_CLAMP_WIDTH 1 /* INPUTS_CLAMP */
+
+/*
+ * R24 (0x18) - Left Line Input 1&2 Volume
+ */
+#define WM8994_IN1_VU 0x0100 /* IN1_VU */
+#define WM8994_IN1_VU_MASK 0x0100 /* IN1_VU */
+#define WM8994_IN1_VU_SHIFT 8 /* IN1_VU */
+#define WM8994_IN1_VU_WIDTH 1 /* IN1_VU */
+#define WM8994_IN1L_MUTE 0x0080 /* IN1L_MUTE */
+#define WM8994_IN1L_MUTE_MASK 0x0080 /* IN1L_MUTE */
+#define WM8994_IN1L_MUTE_SHIFT 7 /* IN1L_MUTE */
+#define WM8994_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */
+#define WM8994_IN1L_ZC 0x0040 /* IN1L_ZC */
+#define WM8994_IN1L_ZC_MASK 0x0040 /* IN1L_ZC */
+#define WM8994_IN1L_ZC_SHIFT 6 /* IN1L_ZC */
+#define WM8994_IN1L_ZC_WIDTH 1 /* IN1L_ZC */
+#define WM8994_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */
+#define WM8994_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */
+#define WM8994_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */
+
+/*
+ * R25 (0x19) - Left Line Input 3&4 Volume
+ */
+#define WM8994_IN2_VU 0x0100 /* IN2_VU */
+#define WM8994_IN2_VU_MASK 0x0100 /* IN2_VU */
+#define WM8994_IN2_VU_SHIFT 8 /* IN2_VU */
+#define WM8994_IN2_VU_WIDTH 1 /* IN2_VU */
+#define WM8994_IN2L_MUTE 0x0080 /* IN2L_MUTE */
+#define WM8994_IN2L_MUTE_MASK 0x0080 /* IN2L_MUTE */
+#define WM8994_IN2L_MUTE_SHIFT 7 /* IN2L_MUTE */
+#define WM8994_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */
+#define WM8994_IN2L_ZC 0x0040 /* IN2L_ZC */
+#define WM8994_IN2L_ZC_MASK 0x0040 /* IN2L_ZC */
+#define WM8994_IN2L_ZC_SHIFT 6 /* IN2L_ZC */
+#define WM8994_IN2L_ZC_WIDTH 1 /* IN2L_ZC */
+#define WM8994_IN2L_VOL_MASK 0x001F /* IN2L_VOL - [4:0] */
+#define WM8994_IN2L_VOL_SHIFT 0 /* IN2L_VOL - [4:0] */
+#define WM8994_IN2L_VOL_WIDTH 5 /* IN2L_VOL - [4:0] */
+
+/*
+ * R26 (0x1A) - Right Line Input 1&2 Volume
+ */
+#define WM8994_IN1_VU 0x0100 /* IN1_VU */
+#define WM8994_IN1_VU_MASK 0x0100 /* IN1_VU */
+#define WM8994_IN1_VU_SHIFT 8 /* IN1_VU */
+#define WM8994_IN1_VU_WIDTH 1 /* IN1_VU */
+#define WM8994_IN1R_MUTE 0x0080 /* IN1R_MUTE */
+#define WM8994_IN1R_MUTE_MASK 0x0080 /* IN1R_MUTE */
+#define WM8994_IN1R_MUTE_SHIFT 7 /* IN1R_MUTE */
+#define WM8994_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */
+#define WM8994_IN1R_ZC 0x0040 /* IN1R_ZC */
+#define WM8994_IN1R_ZC_MASK 0x0040 /* IN1R_ZC */
+#define WM8994_IN1R_ZC_SHIFT 6 /* IN1R_ZC */
+#define WM8994_IN1R_ZC_WIDTH 1 /* IN1R_ZC */
+#define WM8994_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */
+#define WM8994_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */
+#define WM8994_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */
+
+/*
+ * R27 (0x1B) - Right Line Input 3&4 Volume
+ */
+#define WM8994_IN2_VU 0x0100 /* IN2_VU */
+#define WM8994_IN2_VU_MASK 0x0100 /* IN2_VU */
+#define WM8994_IN2_VU_SHIFT 8 /* IN2_VU */
+#define WM8994_IN2_VU_WIDTH 1 /* IN2_VU */
+#define WM8994_IN2R_MUTE 0x0080 /* IN2R_MUTE */
+#define WM8994_IN2R_MUTE_MASK 0x0080 /* IN2R_MUTE */
+#define WM8994_IN2R_MUTE_SHIFT 7 /* IN2R_MUTE */
+#define WM8994_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */
+#define WM8994_IN2R_ZC 0x0040 /* IN2R_ZC */
+#define WM8994_IN2R_ZC_MASK 0x0040 /* IN2R_ZC */
+#define WM8994_IN2R_ZC_SHIFT 6 /* IN2R_ZC */
+#define WM8994_IN2R_ZC_WIDTH 1 /* IN2R_ZC */
+#define WM8994_IN2R_VOL_MASK 0x001F /* IN2R_VOL - [4:0] */
+#define WM8994_IN2R_VOL_SHIFT 0 /* IN2R_VOL - [4:0] */
+#define WM8994_IN2R_VOL_WIDTH 5 /* IN2R_VOL - [4:0] */
+
+/*
+ * R28 (0x1C) - Left Output Volume
+ */
+#define WM8994_HPOUT1_VU 0x0100 /* HPOUT1_VU */
+#define WM8994_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */
+#define WM8994_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */
+#define WM8994_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */
+#define WM8994_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */
+#define WM8994_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */
+#define WM8994_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */
+#define WM8994_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */
+#define WM8994_HPOUT1L_MUTE_N 0x0040 /* HPOUT1L_MUTE_N */
+#define WM8994_HPOUT1L_MUTE_N_MASK 0x0040 /* HPOUT1L_MUTE_N */
+#define WM8994_HPOUT1L_MUTE_N_SHIFT 6 /* HPOUT1L_MUTE_N */
+#define WM8994_HPOUT1L_MUTE_N_WIDTH 1 /* HPOUT1L_MUTE_N */
+#define WM8994_HPOUT1L_VOL_MASK 0x003F /* HPOUT1L_VOL - [5:0] */
+#define WM8994_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [5:0] */
+#define WM8994_HPOUT1L_VOL_WIDTH 6 /* HPOUT1L_VOL - [5:0] */
+
+/*
+ * R29 (0x1D) - Right Output Volume
+ */
+#define WM8994_HPOUT1_VU 0x0100 /* HPOUT1_VU */
+#define WM8994_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */
+#define WM8994_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */
+#define WM8994_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */
+#define WM8994_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */
+#define WM8994_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */
+#define WM8994_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */
+#define WM8994_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */
+#define WM8994_HPOUT1R_MUTE_N 0x0040 /* HPOUT1R_MUTE_N */
+#define WM8994_HPOUT1R_MUTE_N_MASK 0x0040 /* HPOUT1R_MUTE_N */
+#define WM8994_HPOUT1R_MUTE_N_SHIFT 6 /* HPOUT1R_MUTE_N */
+#define WM8994_HPOUT1R_MUTE_N_WIDTH 1 /* HPOUT1R_MUTE_N */
+#define WM8994_HPOUT1R_VOL_MASK 0x003F /* HPOUT1R_VOL - [5:0] */
+#define WM8994_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [5:0] */
+#define WM8994_HPOUT1R_VOL_WIDTH 6 /* HPOUT1R_VOL - [5:0] */
+
+/*
+ * R30 (0x1E) - Line Outputs Volume
+ */
+#define WM8994_LINEOUT1N_MUTE 0x0040 /* LINEOUT1N_MUTE */
+#define WM8994_LINEOUT1N_MUTE_MASK 0x0040 /* LINEOUT1N_MUTE */
+#define WM8994_LINEOUT1N_MUTE_SHIFT 6 /* LINEOUT1N_MUTE */
+#define WM8994_LINEOUT1N_MUTE_WIDTH 1 /* LINEOUT1N_MUTE */
+#define WM8994_LINEOUT1P_MUTE 0x0020 /* LINEOUT1P_MUTE */
+#define WM8994_LINEOUT1P_MUTE_MASK 0x0020 /* LINEOUT1P_MUTE */
+#define WM8994_LINEOUT1P_MUTE_SHIFT 5 /* LINEOUT1P_MUTE */
+#define WM8994_LINEOUT1P_MUTE_WIDTH 1 /* LINEOUT1P_MUTE */
+#define WM8994_LINEOUT1_VOL 0x0010 /* LINEOUT1_VOL */
+#define WM8994_LINEOUT1_VOL_MASK 0x0010 /* LINEOUT1_VOL */
+#define WM8994_LINEOUT1_VOL_SHIFT 4 /* LINEOUT1_VOL */
+#define WM8994_LINEOUT1_VOL_WIDTH 1 /* LINEOUT1_VOL */
+#define WM8994_LINEOUT2N_MUTE 0x0004 /* LINEOUT2N_MUTE */
+#define WM8994_LINEOUT2N_MUTE_MASK 0x0004 /* LINEOUT2N_MUTE */
+#define WM8994_LINEOUT2N_MUTE_SHIFT 2 /* LINEOUT2N_MUTE */
+#define WM8994_LINEOUT2N_MUTE_WIDTH 1 /* LINEOUT2N_MUTE */
+#define WM8994_LINEOUT2P_MUTE 0x0002 /* LINEOUT2P_MUTE */
+#define WM8994_LINEOUT2P_MUTE_MASK 0x0002 /* LINEOUT2P_MUTE */
+#define WM8994_LINEOUT2P_MUTE_SHIFT 1 /* LINEOUT2P_MUTE */
+#define WM8994_LINEOUT2P_MUTE_WIDTH 1 /* LINEOUT2P_MUTE */
+#define WM8994_LINEOUT2_VOL 0x0001 /* LINEOUT2_VOL */
+#define WM8994_LINEOUT2_VOL_MASK 0x0001 /* LINEOUT2_VOL */
+#define WM8994_LINEOUT2_VOL_SHIFT 0 /* LINEOUT2_VOL */
+#define WM8994_LINEOUT2_VOL_WIDTH 1 /* LINEOUT2_VOL */
+
+/*
+ * R31 (0x1F) - HPOUT2 Volume
+ */
+#define WM8994_HPOUT2_MUTE 0x0020 /* HPOUT2_MUTE */
+#define WM8994_HPOUT2_MUTE_MASK 0x0020 /* HPOUT2_MUTE */
+#define WM8994_HPOUT2_MUTE_SHIFT 5 /* HPOUT2_MUTE */
+#define WM8994_HPOUT2_MUTE_WIDTH 1 /* HPOUT2_MUTE */
+#define WM8994_HPOUT2_VOL 0x0010 /* HPOUT2_VOL */
+#define WM8994_HPOUT2_VOL_MASK 0x0010 /* HPOUT2_VOL */
+#define WM8994_HPOUT2_VOL_SHIFT 4 /* HPOUT2_VOL */
+#define WM8994_HPOUT2_VOL_WIDTH 1 /* HPOUT2_VOL */
+
+/*
+ * R32 (0x20) - Left OPGA Volume
+ */
+#define WM8994_MIXOUT_VU 0x0100 /* MIXOUT_VU */
+#define WM8994_MIXOUT_VU_MASK 0x0100 /* MIXOUT_VU */
+#define WM8994_MIXOUT_VU_SHIFT 8 /* MIXOUT_VU */
+#define WM8994_MIXOUT_VU_WIDTH 1 /* MIXOUT_VU */
+#define WM8994_MIXOUTL_ZC 0x0080 /* MIXOUTL_ZC */
+#define WM8994_MIXOUTL_ZC_MASK 0x0080 /* MIXOUTL_ZC */
+#define WM8994_MIXOUTL_ZC_SHIFT 7 /* MIXOUTL_ZC */
+#define WM8994_MIXOUTL_ZC_WIDTH 1 /* MIXOUTL_ZC */
+#define WM8994_MIXOUTL_MUTE_N 0x0040 /* MIXOUTL_MUTE_N */
+#define WM8994_MIXOUTL_MUTE_N_MASK 0x0040 /* MIXOUTL_MUTE_N */
+#define WM8994_MIXOUTL_MUTE_N_SHIFT 6 /* MIXOUTL_MUTE_N */
+#define WM8994_MIXOUTL_MUTE_N_WIDTH 1 /* MIXOUTL_MUTE_N */
+#define WM8994_MIXOUTL_VOL_MASK 0x003F /* MIXOUTL_VOL - [5:0] */
+#define WM8994_MIXOUTL_VOL_SHIFT 0 /* MIXOUTL_VOL - [5:0] */
+#define WM8994_MIXOUTL_VOL_WIDTH 6 /* MIXOUTL_VOL - [5:0] */
+
+/*
+ * R33 (0x21) - Right OPGA Volume
+ */
+#define WM8994_MIXOUT_VU 0x0100 /* MIXOUT_VU */
+#define WM8994_MIXOUT_VU_MASK 0x0100 /* MIXOUT_VU */
+#define WM8994_MIXOUT_VU_SHIFT 8 /* MIXOUT_VU */
+#define WM8994_MIXOUT_VU_WIDTH 1 /* MIXOUT_VU */
+#define WM8994_MIXOUTR_ZC 0x0080 /* MIXOUTR_ZC */
+#define WM8994_MIXOUTR_ZC_MASK 0x0080 /* MIXOUTR_ZC */
+#define WM8994_MIXOUTR_ZC_SHIFT 7 /* MIXOUTR_ZC */
+#define WM8994_MIXOUTR_ZC_WIDTH 1 /* MIXOUTR_ZC */
+#define WM8994_MIXOUTR_MUTE_N 0x0040 /* MIXOUTR_MUTE_N */
+#define WM8994_MIXOUTR_MUTE_N_MASK 0x0040 /* MIXOUTR_MUTE_N */
+#define WM8994_MIXOUTR_MUTE_N_SHIFT 6 /* MIXOUTR_MUTE_N */
+#define WM8994_MIXOUTR_MUTE_N_WIDTH 1 /* MIXOUTR_MUTE_N */
+#define WM8994_MIXOUTR_VOL_MASK 0x003F /* MIXOUTR_VOL - [5:0] */
+#define WM8994_MIXOUTR_VOL_SHIFT 0 /* MIXOUTR_VOL - [5:0] */
+#define WM8994_MIXOUTR_VOL_WIDTH 6 /* MIXOUTR_VOL - [5:0] */
+
+/*
+ * R34 (0x22) - SPKMIXL Attenuation
+ */
+#define WM8994_DAC2L_SPKMIXL_VOL 0x0040 /* DAC2L_SPKMIXL_VOL */
+#define WM8994_DAC2L_SPKMIXL_VOL_MASK 0x0040 /* DAC2L_SPKMIXL_VOL */
+#define WM8994_DAC2L_SPKMIXL_VOL_SHIFT 6 /* DAC2L_SPKMIXL_VOL */
+#define WM8994_DAC2L_SPKMIXL_VOL_WIDTH 1 /* DAC2L_SPKMIXL_VOL */
+#define WM8994_MIXINL_SPKMIXL_VOL 0x0020 /* MIXINL_SPKMIXL_VOL */
+#define WM8994_MIXINL_SPKMIXL_VOL_MASK 0x0020 /* MIXINL_SPKMIXL_VOL */
+#define WM8994_MIXINL_SPKMIXL_VOL_SHIFT 5 /* MIXINL_SPKMIXL_VOL */
+#define WM8994_MIXINL_SPKMIXL_VOL_WIDTH 1 /* MIXINL_SPKMIXL_VOL */
+#define WM8994_IN1LP_SPKMIXL_VOL 0x0010 /* IN1LP_SPKMIXL_VOL */
+#define WM8994_IN1LP_SPKMIXL_VOL_MASK 0x0010 /* IN1LP_SPKMIXL_VOL */
+#define WM8994_IN1LP_SPKMIXL_VOL_SHIFT 4 /* IN1LP_SPKMIXL_VOL */
+#define WM8994_IN1LP_SPKMIXL_VOL_WIDTH 1 /* IN1LP_SPKMIXL_VOL */
+#define WM8994_MIXOUTL_SPKMIXL_VOL 0x0008 /* MIXOUTL_SPKMIXL_VOL */
+#define WM8994_MIXOUTL_SPKMIXL_VOL_MASK 0x0008 /* MIXOUTL_SPKMIXL_VOL */
+#define WM8994_MIXOUTL_SPKMIXL_VOL_SHIFT 3 /* MIXOUTL_SPKMIXL_VOL */
+#define WM8994_MIXOUTL_SPKMIXL_VOL_WIDTH 1 /* MIXOUTL_SPKMIXL_VOL */
+#define WM8994_DAC1L_SPKMIXL_VOL 0x0004 /* DAC1L_SPKMIXL_VOL */
+#define WM8994_DAC1L_SPKMIXL_VOL_MASK 0x0004 /* DAC1L_SPKMIXL_VOL */
+#define WM8994_DAC1L_SPKMIXL_VOL_SHIFT 2 /* DAC1L_SPKMIXL_VOL */
+#define WM8994_DAC1L_SPKMIXL_VOL_WIDTH 1 /* DAC1L_SPKMIXL_VOL */
+#define WM8994_SPKMIXL_VOL_MASK 0x0003 /* SPKMIXL_VOL - [1:0] */
+#define WM8994_SPKMIXL_VOL_SHIFT 0 /* SPKMIXL_VOL - [1:0] */
+#define WM8994_SPKMIXL_VOL_WIDTH 2 /* SPKMIXL_VOL - [1:0] */
+
+/*
+ * R35 (0x23) - SPKMIXR Attenuation
+ */
+#define WM8994_SPKOUT_CLASSAB 0x0100 /* SPKOUT_CLASSAB */
+#define WM8994_SPKOUT_CLASSAB_MASK 0x0100 /* SPKOUT_CLASSAB */
+#define WM8994_SPKOUT_CLASSAB_SHIFT 8 /* SPKOUT_CLASSAB */
+#define WM8994_SPKOUT_CLASSAB_WIDTH 1 /* SPKOUT_CLASSAB */
+#define WM8994_DAC2R_SPKMIXR_VOL 0x0040 /* DAC2R_SPKMIXR_VOL */
+#define WM8994_DAC2R_SPKMIXR_VOL_MASK 0x0040 /* DAC2R_SPKMIXR_VOL */
+#define WM8994_DAC2R_SPKMIXR_VOL_SHIFT 6 /* DAC2R_SPKMIXR_VOL */
+#define WM8994_DAC2R_SPKMIXR_VOL_WIDTH 1 /* DAC2R_SPKMIXR_VOL */
+#define WM8994_MIXINR_SPKMIXR_VOL 0x0020 /* MIXINR_SPKMIXR_VOL */
+#define WM8994_MIXINR_SPKMIXR_VOL_MASK 0x0020 /* MIXINR_SPKMIXR_VOL */
+#define WM8994_MIXINR_SPKMIXR_VOL_SHIFT 5 /* MIXINR_SPKMIXR_VOL */
+#define WM8994_MIXINR_SPKMIXR_VOL_WIDTH 1 /* MIXINR_SPKMIXR_VOL */
+#define WM8994_IN1RP_SPKMIXR_VOL 0x0010 /* IN1RP_SPKMIXR_VOL */
+#define WM8994_IN1RP_SPKMIXR_VOL_MASK 0x0010 /* IN1RP_SPKMIXR_VOL */
+#define WM8994_IN1RP_SPKMIXR_VOL_SHIFT 4 /* IN1RP_SPKMIXR_VOL */
+#define WM8994_IN1RP_SPKMIXR_VOL_WIDTH 1 /* IN1RP_SPKMIXR_VOL */
+#define WM8994_MIXOUTR_SPKMIXR_VOL 0x0008 /* MIXOUTR_SPKMIXR_VOL */
+#define WM8994_MIXOUTR_SPKMIXR_VOL_MASK 0x0008 /* MIXOUTR_SPKMIXR_VOL */
+#define WM8994_MIXOUTR_SPKMIXR_VOL_SHIFT 3 /* MIXOUTR_SPKMIXR_VOL */
+#define WM8994_MIXOUTR_SPKMIXR_VOL_WIDTH 1 /* MIXOUTR_SPKMIXR_VOL */
+#define WM8994_DAC1R_SPKMIXR_VOL 0x0004 /* DAC1R_SPKMIXR_VOL */
+#define WM8994_DAC1R_SPKMIXR_VOL_MASK 0x0004 /* DAC1R_SPKMIXR_VOL */
+#define WM8994_DAC1R_SPKMIXR_VOL_SHIFT 2 /* DAC1R_SPKMIXR_VOL */
+#define WM8994_DAC1R_SPKMIXR_VOL_WIDTH 1 /* DAC1R_SPKMIXR_VOL */
+#define WM8994_SPKMIXR_VOL_MASK 0x0003 /* SPKMIXR_VOL - [1:0] */
+#define WM8994_SPKMIXR_VOL_SHIFT 0 /* SPKMIXR_VOL - [1:0] */
+#define WM8994_SPKMIXR_VOL_WIDTH 2 /* SPKMIXR_VOL - [1:0] */
+
+/*
+ * R36 (0x24) - SPKOUT Mixers
+ */
+#define WM8994_IN2LRP_TO_SPKOUTL 0x0020 /* IN2LRP_TO_SPKOUTL */
+#define WM8994_IN2LRP_TO_SPKOUTL_MASK 0x0020 /* IN2LRP_TO_SPKOUTL */
+#define WM8994_IN2LRP_TO_SPKOUTL_SHIFT 5 /* IN2LRP_TO_SPKOUTL */
+#define WM8994_IN2LRP_TO_SPKOUTL_WIDTH 1 /* IN2LRP_TO_SPKOUTL */
+#define WM8994_SPKMIXL_TO_SPKOUTL 0x0010 /* SPKMIXL_TO_SPKOUTL */
+#define WM8994_SPKMIXL_TO_SPKOUTL_MASK 0x0010 /* SPKMIXL_TO_SPKOUTL */
+#define WM8994_SPKMIXL_TO_SPKOUTL_SHIFT 4 /* SPKMIXL_TO_SPKOUTL */
+#define WM8994_SPKMIXL_TO_SPKOUTL_WIDTH 1 /* SPKMIXL_TO_SPKOUTL */
+#define WM8994_SPKMIXR_TO_SPKOUTL 0x0008 /* SPKMIXR_TO_SPKOUTL */
+#define WM8994_SPKMIXR_TO_SPKOUTL_MASK 0x0008 /* SPKMIXR_TO_SPKOUTL */
+#define WM8994_SPKMIXR_TO_SPKOUTL_SHIFT 3 /* SPKMIXR_TO_SPKOUTL */
+#define WM8994_SPKMIXR_TO_SPKOUTL_WIDTH 1 /* SPKMIXR_TO_SPKOUTL */
+#define WM8994_IN2LRP_TO_SPKOUTR 0x0004 /* IN2LRP_TO_SPKOUTR */
+#define WM8994_IN2LRP_TO_SPKOUTR_MASK 0x0004 /* IN2LRP_TO_SPKOUTR */
+#define WM8994_IN2LRP_TO_SPKOUTR_SHIFT 2 /* IN2LRP_TO_SPKOUTR */
+#define WM8994_IN2LRP_TO_SPKOUTR_WIDTH 1 /* IN2LRP_TO_SPKOUTR */
+#define WM8994_SPKMIXL_TO_SPKOUTR 0x0002 /* SPKMIXL_TO_SPKOUTR */
+#define WM8994_SPKMIXL_TO_SPKOUTR_MASK 0x0002 /* SPKMIXL_TO_SPKOUTR */
+#define WM8994_SPKMIXL_TO_SPKOUTR_SHIFT 1 /* SPKMIXL_TO_SPKOUTR */
+#define WM8994_SPKMIXL_TO_SPKOUTR_WIDTH 1 /* SPKMIXL_TO_SPKOUTR */
+#define WM8994_SPKMIXR_TO_SPKOUTR 0x0001 /* SPKMIXR_TO_SPKOUTR */
+#define WM8994_SPKMIXR_TO_SPKOUTR_MASK 0x0001 /* SPKMIXR_TO_SPKOUTR */
+#define WM8994_SPKMIXR_TO_SPKOUTR_SHIFT 0 /* SPKMIXR_TO_SPKOUTR */
+#define WM8994_SPKMIXR_TO_SPKOUTR_WIDTH 1 /* SPKMIXR_TO_SPKOUTR */
+
+/*
+ * R37 (0x25) - ClassD
+ */
+#define WM8994_SPKOUTL_BOOST_MASK 0x0038 /* SPKOUTL_BOOST - [5:3] */
+#define WM8994_SPKOUTL_BOOST_SHIFT 3 /* SPKOUTL_BOOST - [5:3] */
+#define WM8994_SPKOUTL_BOOST_WIDTH 3 /* SPKOUTL_BOOST - [5:3] */
+#define WM8994_SPKOUTR_BOOST_MASK 0x0007 /* SPKOUTR_BOOST - [2:0] */
+#define WM8994_SPKOUTR_BOOST_SHIFT 0 /* SPKOUTR_BOOST - [2:0] */
+#define WM8994_SPKOUTR_BOOST_WIDTH 3 /* SPKOUTR_BOOST - [2:0] */
+
+/*
+ * R38 (0x26) - Speaker Volume Left
+ */
+#define WM8994_SPKOUT_VU 0x0100 /* SPKOUT_VU */
+#define WM8994_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */
+#define WM8994_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */
+#define WM8994_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */
+#define WM8994_SPKOUTL_ZC 0x0080 /* SPKOUTL_ZC */
+#define WM8994_SPKOUTL_ZC_MASK 0x0080 /* SPKOUTL_ZC */
+#define WM8994_SPKOUTL_ZC_SHIFT 7 /* SPKOUTL_ZC */
+#define WM8994_SPKOUTL_ZC_WIDTH 1 /* SPKOUTL_ZC */
+#define WM8994_SPKOUTL_MUTE_N 0x0040 /* SPKOUTL_MUTE_N */
+#define WM8994_SPKOUTL_MUTE_N_MASK 0x0040 /* SPKOUTL_MUTE_N */
+#define WM8994_SPKOUTL_MUTE_N_SHIFT 6 /* SPKOUTL_MUTE_N */
+#define WM8994_SPKOUTL_MUTE_N_WIDTH 1 /* SPKOUTL_MUTE_N */
+#define WM8994_SPKOUTL_VOL_MASK 0x003F /* SPKOUTL_VOL - [5:0] */
+#define WM8994_SPKOUTL_VOL_SHIFT 0 /* SPKOUTL_VOL - [5:0] */
+#define WM8994_SPKOUTL_VOL_WIDTH 6 /* SPKOUTL_VOL - [5:0] */
+
+/*
+ * R39 (0x27) - Speaker Volume Right
+ */
+#define WM8994_SPKOUT_VU 0x0100 /* SPKOUT_VU */
+#define WM8994_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */
+#define WM8994_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */
+#define WM8994_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */
+#define WM8994_SPKOUTR_ZC 0x0080 /* SPKOUTR_ZC */
+#define WM8994_SPKOUTR_ZC_MASK 0x0080 /* SPKOUTR_ZC */
+#define WM8994_SPKOUTR_ZC_SHIFT 7 /* SPKOUTR_ZC */
+#define WM8994_SPKOUTR_ZC_WIDTH 1 /* SPKOUTR_ZC */
+#define WM8994_SPKOUTR_MUTE_N 0x0040 /* SPKOUTR_MUTE_N */
+#define WM8994_SPKOUTR_MUTE_N_MASK 0x0040 /* SPKOUTR_MUTE_N */
+#define WM8994_SPKOUTR_MUTE_N_SHIFT 6 /* SPKOUTR_MUTE_N */
+#define WM8994_SPKOUTR_MUTE_N_WIDTH 1 /* SPKOUTR_MUTE_N */
+#define WM8994_SPKOUTR_VOL_MASK 0x003F /* SPKOUTR_VOL - [5:0] */
+#define WM8994_SPKOUTR_VOL_SHIFT 0 /* SPKOUTR_VOL - [5:0] */
+#define WM8994_SPKOUTR_VOL_WIDTH 6 /* SPKOUTR_VOL - [5:0] */
+
+/*
+ * R40 (0x28) - Input Mixer (2)
+ */
+#define WM8994_IN2LP_TO_IN2L 0x0080 /* IN2LP_TO_IN2L */
+#define WM8994_IN2LP_TO_IN2L_MASK 0x0080 /* IN2LP_TO_IN2L */
+#define WM8994_IN2LP_TO_IN2L_SHIFT 7 /* IN2LP_TO_IN2L */
+#define WM8994_IN2LP_TO_IN2L_WIDTH 1 /* IN2LP_TO_IN2L */
+#define WM8994_IN2LN_TO_IN2L 0x0040 /* IN2LN_TO_IN2L */
+#define WM8994_IN2LN_TO_IN2L_MASK 0x0040 /* IN2LN_TO_IN2L */
+#define WM8994_IN2LN_TO_IN2L_SHIFT 6 /* IN2LN_TO_IN2L */
+#define WM8994_IN2LN_TO_IN2L_WIDTH 1 /* IN2LN_TO_IN2L */
+#define WM8994_IN1LP_TO_IN1L 0x0020 /* IN1LP_TO_IN1L */
+#define WM8994_IN1LP_TO_IN1L_MASK 0x0020 /* IN1LP_TO_IN1L */
+#define WM8994_IN1LP_TO_IN1L_SHIFT 5 /* IN1LP_TO_IN1L */
+#define WM8994_IN1LP_TO_IN1L_WIDTH 1 /* IN1LP_TO_IN1L */
+#define WM8994_IN1LN_TO_IN1L 0x0010 /* IN1LN_TO_IN1L */
+#define WM8994_IN1LN_TO_IN1L_MASK 0x0010 /* IN1LN_TO_IN1L */
+#define WM8994_IN1LN_TO_IN1L_SHIFT 4 /* IN1LN_TO_IN1L */
+#define WM8994_IN1LN_TO_IN1L_WIDTH 1 /* IN1LN_TO_IN1L */
+#define WM8994_IN2RP_TO_IN2R 0x0008 /* IN2RP_TO_IN2R */
+#define WM8994_IN2RP_TO_IN2R_MASK 0x0008 /* IN2RP_TO_IN2R */
+#define WM8994_IN2RP_TO_IN2R_SHIFT 3 /* IN2RP_TO_IN2R */
+#define WM8994_IN2RP_TO_IN2R_WIDTH 1 /* IN2RP_TO_IN2R */
+#define WM8994_IN2RN_TO_IN2R 0x0004 /* IN2RN_TO_IN2R */
+#define WM8994_IN2RN_TO_IN2R_MASK 0x0004 /* IN2RN_TO_IN2R */
+#define WM8994_IN2RN_TO_IN2R_SHIFT 2 /* IN2RN_TO_IN2R */
+#define WM8994_IN2RN_TO_IN2R_WIDTH 1 /* IN2RN_TO_IN2R */
+#define WM8994_IN1RP_TO_IN1R 0x0002 /* IN1RP_TO_IN1R */
+#define WM8994_IN1RP_TO_IN1R_MASK 0x0002 /* IN1RP_TO_IN1R */
+#define WM8994_IN1RP_TO_IN1R_SHIFT 1 /* IN1RP_TO_IN1R */
+#define WM8994_IN1RP_TO_IN1R_WIDTH 1 /* IN1RP_TO_IN1R */
+#define WM8994_IN1RN_TO_IN1R 0x0001 /* IN1RN_TO_IN1R */
+#define WM8994_IN1RN_TO_IN1R_MASK 0x0001 /* IN1RN_TO_IN1R */
+#define WM8994_IN1RN_TO_IN1R_SHIFT 0 /* IN1RN_TO_IN1R */
+#define WM8994_IN1RN_TO_IN1R_WIDTH 1 /* IN1RN_TO_IN1R */
+
+/*
+ * R41 (0x29) - Input Mixer (3)
+ */
+#define WM8994_IN2L_TO_MIXINL 0x0100 /* IN2L_TO_MIXINL */
+#define WM8994_IN2L_TO_MIXINL_MASK 0x0100 /* IN2L_TO_MIXINL */
+#define WM8994_IN2L_TO_MIXINL_SHIFT 8 /* IN2L_TO_MIXINL */
+#define WM8994_IN2L_TO_MIXINL_WIDTH 1 /* IN2L_TO_MIXINL */
+#define WM8994_IN2L_MIXINL_VOL 0x0080 /* IN2L_MIXINL_VOL */
+#define WM8994_IN2L_MIXINL_VOL_MASK 0x0080 /* IN2L_MIXINL_VOL */
+#define WM8994_IN2L_MIXINL_VOL_SHIFT 7 /* IN2L_MIXINL_VOL */
+#define WM8994_IN2L_MIXINL_VOL_WIDTH 1 /* IN2L_MIXINL_VOL */
+#define WM8994_IN1L_TO_MIXINL 0x0020 /* IN1L_TO_MIXINL */
+#define WM8994_IN1L_TO_MIXINL_MASK 0x0020 /* IN1L_TO_MIXINL */
+#define WM8994_IN1L_TO_MIXINL_SHIFT 5 /* IN1L_TO_MIXINL */
+#define WM8994_IN1L_TO_MIXINL_WIDTH 1 /* IN1L_TO_MIXINL */
+#define WM8994_IN1L_MIXINL_VOL 0x0010 /* IN1L_MIXINL_VOL */
+#define WM8994_IN1L_MIXINL_VOL_MASK 0x0010 /* IN1L_MIXINL_VOL */
+#define WM8994_IN1L_MIXINL_VOL_SHIFT 4 /* IN1L_MIXINL_VOL */
+#define WM8994_IN1L_MIXINL_VOL_WIDTH 1 /* IN1L_MIXINL_VOL */
+#define WM8994_MIXOUTL_MIXINL_VOL_MASK 0x0007 /* MIXOUTL_MIXINL_VOL - [2:0] */
+#define WM8994_MIXOUTL_MIXINL_VOL_SHIFT 0 /* MIXOUTL_MIXINL_VOL - [2:0] */
+#define WM8994_MIXOUTL_MIXINL_VOL_WIDTH 3 /* MIXOUTL_MIXINL_VOL - [2:0] */
+
+/*
+ * R42 (0x2A) - Input Mixer (4)
+ */
+#define WM8994_IN2R_TO_MIXINR 0x0100 /* IN2R_TO_MIXINR */
+#define WM8994_IN2R_TO_MIXINR_MASK 0x0100 /* IN2R_TO_MIXINR */
+#define WM8994_IN2R_TO_MIXINR_SHIFT 8 /* IN2R_TO_MIXINR */
+#define WM8994_IN2R_TO_MIXINR_WIDTH 1 /* IN2R_TO_MIXINR */
+#define WM8994_IN2R_MIXINR_VOL 0x0080 /* IN2R_MIXINR_VOL */
+#define WM8994_IN2R_MIXINR_VOL_MASK 0x0080 /* IN2R_MIXINR_VOL */
+#define WM8994_IN2R_MIXINR_VOL_SHIFT 7 /* IN2R_MIXINR_VOL */
+#define WM8994_IN2R_MIXINR_VOL_WIDTH 1 /* IN2R_MIXINR_VOL */
+#define WM8994_IN1R_TO_MIXINR 0x0020 /* IN1R_TO_MIXINR */
+#define WM8994_IN1R_TO_MIXINR_MASK 0x0020 /* IN1R_TO_MIXINR */
+#define WM8994_IN1R_TO_MIXINR_SHIFT 5 /* IN1R_TO_MIXINR */
+#define WM8994_IN1R_TO_MIXINR_WIDTH 1 /* IN1R_TO_MIXINR */
+#define WM8994_IN1R_MIXINR_VOL 0x0010 /* IN1R_MIXINR_VOL */
+#define WM8994_IN1R_MIXINR_VOL_MASK 0x0010 /* IN1R_MIXINR_VOL */
+#define WM8994_IN1R_MIXINR_VOL_SHIFT 4 /* IN1R_MIXINR_VOL */
+#define WM8994_IN1R_MIXINR_VOL_WIDTH 1 /* IN1R_MIXINR_VOL */
+#define WM8994_MIXOUTR_MIXINR_VOL_MASK 0x0007 /* MIXOUTR_MIXINR_VOL - [2:0] */
+#define WM8994_MIXOUTR_MIXINR_VOL_SHIFT 0 /* MIXOUTR_MIXINR_VOL - [2:0] */
+#define WM8994_MIXOUTR_MIXINR_VOL_WIDTH 3 /* MIXOUTR_MIXINR_VOL - [2:0] */
+
+/*
+ * R43 (0x2B) - Input Mixer (5)
+ */
+#define WM8994_IN1LP_MIXINL_VOL_MASK 0x01C0 /* IN1LP_MIXINL_VOL - [8:6] */
+#define WM8994_IN1LP_MIXINL_VOL_SHIFT 6 /* IN1LP_MIXINL_VOL - [8:6] */
+#define WM8994_IN1LP_MIXINL_VOL_WIDTH 3 /* IN1LP_MIXINL_VOL - [8:6] */
+#define WM8994_IN2LRP_MIXINL_VOL_MASK 0x0007 /* IN2LRP_MIXINL_VOL - [2:0] */
+#define WM8994_IN2LRP_MIXINL_VOL_SHIFT 0 /* IN2LRP_MIXINL_VOL - [2:0] */
+#define WM8994_IN2LRP_MIXINL_VOL_WIDTH 3 /* IN2LRP_MIXINL_VOL - [2:0] */
+
+/*
+ * R44 (0x2C) - Input Mixer (6)
+ */
+#define WM8994_IN1RP_MIXINR_VOL_MASK 0x01C0 /* IN1RP_MIXINR_VOL - [8:6] */
+#define WM8994_IN1RP_MIXINR_VOL_SHIFT 6 /* IN1RP_MIXINR_VOL - [8:6] */
+#define WM8994_IN1RP_MIXINR_VOL_WIDTH 3 /* IN1RP_MIXINR_VOL - [8:6] */
+#define WM8994_IN2LRP_MIXINR_VOL_MASK 0x0007 /* IN2LRP_MIXINR_VOL - [2:0] */
+#define WM8994_IN2LRP_MIXINR_VOL_SHIFT 0 /* IN2LRP_MIXINR_VOL - [2:0] */
+#define WM8994_IN2LRP_MIXINR_VOL_WIDTH 3 /* IN2LRP_MIXINR_VOL - [2:0] */
+
+/*
+ * R45 (0x2D) - Output Mixer (1)
+ */
+#define WM8994_DAC1L_TO_HPOUT1L 0x0100 /* DAC1L_TO_HPOUT1L */
+#define WM8994_DAC1L_TO_HPOUT1L_MASK 0x0100 /* DAC1L_TO_HPOUT1L */
+#define WM8994_DAC1L_TO_HPOUT1L_SHIFT 8 /* DAC1L_TO_HPOUT1L */
+#define WM8994_DAC1L_TO_HPOUT1L_WIDTH 1 /* DAC1L_TO_HPOUT1L */
+#define WM8994_MIXINR_TO_MIXOUTL 0x0080 /* MIXINR_TO_MIXOUTL */
+#define WM8994_MIXINR_TO_MIXOUTL_MASK 0x0080 /* MIXINR_TO_MIXOUTL */
+#define WM8994_MIXINR_TO_MIXOUTL_SHIFT 7 /* MIXINR_TO_MIXOUTL */
+#define WM8994_MIXINR_TO_MIXOUTL_WIDTH 1 /* MIXINR_TO_MIXOUTL */
+#define WM8994_MIXINL_TO_MIXOUTL 0x0040 /* MIXINL_TO_MIXOUTL */
+#define WM8994_MIXINL_TO_MIXOUTL_MASK 0x0040 /* MIXINL_TO_MIXOUTL */
+#define WM8994_MIXINL_TO_MIXOUTL_SHIFT 6 /* MIXINL_TO_MIXOUTL */
+#define WM8994_MIXINL_TO_MIXOUTL_WIDTH 1 /* MIXINL_TO_MIXOUTL */
+#define WM8994_IN2RN_TO_MIXOUTL 0x0020 /* IN2RN_TO_MIXOUTL */
+#define WM8994_IN2RN_TO_MIXOUTL_MASK 0x0020 /* IN2RN_TO_MIXOUTL */
+#define WM8994_IN2RN_TO_MIXOUTL_SHIFT 5 /* IN2RN_TO_MIXOUTL */
+#define WM8994_IN2RN_TO_MIXOUTL_WIDTH 1 /* IN2RN_TO_MIXOUTL */
+#define WM8994_IN2LN_TO_MIXOUTL 0x0010 /* IN2LN_TO_MIXOUTL */
+#define WM8994_IN2LN_TO_MIXOUTL_MASK 0x0010 /* IN2LN_TO_MIXOUTL */
+#define WM8994_IN2LN_TO_MIXOUTL_SHIFT 4 /* IN2LN_TO_MIXOUTL */
+#define WM8994_IN2LN_TO_MIXOUTL_WIDTH 1 /* IN2LN_TO_MIXOUTL */
+#define WM8994_IN1R_TO_MIXOUTL 0x0008 /* IN1R_TO_MIXOUTL */
+#define WM8994_IN1R_TO_MIXOUTL_MASK 0x0008 /* IN1R_TO_MIXOUTL */
+#define WM8994_IN1R_TO_MIXOUTL_SHIFT 3 /* IN1R_TO_MIXOUTL */
+#define WM8994_IN1R_TO_MIXOUTL_WIDTH 1 /* IN1R_TO_MIXOUTL */
+#define WM8994_IN1L_TO_MIXOUTL 0x0004 /* IN1L_TO_MIXOUTL */
+#define WM8994_IN1L_TO_MIXOUTL_MASK 0x0004 /* IN1L_TO_MIXOUTL */
+#define WM8994_IN1L_TO_MIXOUTL_SHIFT 2 /* IN1L_TO_MIXOUTL */
+#define WM8994_IN1L_TO_MIXOUTL_WIDTH 1 /* IN1L_TO_MIXOUTL */
+#define WM8994_IN2LP_TO_MIXOUTL 0x0002 /* IN2LP_TO_MIXOUTL */
+#define WM8994_IN2LP_TO_MIXOUTL_MASK 0x0002 /* IN2LP_TO_MIXOUTL */
+#define WM8994_IN2LP_TO_MIXOUTL_SHIFT 1 /* IN2LP_TO_MIXOUTL */
+#define WM8994_IN2LP_TO_MIXOUTL_WIDTH 1 /* IN2LP_TO_MIXOUTL */
+#define WM8994_DAC1L_TO_MIXOUTL 0x0001 /* DAC1L_TO_MIXOUTL */
+#define WM8994_DAC1L_TO_MIXOUTL_MASK 0x0001 /* DAC1L_TO_MIXOUTL */
+#define WM8994_DAC1L_TO_MIXOUTL_SHIFT 0 /* DAC1L_TO_MIXOUTL */
+#define WM8994_DAC1L_TO_MIXOUTL_WIDTH 1 /* DAC1L_TO_MIXOUTL */
+
+/*
+ * R46 (0x2E) - Output Mixer (2)
+ */
+#define WM8994_DAC1R_TO_HPOUT1R 0x0100 /* DAC1R_TO_HPOUT1R */
+#define WM8994_DAC1R_TO_HPOUT1R_MASK 0x0100 /* DAC1R_TO_HPOUT1R */
+#define WM8994_DAC1R_TO_HPOUT1R_SHIFT 8 /* DAC1R_TO_HPOUT1R */
+#define WM8994_DAC1R_TO_HPOUT1R_WIDTH 1 /* DAC1R_TO_HPOUT1R */
+#define WM8994_MIXINL_TO_MIXOUTR 0x0080 /* MIXINL_TO_MIXOUTR */
+#define WM8994_MIXINL_TO_MIXOUTR_MASK 0x0080 /* MIXINL_TO_MIXOUTR */
+#define WM8994_MIXINL_TO_MIXOUTR_SHIFT 7 /* MIXINL_TO_MIXOUTR */
+#define WM8994_MIXINL_TO_MIXOUTR_WIDTH 1 /* MIXINL_TO_MIXOUTR */
+#define WM8994_MIXINR_TO_MIXOUTR 0x0040 /* MIXINR_TO_MIXOUTR */
+#define WM8994_MIXINR_TO_MIXOUTR_MASK 0x0040 /* MIXINR_TO_MIXOUTR */
+#define WM8994_MIXINR_TO_MIXOUTR_SHIFT 6 /* MIXINR_TO_MIXOUTR */
+#define WM8994_MIXINR_TO_MIXOUTR_WIDTH 1 /* MIXINR_TO_MIXOUTR */
+#define WM8994_IN2LN_TO_MIXOUTR 0x0020 /* IN2LN_TO_MIXOUTR */
+#define WM8994_IN2LN_TO_MIXOUTR_MASK 0x0020 /* IN2LN_TO_MIXOUTR */
+#define WM8994_IN2LN_TO_MIXOUTR_SHIFT 5 /* IN2LN_TO_MIXOUTR */
+#define WM8994_IN2LN_TO_MIXOUTR_WIDTH 1 /* IN2LN_TO_MIXOUTR */
+#define WM8994_IN2RN_TO_MIXOUTR 0x0010 /* IN2RN_TO_MIXOUTR */
+#define WM8994_IN2RN_TO_MIXOUTR_MASK 0x0010 /* IN2RN_TO_MIXOUTR */
+#define WM8994_IN2RN_TO_MIXOUTR_SHIFT 4 /* IN2RN_TO_MIXOUTR */
+#define WM8994_IN2RN_TO_MIXOUTR_WIDTH 1 /* IN2RN_TO_MIXOUTR */
+#define WM8994_IN1L_TO_MIXOUTR 0x0008 /* IN1L_TO_MIXOUTR */
+#define WM8994_IN1L_TO_MIXOUTR_MASK 0x0008 /* IN1L_TO_MIXOUTR */
+#define WM8994_IN1L_TO_MIXOUTR_SHIFT 3 /* IN1L_TO_MIXOUTR */
+#define WM8994_IN1L_TO_MIXOUTR_WIDTH 1 /* IN1L_TO_MIXOUTR */
+#define WM8994_IN1R_TO_MIXOUTR 0x0004 /* IN1R_TO_MIXOUTR */
+#define WM8994_IN1R_TO_MIXOUTR_MASK 0x0004 /* IN1R_TO_MIXOUTR */
+#define WM8994_IN1R_TO_MIXOUTR_SHIFT 2 /* IN1R_TO_MIXOUTR */
+#define WM8994_IN1R_TO_MIXOUTR_WIDTH 1 /* IN1R_TO_MIXOUTR */
+#define WM8994_IN2RP_TO_MIXOUTR 0x0002 /* IN2RP_TO_MIXOUTR */
+#define WM8994_IN2RP_TO_MIXOUTR_MASK 0x0002 /* IN2RP_TO_MIXOUTR */
+#define WM8994_IN2RP_TO_MIXOUTR_SHIFT 1 /* IN2RP_TO_MIXOUTR */
+#define WM8994_IN2RP_TO_MIXOUTR_WIDTH 1 /* IN2RP_TO_MIXOUTR */
+#define WM8994_DAC1R_TO_MIXOUTR 0x0001 /* DAC1R_TO_MIXOUTR */
+#define WM8994_DAC1R_TO_MIXOUTR_MASK 0x0001 /* DAC1R_TO_MIXOUTR */
+#define WM8994_DAC1R_TO_MIXOUTR_SHIFT 0 /* DAC1R_TO_MIXOUTR */
+#define WM8994_DAC1R_TO_MIXOUTR_WIDTH 1 /* DAC1R_TO_MIXOUTR */
+
+/*
+ * R47 (0x2F) - Output Mixer (3)
+ */
+#define WM8994_IN2LP_MIXOUTL_VOL_MASK 0x0E00 /* IN2LP_MIXOUTL_VOL - [11:9] */
+#define WM8994_IN2LP_MIXOUTL_VOL_SHIFT 9 /* IN2LP_MIXOUTL_VOL - [11:9] */
+#define WM8994_IN2LP_MIXOUTL_VOL_WIDTH 3 /* IN2LP_MIXOUTL_VOL - [11:9] */
+#define WM8994_IN2LN_MIXOUTL_VOL_MASK 0x01C0 /* IN2LN_MIXOUTL_VOL - [8:6] */
+#define WM8994_IN2LN_MIXOUTL_VOL_SHIFT 6 /* IN2LN_MIXOUTL_VOL - [8:6] */
+#define WM8994_IN2LN_MIXOUTL_VOL_WIDTH 3 /* IN2LN_MIXOUTL_VOL - [8:6] */
+#define WM8994_IN1R_MIXOUTL_VOL_MASK 0x0038 /* IN1R_MIXOUTL_VOL - [5:3] */
+#define WM8994_IN1R_MIXOUTL_VOL_SHIFT 3 /* IN1R_MIXOUTL_VOL - [5:3] */
+#define WM8994_IN1R_MIXOUTL_VOL_WIDTH 3 /* IN1R_MIXOUTL_VOL - [5:3] */
+#define WM8994_IN1L_MIXOUTL_VOL_MASK 0x0007 /* IN1L_MIXOUTL_VOL - [2:0] */
+#define WM8994_IN1L_MIXOUTL_VOL_SHIFT 0 /* IN1L_MIXOUTL_VOL - [2:0] */
+#define WM8994_IN1L_MIXOUTL_VOL_WIDTH 3 /* IN1L_MIXOUTL_VOL - [2:0] */
+
+/*
+ * R48 (0x30) - Output Mixer (4)
+ */
+#define WM8994_IN2RP_MIXOUTR_VOL_MASK 0x0E00 /* IN2RP_MIXOUTR_VOL - [11:9] */
+#define WM8994_IN2RP_MIXOUTR_VOL_SHIFT 9 /* IN2RP_MIXOUTR_VOL - [11:9] */
+#define WM8994_IN2RP_MIXOUTR_VOL_WIDTH 3 /* IN2RP_MIXOUTR_VOL - [11:9] */
+#define WM8994_IN2RN_MIXOUTR_VOL_MASK 0x01C0 /* IN2RN_MIXOUTR_VOL - [8:6] */
+#define WM8994_IN2RN_MIXOUTR_VOL_SHIFT 6 /* IN2RN_MIXOUTR_VOL - [8:6] */
+#define WM8994_IN2RN_MIXOUTR_VOL_WIDTH 3 /* IN2RN_MIXOUTR_VOL - [8:6] */
+#define WM8994_IN1L_MIXOUTR_VOL_MASK 0x0038 /* IN1L_MIXOUTR_VOL - [5:3] */
+#define WM8994_IN1L_MIXOUTR_VOL_SHIFT 3 /* IN1L_MIXOUTR_VOL - [5:3] */
+#define WM8994_IN1L_MIXOUTR_VOL_WIDTH 3 /* IN1L_MIXOUTR_VOL - [5:3] */
+#define WM8994_IN1R_MIXOUTR_VOL_MASK 0x0007 /* IN1R_MIXOUTR_VOL - [2:0] */
+#define WM8994_IN1R_MIXOUTR_VOL_SHIFT 0 /* IN1R_MIXOUTR_VOL - [2:0] */
+#define WM8994_IN1R_MIXOUTR_VOL_WIDTH 3 /* IN1R_MIXOUTR_VOL - [2:0] */
+
+/*
+ * R49 (0x31) - Output Mixer (5)
+ */
+#define WM8994_DAC1L_MIXOUTL_VOL_MASK 0x0E00 /* DAC1L_MIXOUTL_VOL - [11:9] */
+#define WM8994_DAC1L_MIXOUTL_VOL_SHIFT 9 /* DAC1L_MIXOUTL_VOL - [11:9] */
+#define WM8994_DAC1L_MIXOUTL_VOL_WIDTH 3 /* DAC1L_MIXOUTL_VOL - [11:9] */
+#define WM8994_IN2RN_MIXOUTL_VOL_MASK 0x01C0 /* IN2RN_MIXOUTL_VOL - [8:6] */
+#define WM8994_IN2RN_MIXOUTL_VOL_SHIFT 6 /* IN2RN_MIXOUTL_VOL - [8:6] */
+#define WM8994_IN2RN_MIXOUTL_VOL_WIDTH 3 /* IN2RN_MIXOUTL_VOL - [8:6] */
+#define WM8994_MIXINR_MIXOUTL_VOL_MASK 0x0038 /* MIXINR_MIXOUTL_VOL - [5:3] */
+#define WM8994_MIXINR_MIXOUTL_VOL_SHIFT 3 /* MIXINR_MIXOUTL_VOL - [5:3] */
+#define WM8994_MIXINR_MIXOUTL_VOL_WIDTH 3 /* MIXINR_MIXOUTL_VOL - [5:3] */
+#define WM8994_MIXINL_MIXOUTL_VOL_MASK 0x0007 /* MIXINL_MIXOUTL_VOL - [2:0] */
+#define WM8994_MIXINL_MIXOUTL_VOL_SHIFT 0 /* MIXINL_MIXOUTL_VOL - [2:0] */
+#define WM8994_MIXINL_MIXOUTL_VOL_WIDTH 3 /* MIXINL_MIXOUTL_VOL - [2:0] */
+
+/*
+ * R50 (0x32) - Output Mixer (6)
+ */
+#define WM8994_DAC1R_MIXOUTR_VOL_MASK 0x0E00 /* DAC1R_MIXOUTR_VOL - [11:9] */
+#define WM8994_DAC1R_MIXOUTR_VOL_SHIFT 9 /* DAC1R_MIXOUTR_VOL - [11:9] */
+#define WM8994_DAC1R_MIXOUTR_VOL_WIDTH 3 /* DAC1R_MIXOUTR_VOL - [11:9] */
+#define WM8994_IN2LN_MIXOUTR_VOL_MASK 0x01C0 /* IN2LN_MIXOUTR_VOL - [8:6] */
+#define WM8994_IN2LN_MIXOUTR_VOL_SHIFT 6 /* IN2LN_MIXOUTR_VOL - [8:6] */
+#define WM8994_IN2LN_MIXOUTR_VOL_WIDTH 3 /* IN2LN_MIXOUTR_VOL - [8:6] */
+#define WM8994_MIXINL_MIXOUTR_VOL_MASK 0x0038 /* MIXINL_MIXOUTR_VOL - [5:3] */
+#define WM8994_MIXINL_MIXOUTR_VOL_SHIFT 3 /* MIXINL_MIXOUTR_VOL - [5:3] */
+#define WM8994_MIXINL_MIXOUTR_VOL_WIDTH 3 /* MIXINL_MIXOUTR_VOL - [5:3] */
+#define WM8994_MIXINR_MIXOUTR_VOL_MASK 0x0007 /* MIXINR_MIXOUTR_VOL - [2:0] */
+#define WM8994_MIXINR_MIXOUTR_VOL_SHIFT 0 /* MIXINR_MIXOUTR_VOL - [2:0] */
+#define WM8994_MIXINR_MIXOUTR_VOL_WIDTH 3 /* MIXINR_MIXOUTR_VOL - [2:0] */
+
+/*
+ * R51 (0x33) - HPOUT2 Mixer
+ */
+#define WM8994_IN2LRP_TO_HPOUT2 0x0020 /* IN2LRP_TO_HPOUT2 */
+#define WM8994_IN2LRP_TO_HPOUT2_MASK 0x0020 /* IN2LRP_TO_HPOUT2 */
+#define WM8994_IN2LRP_TO_HPOUT2_SHIFT 5 /* IN2LRP_TO_HPOUT2 */
+#define WM8994_IN2LRP_TO_HPOUT2_WIDTH 1 /* IN2LRP_TO_HPOUT2 */
+#define WM8994_MIXOUTLVOL_TO_HPOUT2 0x0010 /* MIXOUTLVOL_TO_HPOUT2 */
+#define WM8994_MIXOUTLVOL_TO_HPOUT2_MASK 0x0010 /* MIXOUTLVOL_TO_HPOUT2 */
+#define WM8994_MIXOUTLVOL_TO_HPOUT2_SHIFT 4 /* MIXOUTLVOL_TO_HPOUT2 */
+#define WM8994_MIXOUTLVOL_TO_HPOUT2_WIDTH 1 /* MIXOUTLVOL_TO_HPOUT2 */
+#define WM8994_MIXOUTRVOL_TO_HPOUT2 0x0008 /* MIXOUTRVOL_TO_HPOUT2 */
+#define WM8994_MIXOUTRVOL_TO_HPOUT2_MASK 0x0008 /* MIXOUTRVOL_TO_HPOUT2 */
+#define WM8994_MIXOUTRVOL_TO_HPOUT2_SHIFT 3 /* MIXOUTRVOL_TO_HPOUT2 */
+#define WM8994_MIXOUTRVOL_TO_HPOUT2_WIDTH 1 /* MIXOUTRVOL_TO_HPOUT2 */
+
+/*
+ * R52 (0x34) - Line Mixer (1)
+ */
+#define WM8994_MIXOUTL_TO_LINEOUT1N 0x0040 /* MIXOUTL_TO_LINEOUT1N */
+#define WM8994_MIXOUTL_TO_LINEOUT1N_MASK 0x0040 /* MIXOUTL_TO_LINEOUT1N */
+#define WM8994_MIXOUTL_TO_LINEOUT1N_SHIFT 6 /* MIXOUTL_TO_LINEOUT1N */
+#define WM8994_MIXOUTL_TO_LINEOUT1N_WIDTH 1 /* MIXOUTL_TO_LINEOUT1N */
+#define WM8994_MIXOUTR_TO_LINEOUT1N 0x0020 /* MIXOUTR_TO_LINEOUT1N */
+#define WM8994_MIXOUTR_TO_LINEOUT1N_MASK 0x0020 /* MIXOUTR_TO_LINEOUT1N */
+#define WM8994_MIXOUTR_TO_LINEOUT1N_SHIFT 5 /* MIXOUTR_TO_LINEOUT1N */
+#define WM8994_MIXOUTR_TO_LINEOUT1N_WIDTH 1 /* MIXOUTR_TO_LINEOUT1N */
+#define WM8994_LINEOUT1_MODE 0x0010 /* LINEOUT1_MODE */
+#define WM8994_LINEOUT1_MODE_MASK 0x0010 /* LINEOUT1_MODE */
+#define WM8994_LINEOUT1_MODE_SHIFT 4 /* LINEOUT1_MODE */
+#define WM8994_LINEOUT1_MODE_WIDTH 1 /* LINEOUT1_MODE */
+#define WM8994_IN1R_TO_LINEOUT1P 0x0004 /* IN1R_TO_LINEOUT1P */
+#define WM8994_IN1R_TO_LINEOUT1P_MASK 0x0004 /* IN1R_TO_LINEOUT1P */
+#define WM8994_IN1R_TO_LINEOUT1P_SHIFT 2 /* IN1R_TO_LINEOUT1P */
+#define WM8994_IN1R_TO_LINEOUT1P_WIDTH 1 /* IN1R_TO_LINEOUT1P */
+#define WM8994_IN1L_TO_LINEOUT1P 0x0002 /* IN1L_TO_LINEOUT1P */
+#define WM8994_IN1L_TO_LINEOUT1P_MASK 0x0002 /* IN1L_TO_LINEOUT1P */
+#define WM8994_IN1L_TO_LINEOUT1P_SHIFT 1 /* IN1L_TO_LINEOUT1P */
+#define WM8994_IN1L_TO_LINEOUT1P_WIDTH 1 /* IN1L_TO_LINEOUT1P */
+#define WM8994_MIXOUTL_TO_LINEOUT1P 0x0001 /* MIXOUTL_TO_LINEOUT1P */
+#define WM8994_MIXOUTL_TO_LINEOUT1P_MASK 0x0001 /* MIXOUTL_TO_LINEOUT1P */
+#define WM8994_MIXOUTL_TO_LINEOUT1P_SHIFT 0 /* MIXOUTL_TO_LINEOUT1P */
+#define WM8994_MIXOUTL_TO_LINEOUT1P_WIDTH 1 /* MIXOUTL_TO_LINEOUT1P */
+
+/*
+ * R53 (0x35) - Line Mixer (2)
+ */
+#define WM8994_MIXOUTR_TO_LINEOUT2N 0x0040 /* MIXOUTR_TO_LINEOUT2N */
+#define WM8994_MIXOUTR_TO_LINEOUT2N_MASK 0x0040 /* MIXOUTR_TO_LINEOUT2N */
+#define WM8994_MIXOUTR_TO_LINEOUT2N_SHIFT 6 /* MIXOUTR_TO_LINEOUT2N */
+#define WM8994_MIXOUTR_TO_LINEOUT2N_WIDTH 1 /* MIXOUTR_TO_LINEOUT2N */
+#define WM8994_MIXOUTL_TO_LINEOUT2N 0x0020 /* MIXOUTL_TO_LINEOUT2N */
+#define WM8994_MIXOUTL_TO_LINEOUT2N_MASK 0x0020 /* MIXOUTL_TO_LINEOUT2N */
+#define WM8994_MIXOUTL_TO_LINEOUT2N_SHIFT 5 /* MIXOUTL_TO_LINEOUT2N */
+#define WM8994_MIXOUTL_TO_LINEOUT2N_WIDTH 1 /* MIXOUTL_TO_LINEOUT2N */
+#define WM8994_LINEOUT2_MODE 0x0010 /* LINEOUT2_MODE */
+#define WM8994_LINEOUT2_MODE_MASK 0x0010 /* LINEOUT2_MODE */
+#define WM8994_LINEOUT2_MODE_SHIFT 4 /* LINEOUT2_MODE */
+#define WM8994_LINEOUT2_MODE_WIDTH 1 /* LINEOUT2_MODE */
+#define WM8994_IN1L_TO_LINEOUT2P 0x0004 /* IN1L_TO_LINEOUT2P */
+#define WM8994_IN1L_TO_LINEOUT2P_MASK 0x0004 /* IN1L_TO_LINEOUT2P */
+#define WM8994_IN1L_TO_LINEOUT2P_SHIFT 2 /* IN1L_TO_LINEOUT2P */
+#define WM8994_IN1L_TO_LINEOUT2P_WIDTH 1 /* IN1L_TO_LINEOUT2P */
+#define WM8994_IN1R_TO_LINEOUT2P 0x0002 /* IN1R_TO_LINEOUT2P */
+#define WM8994_IN1R_TO_LINEOUT2P_MASK 0x0002 /* IN1R_TO_LINEOUT2P */
+#define WM8994_IN1R_TO_LINEOUT2P_SHIFT 1 /* IN1R_TO_LINEOUT2P */
+#define WM8994_IN1R_TO_LINEOUT2P_WIDTH 1 /* IN1R_TO_LINEOUT2P */
+#define WM8994_MIXOUTR_TO_LINEOUT2P 0x0001 /* MIXOUTR_TO_LINEOUT2P */
+#define WM8994_MIXOUTR_TO_LINEOUT2P_MASK 0x0001 /* MIXOUTR_TO_LINEOUT2P */
+#define WM8994_MIXOUTR_TO_LINEOUT2P_SHIFT 0 /* MIXOUTR_TO_LINEOUT2P */
+#define WM8994_MIXOUTR_TO_LINEOUT2P_WIDTH 1 /* MIXOUTR_TO_LINEOUT2P */
+
+/*
+ * R54 (0x36) - Speaker Mixer
+ */
+#define WM8994_DAC2L_TO_SPKMIXL 0x0200 /* DAC2L_TO_SPKMIXL */
+#define WM8994_DAC2L_TO_SPKMIXL_MASK 0x0200 /* DAC2L_TO_SPKMIXL */
+#define WM8994_DAC2L_TO_SPKMIXL_SHIFT 9 /* DAC2L_TO_SPKMIXL */
+#define WM8994_DAC2L_TO_SPKMIXL_WIDTH 1 /* DAC2L_TO_SPKMIXL */
+#define WM8994_DAC2R_TO_SPKMIXR 0x0100 /* DAC2R_TO_SPKMIXR */
+#define WM8994_DAC2R_TO_SPKMIXR_MASK 0x0100 /* DAC2R_TO_SPKMIXR */
+#define WM8994_DAC2R_TO_SPKMIXR_SHIFT 8 /* DAC2R_TO_SPKMIXR */
+#define WM8994_DAC2R_TO_SPKMIXR_WIDTH 1 /* DAC2R_TO_SPKMIXR */
+#define WM8994_MIXINL_TO_SPKMIXL 0x0080 /* MIXINL_TO_SPKMIXL */
+#define WM8994_MIXINL_TO_SPKMIXL_MASK 0x0080 /* MIXINL_TO_SPKMIXL */
+#define WM8994_MIXINL_TO_SPKMIXL_SHIFT 7 /* MIXINL_TO_SPKMIXL */
+#define WM8994_MIXINL_TO_SPKMIXL_WIDTH 1 /* MIXINL_TO_SPKMIXL */
+#define WM8994_MIXINR_TO_SPKMIXR 0x0040 /* MIXINR_TO_SPKMIXR */
+#define WM8994_MIXINR_TO_SPKMIXR_MASK 0x0040 /* MIXINR_TO_SPKMIXR */
+#define WM8994_MIXINR_TO_SPKMIXR_SHIFT 6 /* MIXINR_TO_SPKMIXR */
+#define WM8994_MIXINR_TO_SPKMIXR_WIDTH 1 /* MIXINR_TO_SPKMIXR */
+#define WM8994_IN1LP_TO_SPKMIXL 0x0020 /* IN1LP_TO_SPKMIXL */
+#define WM8994_IN1LP_TO_SPKMIXL_MASK 0x0020 /* IN1LP_TO_SPKMIXL */
+#define WM8994_IN1LP_TO_SPKMIXL_SHIFT 5 /* IN1LP_TO_SPKMIXL */
+#define WM8994_IN1LP_TO_SPKMIXL_WIDTH 1 /* IN1LP_TO_SPKMIXL */
+#define WM8994_IN1RP_TO_SPKMIXR 0x0010 /* IN1RP_TO_SPKMIXR */
+#define WM8994_IN1RP_TO_SPKMIXR_MASK 0x0010 /* IN1RP_TO_SPKMIXR */
+#define WM8994_IN1RP_TO_SPKMIXR_SHIFT 4 /* IN1RP_TO_SPKMIXR */
+#define WM8994_IN1RP_TO_SPKMIXR_WIDTH 1 /* IN1RP_TO_SPKMIXR */
+#define WM8994_MIXOUTL_TO_SPKMIXL 0x0008 /* MIXOUTL_TO_SPKMIXL */
+#define WM8994_MIXOUTL_TO_SPKMIXL_MASK 0x0008 /* MIXOUTL_TO_SPKMIXL */
+#define WM8994_MIXOUTL_TO_SPKMIXL_SHIFT 3 /* MIXOUTL_TO_SPKMIXL */
+#define WM8994_MIXOUTL_TO_SPKMIXL_WIDTH 1 /* MIXOUTL_TO_SPKMIXL */
+#define WM8994_MIXOUTR_TO_SPKMIXR 0x0004 /* MIXOUTR_TO_SPKMIXR */
+#define WM8994_MIXOUTR_TO_SPKMIXR_MASK 0x0004 /* MIXOUTR_TO_SPKMIXR */
+#define WM8994_MIXOUTR_TO_SPKMIXR_SHIFT 2 /* MIXOUTR_TO_SPKMIXR */
+#define WM8994_MIXOUTR_TO_SPKMIXR_WIDTH 1 /* MIXOUTR_TO_SPKMIXR */
+#define WM8994_DAC1L_TO_SPKMIXL 0x0002 /* DAC1L_TO_SPKMIXL */
+#define WM8994_DAC1L_TO_SPKMIXL_MASK 0x0002 /* DAC1L_TO_SPKMIXL */
+#define WM8994_DAC1L_TO_SPKMIXL_SHIFT 1 /* DAC1L_TO_SPKMIXL */
+#define WM8994_DAC1L_TO_SPKMIXL_WIDTH 1 /* DAC1L_TO_SPKMIXL */
+#define WM8994_DAC1R_TO_SPKMIXR 0x0001 /* DAC1R_TO_SPKMIXR */
+#define WM8994_DAC1R_TO_SPKMIXR_MASK 0x0001 /* DAC1R_TO_SPKMIXR */
+#define WM8994_DAC1R_TO_SPKMIXR_SHIFT 0 /* DAC1R_TO_SPKMIXR */
+#define WM8994_DAC1R_TO_SPKMIXR_WIDTH 1 /* DAC1R_TO_SPKMIXR */
+
+/*
+ * R55 (0x37) - Additional Control
+ */
+#define WM8994_LINEOUT1_FB 0x0080 /* LINEOUT1_FB */
+#define WM8994_LINEOUT1_FB_MASK 0x0080 /* LINEOUT1_FB */
+#define WM8994_LINEOUT1_FB_SHIFT 7 /* LINEOUT1_FB */
+#define WM8994_LINEOUT1_FB_WIDTH 1 /* LINEOUT1_FB */
+#define WM8994_LINEOUT2_FB 0x0040 /* LINEOUT2_FB */
+#define WM8994_LINEOUT2_FB_MASK 0x0040 /* LINEOUT2_FB */
+#define WM8994_LINEOUT2_FB_SHIFT 6 /* LINEOUT2_FB */
+#define WM8994_LINEOUT2_FB_WIDTH 1 /* LINEOUT2_FB */
+#define WM8994_VROI 0x0001 /* VROI */
+#define WM8994_VROI_MASK 0x0001 /* VROI */
+#define WM8994_VROI_SHIFT 0 /* VROI */
+#define WM8994_VROI_WIDTH 1 /* VROI */
+
+/*
+ * R56 (0x38) - AntiPOP (1)
+ */
+#define WM8994_LINEOUT_VMID_BUF_ENA 0x0080 /* LINEOUT_VMID_BUF_ENA */
+#define WM8994_LINEOUT_VMID_BUF_ENA_MASK 0x0080 /* LINEOUT_VMID_BUF_ENA */
+#define WM8994_LINEOUT_VMID_BUF_ENA_SHIFT 7 /* LINEOUT_VMID_BUF_ENA */
+#define WM8994_LINEOUT_VMID_BUF_ENA_WIDTH 1 /* LINEOUT_VMID_BUF_ENA */
+#define WM8994_HPOUT2_IN_ENA 0x0040 /* HPOUT2_IN_ENA */
+#define WM8994_HPOUT2_IN_ENA_MASK 0x0040 /* HPOUT2_IN_ENA */
+#define WM8994_HPOUT2_IN_ENA_SHIFT 6 /* HPOUT2_IN_ENA */
+#define WM8994_HPOUT2_IN_ENA_WIDTH 1 /* HPOUT2_IN_ENA */
+#define WM8994_LINEOUT1_DISCH 0x0020 /* LINEOUT1_DISCH */
+#define WM8994_LINEOUT1_DISCH_MASK 0x0020 /* LINEOUT1_DISCH */
+#define WM8994_LINEOUT1_DISCH_SHIFT 5 /* LINEOUT1_DISCH */
+#define WM8994_LINEOUT1_DISCH_WIDTH 1 /* LINEOUT1_DISCH */
+#define WM8994_LINEOUT2_DISCH 0x0010 /* LINEOUT2_DISCH */
+#define WM8994_LINEOUT2_DISCH_MASK 0x0010 /* LINEOUT2_DISCH */
+#define WM8994_LINEOUT2_DISCH_SHIFT 4 /* LINEOUT2_DISCH */
+#define WM8994_LINEOUT2_DISCH_WIDTH 1 /* LINEOUT2_DISCH */
+
+/*
+ * R57 (0x39) - AntiPOP (2)
+ */
+#define WM8994_MICB2_DISCH 0x0100 /* MICB2_DISCH */
+#define WM8994_MICB2_DISCH_MASK 0x0100 /* MICB2_DISCH */
+#define WM8994_MICB2_DISCH_SHIFT 8 /* MICB2_DISCH */
+#define WM8994_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
+#define WM8994_MICB1_DISCH 0x0080 /* MICB1_DISCH */
+#define WM8994_MICB1_DISCH_MASK 0x0080 /* MICB1_DISCH */
+#define WM8994_MICB1_DISCH_SHIFT 7 /* MICB1_DISCH */
+#define WM8994_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
+#define WM8994_VMID_RAMP_MASK 0x0060 /* VMID_RAMP - [6:5] */
+#define WM8994_VMID_RAMP_SHIFT 5 /* VMID_RAMP - [6:5] */
+#define WM8994_VMID_RAMP_WIDTH 2 /* VMID_RAMP - [6:5] */
+#define WM8994_VMID_BUF_ENA 0x0008 /* VMID_BUF_ENA */
+#define WM8994_VMID_BUF_ENA_MASK 0x0008 /* VMID_BUF_ENA */
+#define WM8994_VMID_BUF_ENA_SHIFT 3 /* VMID_BUF_ENA */
+#define WM8994_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */
+#define WM8994_STARTUP_BIAS_ENA 0x0004 /* STARTUP_BIAS_ENA */
+#define WM8994_STARTUP_BIAS_ENA_MASK 0x0004 /* STARTUP_BIAS_ENA */
+#define WM8994_STARTUP_BIAS_ENA_SHIFT 2 /* STARTUP_BIAS_ENA */
+#define WM8994_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */
+#define WM8994_BIAS_SRC 0x0002 /* BIAS_SRC */
+#define WM8994_BIAS_SRC_MASK 0x0002 /* BIAS_SRC */
+#define WM8994_BIAS_SRC_SHIFT 1 /* BIAS_SRC */
+#define WM8994_BIAS_SRC_WIDTH 1 /* BIAS_SRC */
+#define WM8994_VMID_DISCH 0x0001 /* VMID_DISCH */
+#define WM8994_VMID_DISCH_MASK 0x0001 /* VMID_DISCH */
+#define WM8994_VMID_DISCH_SHIFT 0 /* VMID_DISCH */
+#define WM8994_VMID_DISCH_WIDTH 1 /* VMID_DISCH */
+
+/*
+ * R58 (0x3A) - MICBIAS
+ */
+#define WM8994_MICD_SCTHR_MASK 0x00C0 /* MICD_SCTHR - [7:6] */
+#define WM8994_MICD_SCTHR_SHIFT 6 /* MICD_SCTHR - [7:6] */
+#define WM8994_MICD_SCTHR_WIDTH 2 /* MICD_SCTHR - [7:6] */
+#define WM8994_MICD_THR_MASK 0x0038 /* MICD_THR - [5:3] */
+#define WM8994_MICD_THR_SHIFT 3 /* MICD_THR - [5:3] */
+#define WM8994_MICD_THR_WIDTH 3 /* MICD_THR - [5:3] */
+#define WM8994_MICD_ENA 0x0004 /* MICD_ENA */
+#define WM8994_MICD_ENA_MASK 0x0004 /* MICD_ENA */
+#define WM8994_MICD_ENA_SHIFT 2 /* MICD_ENA */
+#define WM8994_MICD_ENA_WIDTH 1 /* MICD_ENA */
+#define WM8994_MICB2_LVL 0x0002 /* MICB2_LVL */
+#define WM8994_MICB2_LVL_MASK 0x0002 /* MICB2_LVL */
+#define WM8994_MICB2_LVL_SHIFT 1 /* MICB2_LVL */
+#define WM8994_MICB2_LVL_WIDTH 1 /* MICB2_LVL */
+#define WM8994_MICB1_LVL 0x0001 /* MICB1_LVL */
+#define WM8994_MICB1_LVL_MASK 0x0001 /* MICB1_LVL */
+#define WM8994_MICB1_LVL_SHIFT 0 /* MICB1_LVL */
+#define WM8994_MICB1_LVL_WIDTH 1 /* MICB1_LVL */
+
+/*
+ * R59 (0x3B) - LDO 1
+ */
+#define WM8994_LDO1_VSEL_MASK 0x000E /* LDO1_VSEL - [3:1] */
+#define WM8994_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [3:1] */
+#define WM8994_LDO1_VSEL_WIDTH 3 /* LDO1_VSEL - [3:1] */
+#define WM8994_LDO1_DISCH 0x0001 /* LDO1_DISCH */
+#define WM8994_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */
+#define WM8994_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */
+#define WM8994_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */
+
+/*
+ * R60 (0x3C) - LDO 2
+ */
+#define WM8994_LDO2_VSEL_MASK 0x0006 /* LDO2_VSEL - [2:1] */
+#define WM8994_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [2:1] */
+#define WM8994_LDO2_VSEL_WIDTH 2 /* LDO2_VSEL - [2:1] */
+#define WM8994_LDO2_DISCH 0x0001 /* LDO2_DISCH */
+#define WM8994_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */
+#define WM8994_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */
+#define WM8994_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */
+
+/*
+ * R76 (0x4C) - Charge Pump (1)
+ */
+#define WM8994_CP_ENA 0x8000 /* CP_ENA */
+#define WM8994_CP_ENA_MASK 0x8000 /* CP_ENA */
+#define WM8994_CP_ENA_SHIFT 15 /* CP_ENA */
+#define WM8994_CP_ENA_WIDTH 1 /* CP_ENA */
+
+/*
+ * R81 (0x51) - Class W (1)
+ */
+#define WM8994_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */
+#define WM8994_CP_DYN_SRC_SEL_SHIFT 8 /* CP_DYN_SRC_SEL - [9:8] */
+#define WM8994_CP_DYN_SRC_SEL_WIDTH 2 /* CP_DYN_SRC_SEL - [9:8] */
+#define WM8994_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */
+#define WM8994_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */
+#define WM8994_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */
+#define WM8994_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */
+
+/*
+ * R84 (0x54) - DC Servo (1)
+ */
+#define WM8994_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */
+#define WM8994_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */
+#define WM8994_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */
+#define WM8994_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */
+#define WM8994_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */
+#define WM8994_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */
+#define WM8994_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */
+#define WM8994_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */
+#define WM8994_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */
+#define WM8994_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */
+#define WM8994_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */
+#define WM8994_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */
+#define WM8994_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */
+#define WM8994_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */
+#define WM8994_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */
+#define WM8994_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */
+#define WM8994_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */
+#define WM8994_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */
+#define WM8994_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */
+#define WM8994_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */
+#define WM8994_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */
+#define WM8994_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */
+#define WM8994_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */
+#define WM8994_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */
+#define WM8994_DCS_TRIG_DAC_WR_1 0x0008 /* DCS_TRIG_DAC_WR_1 */
+#define WM8994_DCS_TRIG_DAC_WR_1_MASK 0x0008 /* DCS_TRIG_DAC_WR_1 */
+#define WM8994_DCS_TRIG_DAC_WR_1_SHIFT 3 /* DCS_TRIG_DAC_WR_1 */
+#define WM8994_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */
+#define WM8994_DCS_TRIG_DAC_WR_0 0x0004 /* DCS_TRIG_DAC_WR_0 */
+#define WM8994_DCS_TRIG_DAC_WR_0_MASK 0x0004 /* DCS_TRIG_DAC_WR_0 */
+#define WM8994_DCS_TRIG_DAC_WR_0_SHIFT 2 /* DCS_TRIG_DAC_WR_0 */
+#define WM8994_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */
+#define WM8994_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */
+#define WM8994_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */
+#define WM8994_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */
+#define WM8994_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */
+#define WM8994_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */
+#define WM8994_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */
+#define WM8994_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */
+#define WM8994_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */
+
+/*
+ * R85 (0x55) - DC Servo (2)
+ */
+#define WM8994_DCS_SERIES_NO_01_MASK 0x0FE0 /* DCS_SERIES_NO_01 - [11:5] */
+#define WM8994_DCS_SERIES_NO_01_SHIFT 5 /* DCS_SERIES_NO_01 - [11:5] */
+#define WM8994_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [11:5] */
+#define WM8994_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */
+#define WM8994_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */
+#define WM8994_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */
+
+/*
+ * R87 (0x57) - DC Servo (4)
+ */
+#define WM8994_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */
+#define WM8994_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
+#define WM8994_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
+#define WM8994_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */
+#define WM8994_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */
+#define WM8994_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */
+
+/*
+ * R88 (0x58) - DC Servo Readback
+ */
+#define WM8994_DCS_CAL_COMPLETE_MASK 0x0300 /* DCS_CAL_COMPLETE - [9:8] */
+#define WM8994_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [9:8] */
+#define WM8994_DCS_CAL_COMPLETE_WIDTH 2 /* DCS_CAL_COMPLETE - [9:8] */
+#define WM8994_DCS_DAC_WR_COMPLETE_MASK 0x0030 /* DCS_DAC_WR_COMPLETE - [5:4] */
+#define WM8994_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [5:4] */
+#define WM8994_DCS_DAC_WR_COMPLETE_WIDTH 2 /* DCS_DAC_WR_COMPLETE - [5:4] */
+#define WM8994_DCS_STARTUP_COMPLETE_MASK 0x0003 /* DCS_STARTUP_COMPLETE - [1:0] */
+#define WM8994_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [1:0] */
+#define WM8994_DCS_STARTUP_COMPLETE_WIDTH 2 /* DCS_STARTUP_COMPLETE - [1:0] */
+
+/*
+ * R96 (0x60) - Analogue HP (1)
+ */
+#define WM8994_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */
+#define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */
+#define WM8994_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */
+#define WM8994_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */
+#define WM8994_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */
+#define WM8994_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */
+#define WM8994_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */
+#define WM8994_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */
+#define WM8994_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */
+#define WM8994_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */
+#define WM8994_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */
+#define WM8994_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */
+#define WM8994_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */
+#define WM8994_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */
+#define WM8994_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */
+#define WM8994_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */
+#define WM8994_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */
+#define WM8994_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */
+#define WM8994_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */
+#define WM8994_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */
+#define WM8994_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */
+#define WM8994_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */
+#define WM8994_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */
+#define WM8994_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */
+
+/*
+ * R256 (0x100) - Chip Revision
+ */
+#define WM8994_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */
+#define WM8994_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */
+#define WM8994_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */
+
+/*
+ * R257 (0x101) - Control Interface
+ */
+#define WM8994_SPI_CONTRD 0x0040 /* SPI_CONTRD */
+#define WM8994_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */
+#define WM8994_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */
+#define WM8994_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */
+#define WM8994_SPI_4WIRE 0x0020 /* SPI_4WIRE */
+#define WM8994_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */
+#define WM8994_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */
+#define WM8994_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
+#define WM8994_SPI_CFG 0x0010 /* SPI_CFG */
+#define WM8994_SPI_CFG_MASK 0x0010 /* SPI_CFG */
+#define WM8994_SPI_CFG_SHIFT 4 /* SPI_CFG */
+#define WM8994_SPI_CFG_WIDTH 1 /* SPI_CFG */
+#define WM8994_AUTO_INC 0x0004 /* AUTO_INC */
+#define WM8994_AUTO_INC_MASK 0x0004 /* AUTO_INC */
+#define WM8994_AUTO_INC_SHIFT 2 /* AUTO_INC */
+#define WM8994_AUTO_INC_WIDTH 1 /* AUTO_INC */
+
+/*
+ * R272 (0x110) - Write Sequencer Ctrl (1)
+ */
+#define WM8994_WSEQ_ENA 0x8000 /* WSEQ_ENA */
+#define WM8994_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */
+#define WM8994_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */
+#define WM8994_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
+#define WM8994_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
+#define WM8994_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
+#define WM8994_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
+#define WM8994_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
+#define WM8994_WSEQ_START 0x0100 /* WSEQ_START */
+#define WM8994_WSEQ_START_MASK 0x0100 /* WSEQ_START */
+#define WM8994_WSEQ_START_SHIFT 8 /* WSEQ_START */
+#define WM8994_WSEQ_START_WIDTH 1 /* WSEQ_START */
+#define WM8994_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
+#define WM8994_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
+#define WM8994_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
+
+/*
+ * R273 (0x111) - Write Sequencer Ctrl (2)
+ */
+#define WM8994_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */
+#define WM8994_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */
+#define WM8994_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */
+#define WM8994_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
+#define WM8994_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */
+#define WM8994_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */
+#define WM8994_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */
+
+/*
+ * R512 (0x200) - AIF1 Clocking (1)
+ */
+#define WM8994_AIF1CLK_SRC_MASK 0x0018 /* AIF1CLK_SRC - [4:3] */
+#define WM8994_AIF1CLK_SRC_SHIFT 3 /* AIF1CLK_SRC - [4:3] */
+#define WM8994_AIF1CLK_SRC_WIDTH 2 /* AIF1CLK_SRC - [4:3] */
+#define WM8994_AIF1CLK_INV 0x0004 /* AIF1CLK_INV */
+#define WM8994_AIF1CLK_INV_MASK 0x0004 /* AIF1CLK_INV */
+#define WM8994_AIF1CLK_INV_SHIFT 2 /* AIF1CLK_INV */
+#define WM8994_AIF1CLK_INV_WIDTH 1 /* AIF1CLK_INV */
+#define WM8994_AIF1CLK_DIV 0x0002 /* AIF1CLK_DIV */
+#define WM8994_AIF1CLK_DIV_MASK 0x0002 /* AIF1CLK_DIV */
+#define WM8994_AIF1CLK_DIV_SHIFT 1 /* AIF1CLK_DIV */
+#define WM8994_AIF1CLK_DIV_WIDTH 1 /* AIF1CLK_DIV */
+#define WM8994_AIF1CLK_ENA 0x0001 /* AIF1CLK_ENA */
+#define WM8994_AIF1CLK_ENA_MASK 0x0001 /* AIF1CLK_ENA */
+#define WM8994_AIF1CLK_ENA_SHIFT 0 /* AIF1CLK_ENA */
+#define WM8994_AIF1CLK_ENA_WIDTH 1 /* AIF1CLK_ENA */
+
+/*
+ * R513 (0x201) - AIF1 Clocking (2)
+ */
+#define WM8994_AIF1DAC_DIV_MASK 0x0038 /* AIF1DAC_DIV - [5:3] */
+#define WM8994_AIF1DAC_DIV_SHIFT 3 /* AIF1DAC_DIV - [5:3] */
+#define WM8994_AIF1DAC_DIV_WIDTH 3 /* AIF1DAC_DIV - [5:3] */
+#define WM8994_AIF1ADC_DIV_MASK 0x0007 /* AIF1ADC_DIV - [2:0] */
+#define WM8994_AIF1ADC_DIV_SHIFT 0 /* AIF1ADC_DIV - [2:0] */
+#define WM8994_AIF1ADC_DIV_WIDTH 3 /* AIF1ADC_DIV - [2:0] */
+
+/*
+ * R516 (0x204) - AIF2 Clocking (1)
+ */
+#define WM8994_AIF2CLK_SRC_MASK 0x0018 /* AIF2CLK_SRC - [4:3] */
+#define WM8994_AIF2CLK_SRC_SHIFT 3 /* AIF2CLK_SRC - [4:3] */
+#define WM8994_AIF2CLK_SRC_WIDTH 2 /* AIF2CLK_SRC - [4:3] */
+#define WM8994_AIF2CLK_INV 0x0004 /* AIF2CLK_INV */
+#define WM8994_AIF2CLK_INV_MASK 0x0004 /* AIF2CLK_INV */
+#define WM8994_AIF2CLK_INV_SHIFT 2 /* AIF2CLK_INV */
+#define WM8994_AIF2CLK_INV_WIDTH 1 /* AIF2CLK_INV */
+#define WM8994_AIF2CLK_DIV 0x0002 /* AIF2CLK_DIV */
+#define WM8994_AIF2CLK_DIV_MASK 0x0002 /* AIF2CLK_DIV */
+#define WM8994_AIF2CLK_DIV_SHIFT 1 /* AIF2CLK_DIV */
+#define WM8994_AIF2CLK_DIV_WIDTH 1 /* AIF2CLK_DIV */
+#define WM8994_AIF2CLK_ENA 0x0001 /* AIF2CLK_ENA */
+#define WM8994_AIF2CLK_ENA_MASK 0x0001 /* AIF2CLK_ENA */
+#define WM8994_AIF2CLK_ENA_SHIFT 0 /* AIF2CLK_ENA */
+#define WM8994_AIF2CLK_ENA_WIDTH 1 /* AIF2CLK_ENA */
+
+/*
+ * R517 (0x205) - AIF2 Clocking (2)
+ */
+#define WM8994_AIF2DAC_DIV_MASK 0x0038 /* AIF2DAC_DIV - [5:3] */
+#define WM8994_AIF2DAC_DIV_SHIFT 3 /* AIF2DAC_DIV - [5:3] */
+#define WM8994_AIF2DAC_DIV_WIDTH 3 /* AIF2DAC_DIV - [5:3] */
+#define WM8994_AIF2ADC_DIV_MASK 0x0007 /* AIF2ADC_DIV - [2:0] */
+#define WM8994_AIF2ADC_DIV_SHIFT 0 /* AIF2ADC_DIV - [2:0] */
+#define WM8994_AIF2ADC_DIV_WIDTH 3 /* AIF2ADC_DIV - [2:0] */
+
+/*
+ * R520 (0x208) - Clocking (1)
+ */
+#define WM8994_TOCLK_ENA 0x0010 /* TOCLK_ENA */
+#define WM8994_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */
+#define WM8994_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */
+#define WM8994_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
+#define WM8994_AIF1DSPCLK_ENA 0x0008 /* AIF1DSPCLK_ENA */
+#define WM8994_AIF1DSPCLK_ENA_MASK 0x0008 /* AIF1DSPCLK_ENA */
+#define WM8994_AIF1DSPCLK_ENA_SHIFT 3 /* AIF1DSPCLK_ENA */
+#define WM8994_AIF1DSPCLK_ENA_WIDTH 1 /* AIF1DSPCLK_ENA */
+#define WM8994_AIF2DSPCLK_ENA 0x0004 /* AIF2DSPCLK_ENA */
+#define WM8994_AIF2DSPCLK_ENA_MASK 0x0004 /* AIF2DSPCLK_ENA */
+#define WM8994_AIF2DSPCLK_ENA_SHIFT 2 /* AIF2DSPCLK_ENA */
+#define WM8994_AIF2DSPCLK_ENA_WIDTH 1 /* AIF2DSPCLK_ENA */
+#define WM8994_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */
+#define WM8994_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */
+#define WM8994_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */
+#define WM8994_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */
+#define WM8994_SYSCLK_SRC 0x0001 /* SYSCLK_SRC */
+#define WM8994_SYSCLK_SRC_MASK 0x0001 /* SYSCLK_SRC */
+#define WM8994_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC */
+#define WM8994_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */
+
+/*
+ * R521 (0x209) - Clocking (2)
+ */
+#define WM8994_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */
+#define WM8994_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */
+#define WM8994_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */
+#define WM8994_DBCLK_DIV_MASK 0x0070 /* DBCLK_DIV - [6:4] */
+#define WM8994_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [6:4] */
+#define WM8994_DBCLK_DIV_WIDTH 3 /* DBCLK_DIV - [6:4] */
+#define WM8994_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */
+#define WM8994_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */
+#define WM8994_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */
+
+/*
+ * R528 (0x210) - AIF1 Rate
+ */
+#define WM8994_AIF1_SR_MASK 0x00F0 /* AIF1_SR - [7:4] */
+#define WM8994_AIF1_SR_SHIFT 4 /* AIF1_SR - [7:4] */
+#define WM8994_AIF1_SR_WIDTH 4 /* AIF1_SR - [7:4] */
+#define WM8994_AIF1CLK_RATE_MASK 0x000F /* AIF1CLK_RATE - [3:0] */
+#define WM8994_AIF1CLK_RATE_SHIFT 0 /* AIF1CLK_RATE - [3:0] */
+#define WM8994_AIF1CLK_RATE_WIDTH 4 /* AIF1CLK_RATE - [3:0] */
+
+/*
+ * R529 (0x211) - AIF2 Rate
+ */
+#define WM8994_AIF2_SR_MASK 0x00F0 /* AIF2_SR - [7:4] */
+#define WM8994_AIF2_SR_SHIFT 4 /* AIF2_SR - [7:4] */
+#define WM8994_AIF2_SR_WIDTH 4 /* AIF2_SR - [7:4] */
+#define WM8994_AIF2CLK_RATE_MASK 0x000F /* AIF2CLK_RATE - [3:0] */
+#define WM8994_AIF2CLK_RATE_SHIFT 0 /* AIF2CLK_RATE - [3:0] */
+#define WM8994_AIF2CLK_RATE_WIDTH 4 /* AIF2CLK_RATE - [3:0] */
+
+/*
+ * R530 (0x212) - Rate Status
+ */
+#define WM8994_SR_ERROR_MASK 0x000F /* SR_ERROR - [3:0] */
+#define WM8994_SR_ERROR_SHIFT 0 /* SR_ERROR - [3:0] */
+#define WM8994_SR_ERROR_WIDTH 4 /* SR_ERROR - [3:0] */
+
+/*
+ * R544 (0x220) - FLL1 Control (1)
+ */
+#define WM8994_FLL1_FRAC 0x0004 /* FLL1_FRAC */
+#define WM8994_FLL1_FRAC_MASK 0x0004 /* FLL1_FRAC */
+#define WM8994_FLL1_FRAC_SHIFT 2 /* FLL1_FRAC */
+#define WM8994_FLL1_FRAC_WIDTH 1 /* FLL1_FRAC */
+#define WM8994_FLL1_OSC_ENA 0x0002 /* FLL1_OSC_ENA */
+#define WM8994_FLL1_OSC_ENA_MASK 0x0002 /* FLL1_OSC_ENA */
+#define WM8994_FLL1_OSC_ENA_SHIFT 1 /* FLL1_OSC_ENA */
+#define WM8994_FLL1_OSC_ENA_WIDTH 1 /* FLL1_OSC_ENA */
+#define WM8994_FLL1_ENA 0x0001 /* FLL1_ENA */
+#define WM8994_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */
+#define WM8994_FLL1_ENA_SHIFT 0 /* FLL1_ENA */
+#define WM8994_FLL1_ENA_WIDTH 1 /* FLL1_ENA */
+
+/*
+ * R545 (0x221) - FLL1 Control (2)
+ */
+#define WM8994_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */
+#define WM8994_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */
+#define WM8994_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */
+#define WM8994_FLL1_CTRL_RATE_MASK 0x0070 /* FLL1_CTRL_RATE - [6:4] */
+#define WM8994_FLL1_CTRL_RATE_SHIFT 4 /* FLL1_CTRL_RATE - [6:4] */
+#define WM8994_FLL1_CTRL_RATE_WIDTH 3 /* FLL1_CTRL_RATE - [6:4] */
+#define WM8994_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */
+#define WM8994_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */
+#define WM8994_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */
+
+/*
+ * R546 (0x222) - FLL1 Control (3)
+ */
+#define WM8994_FLL1_K_MASK 0xFFFF /* FLL1_K - [15:0] */
+#define WM8994_FLL1_K_SHIFT 0 /* FLL1_K - [15:0] */
+#define WM8994_FLL1_K_WIDTH 16 /* FLL1_K - [15:0] */
+
+/*
+ * R547 (0x223) - FLL1 Control (4)
+ */
+#define WM8994_FLL1_N_MASK 0x7FE0 /* FLL1_N - [14:5] */
+#define WM8994_FLL1_N_SHIFT 5 /* FLL1_N - [14:5] */
+#define WM8994_FLL1_N_WIDTH 10 /* FLL1_N - [14:5] */
+#define WM8994_FLL1_LOOP_GAIN_MASK 0x000F /* FLL1_LOOP_GAIN - [3:0] */
+#define WM8994_FLL1_LOOP_GAIN_SHIFT 0 /* FLL1_LOOP_GAIN - [3:0] */
+#define WM8994_FLL1_LOOP_GAIN_WIDTH 4 /* FLL1_LOOP_GAIN - [3:0] */
+
+/*
+ * R548 (0x224) - FLL1 Control (5)
+ */
+#define WM8994_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */
+#define WM8994_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */
+#define WM8994_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */
+#define WM8994_FLL1_FRC_NCO 0x0040 /* FLL1_FRC_NCO */
+#define WM8994_FLL1_FRC_NCO_MASK 0x0040 /* FLL1_FRC_NCO */
+#define WM8994_FLL1_FRC_NCO_SHIFT 6 /* FLL1_FRC_NCO */
+#define WM8994_FLL1_FRC_NCO_WIDTH 1 /* FLL1_FRC_NCO */
+#define WM8994_FLL1_REFCLK_DIV_MASK 0x0018 /* FLL1_REFCLK_DIV - [4:3] */
+#define WM8994_FLL1_REFCLK_DIV_SHIFT 3 /* FLL1_REFCLK_DIV - [4:3] */
+#define WM8994_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [4:3] */
+#define WM8994_FLL1_REFCLK_SRC_MASK 0x0003 /* FLL1_REFCLK_SRC - [1:0] */
+#define WM8994_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [1:0] */
+#define WM8994_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */
+
+/*
+ * R576 (0x240) - FLL2 Control (1)
+ */
+#define WM8994_FLL2_FRAC 0x0004 /* FLL2_FRAC */
+#define WM8994_FLL2_FRAC_MASK 0x0004 /* FLL2_FRAC */
+#define WM8994_FLL2_FRAC_SHIFT 2 /* FLL2_FRAC */
+#define WM8994_FLL2_FRAC_WIDTH 1 /* FLL2_FRAC */
+#define WM8994_FLL2_OSC_ENA 0x0002 /* FLL2_OSC_ENA */
+#define WM8994_FLL2_OSC_ENA_MASK 0x0002 /* FLL2_OSC_ENA */
+#define WM8994_FLL2_OSC_ENA_SHIFT 1 /* FLL2_OSC_ENA */
+#define WM8994_FLL2_OSC_ENA_WIDTH 1 /* FLL2_OSC_ENA */
+#define WM8994_FLL2_ENA 0x0001 /* FLL2_ENA */
+#define WM8994_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */
+#define WM8994_FLL2_ENA_SHIFT 0 /* FLL2_ENA */
+#define WM8994_FLL2_ENA_WIDTH 1 /* FLL2_ENA */
+
+/*
+ * R577 (0x241) - FLL2 Control (2)
+ */
+#define WM8994_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */
+#define WM8994_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */
+#define WM8994_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */
+#define WM8994_FLL2_CTRL_RATE_MASK 0x0070 /* FLL2_CTRL_RATE - [6:4] */
+#define WM8994_FLL2_CTRL_RATE_SHIFT 4 /* FLL2_CTRL_RATE - [6:4] */
+#define WM8994_FLL2_CTRL_RATE_WIDTH 3 /* FLL2_CTRL_RATE - [6:4] */
+#define WM8994_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */
+#define WM8994_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */
+#define WM8994_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */
+
+/*
+ * R578 (0x242) - FLL2 Control (3)
+ */
+#define WM8994_FLL2_K_MASK 0xFFFF /* FLL2_K - [15:0] */
+#define WM8994_FLL2_K_SHIFT 0 /* FLL2_K - [15:0] */
+#define WM8994_FLL2_K_WIDTH 16 /* FLL2_K - [15:0] */
+
+/*
+ * R579 (0x243) - FLL2 Control (4)
+ */
+#define WM8994_FLL2_N_MASK 0x7FE0 /* FLL2_N - [14:5] */
+#define WM8994_FLL2_N_SHIFT 5 /* FLL2_N - [14:5] */
+#define WM8994_FLL2_N_WIDTH 10 /* FLL2_N - [14:5] */
+#define WM8994_FLL2_LOOP_GAIN_MASK 0x000F /* FLL2_LOOP_GAIN - [3:0] */
+#define WM8994_FLL2_LOOP_GAIN_SHIFT 0 /* FLL2_LOOP_GAIN - [3:0] */
+#define WM8994_FLL2_LOOP_GAIN_WIDTH 4 /* FLL2_LOOP_GAIN - [3:0] */
+
+/*
+ * R580 (0x244) - FLL2 Control (5)
+ */
+#define WM8994_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */
+#define WM8994_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */
+#define WM8994_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */
+#define WM8994_FLL2_FRC_NCO 0x0040 /* FLL2_FRC_NCO */
+#define WM8994_FLL2_FRC_NCO_MASK 0x0040 /* FLL2_FRC_NCO */
+#define WM8994_FLL2_FRC_NCO_SHIFT 6 /* FLL2_FRC_NCO */
+#define WM8994_FLL2_FRC_NCO_WIDTH 1 /* FLL2_FRC_NCO */
+#define WM8994_FLL2_REFCLK_DIV_MASK 0x0018 /* FLL2_REFCLK_DIV - [4:3] */
+#define WM8994_FLL2_REFCLK_DIV_SHIFT 3 /* FLL2_REFCLK_DIV - [4:3] */
+#define WM8994_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [4:3] */
+#define WM8994_FLL2_REFCLK_SRC_MASK 0x0003 /* FLL2_REFCLK_SRC - [1:0] */
+#define WM8994_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [1:0] */
+#define WM8994_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */
+
+/*
+ * R768 (0x300) - AIF1 Control (1)
+ */
+#define WM8994_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */
+#define WM8994_AIF1ADCL_SRC_MASK 0x8000 /* AIF1ADCL_SRC */
+#define WM8994_AIF1ADCL_SRC_SHIFT 15 /* AIF1ADCL_SRC */
+#define WM8994_AIF1ADCL_SRC_WIDTH 1 /* AIF1ADCL_SRC */
+#define WM8994_AIF1ADCR_SRC 0x4000 /* AIF1ADCR_SRC */
+#define WM8994_AIF1ADCR_SRC_MASK 0x4000 /* AIF1ADCR_SRC */
+#define WM8994_AIF1ADCR_SRC_SHIFT 14 /* AIF1ADCR_SRC */
+#define WM8994_AIF1ADCR_SRC_WIDTH 1 /* AIF1ADCR_SRC */
+#define WM8994_AIF1ADC_TDM 0x2000 /* AIF1ADC_TDM */
+#define WM8994_AIF1ADC_TDM_MASK 0x2000 /* AIF1ADC_TDM */
+#define WM8994_AIF1ADC_TDM_SHIFT 13 /* AIF1ADC_TDM */
+#define WM8994_AIF1ADC_TDM_WIDTH 1 /* AIF1ADC_TDM */
+#define WM8994_AIF1_BCLK_INV 0x0100 /* AIF1_BCLK_INV */
+#define WM8994_AIF1_BCLK_INV_MASK 0x0100 /* AIF1_BCLK_INV */
+#define WM8994_AIF1_BCLK_INV_SHIFT 8 /* AIF1_BCLK_INV */
+#define WM8994_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
+#define WM8994_AIF1_LRCLK_INV 0x0080 /* AIF1_LRCLK_INV */
+#define WM8994_AIF1_LRCLK_INV_MASK 0x0080 /* AIF1_LRCLK_INV */
+#define WM8994_AIF1_LRCLK_INV_SHIFT 7 /* AIF1_LRCLK_INV */
+#define WM8994_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */
+#define WM8994_AIF1_WL_MASK 0x0060 /* AIF1_WL - [6:5] */
+#define WM8994_AIF1_WL_SHIFT 5 /* AIF1_WL - [6:5] */
+#define WM8994_AIF1_WL_WIDTH 2 /* AIF1_WL - [6:5] */
+#define WM8994_AIF1_FMT_MASK 0x0018 /* AIF1_FMT - [4:3] */
+#define WM8994_AIF1_FMT_SHIFT 3 /* AIF1_FMT - [4:3] */
+#define WM8994_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [4:3] */
+
+/*
+ * R769 (0x301) - AIF1 Control (2)
+ */
+#define WM8994_AIF1DACL_SRC 0x8000 /* AIF1DACL_SRC */
+#define WM8994_AIF1DACL_SRC_MASK 0x8000 /* AIF1DACL_SRC */
+#define WM8994_AIF1DACL_SRC_SHIFT 15 /* AIF1DACL_SRC */
+#define WM8994_AIF1DACL_SRC_WIDTH 1 /* AIF1DACL_SRC */
+#define WM8994_AIF1DACR_SRC 0x4000 /* AIF1DACR_SRC */
+#define WM8994_AIF1DACR_SRC_MASK 0x4000 /* AIF1DACR_SRC */
+#define WM8994_AIF1DACR_SRC_SHIFT 14 /* AIF1DACR_SRC */
+#define WM8994_AIF1DACR_SRC_WIDTH 1 /* AIF1DACR_SRC */
+#define WM8994_AIF1DAC_BOOST_MASK 0x0C00 /* AIF1DAC_BOOST - [11:10] */
+#define WM8994_AIF1DAC_BOOST_SHIFT 10 /* AIF1DAC_BOOST - [11:10] */
+#define WM8994_AIF1DAC_BOOST_WIDTH 2 /* AIF1DAC_BOOST - [11:10] */
+#define WM8994_AIF1_MONO 0x0100 /* AIF1_MONO */
+#define WM8994_AIF1_MONO_MASK 0x0100 /* AIF1_MONO */
+#define WM8994_AIF1_MONO_SHIFT 8 /* AIF1_MONO */
+#define WM8994_AIF1_MONO_WIDTH 1 /* AIF1_MONO */
+#define WM8994_AIF1DAC_COMP 0x0010 /* AIF1DAC_COMP */
+#define WM8994_AIF1DAC_COMP_MASK 0x0010 /* AIF1DAC_COMP */
+#define WM8994_AIF1DAC_COMP_SHIFT 4 /* AIF1DAC_COMP */
+#define WM8994_AIF1DAC_COMP_WIDTH 1 /* AIF1DAC_COMP */
+#define WM8994_AIF1DAC_COMPMODE 0x0008 /* AIF1DAC_COMPMODE */
+#define WM8994_AIF1DAC_COMPMODE_MASK 0x0008 /* AIF1DAC_COMPMODE */
+#define WM8994_AIF1DAC_COMPMODE_SHIFT 3 /* AIF1DAC_COMPMODE */
+#define WM8994_AIF1DAC_COMPMODE_WIDTH 1 /* AIF1DAC_COMPMODE */
+#define WM8994_AIF1ADC_COMP 0x0004 /* AIF1ADC_COMP */
+#define WM8994_AIF1ADC_COMP_MASK 0x0004 /* AIF1ADC_COMP */
+#define WM8994_AIF1ADC_COMP_SHIFT 2 /* AIF1ADC_COMP */
+#define WM8994_AIF1ADC_COMP_WIDTH 1 /* AIF1ADC_COMP */
+#define WM8994_AIF1ADC_COMPMODE 0x0002 /* AIF1ADC_COMPMODE */
+#define WM8994_AIF1ADC_COMPMODE_MASK 0x0002 /* AIF1ADC_COMPMODE */
+#define WM8994_AIF1ADC_COMPMODE_SHIFT 1 /* AIF1ADC_COMPMODE */
+#define WM8994_AIF1ADC_COMPMODE_WIDTH 1 /* AIF1ADC_COMPMODE */
+#define WM8994_AIF1_LOOPBACK 0x0001 /* AIF1_LOOPBACK */
+#define WM8994_AIF1_LOOPBACK_MASK 0x0001 /* AIF1_LOOPBACK */
+#define WM8994_AIF1_LOOPBACK_SHIFT 0 /* AIF1_LOOPBACK */
+#define WM8994_AIF1_LOOPBACK_WIDTH 1 /* AIF1_LOOPBACK */
+
+/*
+ * R770 (0x302) - AIF1 Master/Slave
+ */
+#define WM8994_AIF1_TRI 0x8000 /* AIF1_TRI */
+#define WM8994_AIF1_TRI_MASK 0x8000 /* AIF1_TRI */
+#define WM8994_AIF1_TRI_SHIFT 15 /* AIF1_TRI */
+#define WM8994_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
+#define WM8994_AIF1_MSTR 0x4000 /* AIF1_MSTR */
+#define WM8994_AIF1_MSTR_MASK 0x4000 /* AIF1_MSTR */
+#define WM8994_AIF1_MSTR_SHIFT 14 /* AIF1_MSTR */
+#define WM8994_AIF1_MSTR_WIDTH 1 /* AIF1_MSTR */
+#define WM8994_AIF1_CLK_FRC 0x2000 /* AIF1_CLK_FRC */
+#define WM8994_AIF1_CLK_FRC_MASK 0x2000 /* AIF1_CLK_FRC */
+#define WM8994_AIF1_CLK_FRC_SHIFT 13 /* AIF1_CLK_FRC */
+#define WM8994_AIF1_CLK_FRC_WIDTH 1 /* AIF1_CLK_FRC */
+#define WM8994_AIF1_LRCLK_FRC 0x1000 /* AIF1_LRCLK_FRC */
+#define WM8994_AIF1_LRCLK_FRC_MASK 0x1000 /* AIF1_LRCLK_FRC */
+#define WM8994_AIF1_LRCLK_FRC_SHIFT 12 /* AIF1_LRCLK_FRC */
+#define WM8994_AIF1_LRCLK_FRC_WIDTH 1 /* AIF1_LRCLK_FRC */
+
+/*
+ * R771 (0x303) - AIF1 BCLK
+ */
+#define WM8994_AIF1_BCLK_DIV_MASK 0x01F0 /* AIF1_BCLK_DIV - [8:4] */
+#define WM8994_AIF1_BCLK_DIV_SHIFT 4 /* AIF1_BCLK_DIV - [8:4] */
+#define WM8994_AIF1_BCLK_DIV_WIDTH 5 /* AIF1_BCLK_DIV - [8:4] */
+
+/*
+ * R772 (0x304) - AIF1ADC LRCLK
+ */
+#define WM8994_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */
+#define WM8994_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */
+#define WM8994_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */
+#define WM8994_AIF1ADC_LRCLK_DIR_WIDTH 1 /* AIF1ADC_LRCLK_DIR */
+#define WM8994_AIF1ADC_RATE_MASK 0x07FF /* AIF1ADC_RATE - [10:0] */
+#define WM8994_AIF1ADC_RATE_SHIFT 0 /* AIF1ADC_RATE - [10:0] */
+#define WM8994_AIF1ADC_RATE_WIDTH 11 /* AIF1ADC_RATE - [10:0] */
+
+/*
+ * R773 (0x305) - AIF1DAC LRCLK
+ */
+#define WM8994_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */
+#define WM8994_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */
+#define WM8994_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */
+#define WM8994_AIF1DAC_LRCLK_DIR_WIDTH 1 /* AIF1DAC_LRCLK_DIR */
+#define WM8994_AIF1DAC_RATE_MASK 0x07FF /* AIF1DAC_RATE - [10:0] */
+#define WM8994_AIF1DAC_RATE_SHIFT 0 /* AIF1DAC_RATE - [10:0] */
+#define WM8994_AIF1DAC_RATE_WIDTH 11 /* AIF1DAC_RATE - [10:0] */
+
+/*
+ * R774 (0x306) - AIF1DAC Data
+ */
+#define WM8994_AIF1DACL_DAT_INV 0x0002 /* AIF1DACL_DAT_INV */
+#define WM8994_AIF1DACL_DAT_INV_MASK 0x0002 /* AIF1DACL_DAT_INV */
+#define WM8994_AIF1DACL_DAT_INV_SHIFT 1 /* AIF1DACL_DAT_INV */
+#define WM8994_AIF1DACL_DAT_INV_WIDTH 1 /* AIF1DACL_DAT_INV */
+#define WM8994_AIF1DACR_DAT_INV 0x0001 /* AIF1DACR_DAT_INV */
+#define WM8994_AIF1DACR_DAT_INV_MASK 0x0001 /* AIF1DACR_DAT_INV */
+#define WM8994_AIF1DACR_DAT_INV_SHIFT 0 /* AIF1DACR_DAT_INV */
+#define WM8994_AIF1DACR_DAT_INV_WIDTH 1 /* AIF1DACR_DAT_INV */
+
+/*
+ * R775 (0x307) - AIF1ADC Data
+ */
+#define WM8994_AIF1ADCL_DAT_INV 0x0002 /* AIF1ADCL_DAT_INV */
+#define WM8994_AIF1ADCL_DAT_INV_MASK 0x0002 /* AIF1ADCL_DAT_INV */
+#define WM8994_AIF1ADCL_DAT_INV_SHIFT 1 /* AIF1ADCL_DAT_INV */
+#define WM8994_AIF1ADCL_DAT_INV_WIDTH 1 /* AIF1ADCL_DAT_INV */
+#define WM8994_AIF1ADCR_DAT_INV 0x0001 /* AIF1ADCR_DAT_INV */
+#define WM8994_AIF1ADCR_DAT_INV_MASK 0x0001 /* AIF1ADCR_DAT_INV */
+#define WM8994_AIF1ADCR_DAT_INV_SHIFT 0 /* AIF1ADCR_DAT_INV */
+#define WM8994_AIF1ADCR_DAT_INV_WIDTH 1 /* AIF1ADCR_DAT_INV */
+
+/*
+ * R784 (0x310) - AIF2 Control (1)
+ */
+#define WM8994_AIF2ADCL_SRC 0x8000 /* AIF2ADCL_SRC */
+#define WM8994_AIF2ADCL_SRC_MASK 0x8000 /* AIF2ADCL_SRC */
+#define WM8994_AIF2ADCL_SRC_SHIFT 15 /* AIF2ADCL_SRC */
+#define WM8994_AIF2ADCL_SRC_WIDTH 1 /* AIF2ADCL_SRC */
+#define WM8994_AIF2ADCR_SRC 0x4000 /* AIF2ADCR_SRC */
+#define WM8994_AIF2ADCR_SRC_MASK 0x4000 /* AIF2ADCR_SRC */
+#define WM8994_AIF2ADCR_SRC_SHIFT 14 /* AIF2ADCR_SRC */
+#define WM8994_AIF2ADCR_SRC_WIDTH 1 /* AIF2ADCR_SRC */
+#define WM8994_AIF2ADC_TDM 0x2000 /* AIF2ADC_TDM */
+#define WM8994_AIF2ADC_TDM_MASK 0x2000 /* AIF2ADC_TDM */
+#define WM8994_AIF2ADC_TDM_SHIFT 13 /* AIF2ADC_TDM */
+#define WM8994_AIF2ADC_TDM_WIDTH 1 /* AIF2ADC_TDM */
+#define WM8994_AIF2ADC_TDM_CHAN 0x1000 /* AIF2ADC_TDM_CHAN */
+#define WM8994_AIF2ADC_TDM_CHAN_MASK 0x1000 /* AIF2ADC_TDM_CHAN */
+#define WM8994_AIF2ADC_TDM_CHAN_SHIFT 12 /* AIF2ADC_TDM_CHAN */
+#define WM8994_AIF2ADC_TDM_CHAN_WIDTH 1 /* AIF2ADC_TDM_CHAN */
+#define WM8994_AIF2_BCLK_INV 0x0100 /* AIF2_BCLK_INV */
+#define WM8994_AIF2_BCLK_INV_MASK 0x0100 /* AIF2_BCLK_INV */
+#define WM8994_AIF2_BCLK_INV_SHIFT 8 /* AIF2_BCLK_INV */
+#define WM8994_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */
+#define WM8994_AIF2_LRCLK_INV 0x0080 /* AIF2_LRCLK_INV */
+#define WM8994_AIF2_LRCLK_INV_MASK 0x0080 /* AIF2_LRCLK_INV */
+#define WM8994_AIF2_LRCLK_INV_SHIFT 7 /* AIF2_LRCLK_INV */
+#define WM8994_AIF2_LRCLK_INV_WIDTH 1 /* AIF2_LRCLK_INV */
+#define WM8994_AIF2_WL_MASK 0x0060 /* AIF2_WL - [6:5] */
+#define WM8994_AIF2_WL_SHIFT 5 /* AIF2_WL - [6:5] */
+#define WM8994_AIF2_WL_WIDTH 2 /* AIF2_WL - [6:5] */
+#define WM8994_AIF2_FMT_MASK 0x0018 /* AIF2_FMT - [4:3] */
+#define WM8994_AIF2_FMT_SHIFT 3 /* AIF2_FMT - [4:3] */
+#define WM8994_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [4:3] */
+
+/*
+ * R785 (0x311) - AIF2 Control (2)
+ */
+#define WM8994_AIF2DACL_SRC 0x8000 /* AIF2DACL_SRC */
+#define WM8994_AIF2DACL_SRC_MASK 0x8000 /* AIF2DACL_SRC */
+#define WM8994_AIF2DACL_SRC_SHIFT 15 /* AIF2DACL_SRC */
+#define WM8994_AIF2DACL_SRC_WIDTH 1 /* AIF2DACL_SRC */
+#define WM8994_AIF2DACR_SRC 0x4000 /* AIF2DACR_SRC */
+#define WM8994_AIF2DACR_SRC_MASK 0x4000 /* AIF2DACR_SRC */
+#define WM8994_AIF2DACR_SRC_SHIFT 14 /* AIF2DACR_SRC */
+#define WM8994_AIF2DACR_SRC_WIDTH 1 /* AIF2DACR_SRC */
+#define WM8994_AIF2DAC_TDM 0x2000 /* AIF2DAC_TDM */
+#define WM8994_AIF2DAC_TDM_MASK 0x2000 /* AIF2DAC_TDM */
+#define WM8994_AIF2DAC_TDM_SHIFT 13 /* AIF2DAC_TDM */
+#define WM8994_AIF2DAC_TDM_WIDTH 1 /* AIF2DAC_TDM */
+#define WM8994_AIF2DAC_TDM_CHAN 0x1000 /* AIF2DAC_TDM_CHAN */
+#define WM8994_AIF2DAC_TDM_CHAN_MASK 0x1000 /* AIF2DAC_TDM_CHAN */
+#define WM8994_AIF2DAC_TDM_CHAN_SHIFT 12 /* AIF2DAC_TDM_CHAN */
+#define WM8994_AIF2DAC_TDM_CHAN_WIDTH 1 /* AIF2DAC_TDM_CHAN */
+#define WM8994_AIF2DAC_BOOST_MASK 0x0C00 /* AIF2DAC_BOOST - [11:10] */
+#define WM8994_AIF2DAC_BOOST_SHIFT 10 /* AIF2DAC_BOOST - [11:10] */
+#define WM8994_AIF2DAC_BOOST_WIDTH 2 /* AIF2DAC_BOOST - [11:10] */
+#define WM8994_AIF2_MONO 0x0100 /* AIF2_MONO */
+#define WM8994_AIF2_MONO_MASK 0x0100 /* AIF2_MONO */
+#define WM8994_AIF2_MONO_SHIFT 8 /* AIF2_MONO */
+#define WM8994_AIF2_MONO_WIDTH 1 /* AIF2_MONO */
+#define WM8994_AIF2DAC_COMP 0x0010 /* AIF2DAC_COMP */
+#define WM8994_AIF2DAC_COMP_MASK 0x0010 /* AIF2DAC_COMP */
+#define WM8994_AIF2DAC_COMP_SHIFT 4 /* AIF2DAC_COMP */
+#define WM8994_AIF2DAC_COMP_WIDTH 1 /* AIF2DAC_COMP */
+#define WM8994_AIF2DAC_COMPMODE 0x0008 /* AIF2DAC_COMPMODE */
+#define WM8994_AIF2DAC_COMPMODE_MASK 0x0008 /* AIF2DAC_COMPMODE */
+#define WM8994_AIF2DAC_COMPMODE_SHIFT 3 /* AIF2DAC_COMPMODE */
+#define WM8994_AIF2DAC_COMPMODE_WIDTH 1 /* AIF2DAC_COMPMODE */
+#define WM8994_AIF2ADC_COMP 0x0004 /* AIF2ADC_COMP */
+#define WM8994_AIF2ADC_COMP_MASK 0x0004 /* AIF2ADC_COMP */
+#define WM8994_AIF2ADC_COMP_SHIFT 2 /* AIF2ADC_COMP */
+#define WM8994_AIF2ADC_COMP_WIDTH 1 /* AIF2ADC_COMP */
+#define WM8994_AIF2ADC_COMPMODE 0x0002 /* AIF2ADC_COMPMODE */
+#define WM8994_AIF2ADC_COMPMODE_MASK 0x0002 /* AIF2ADC_COMPMODE */
+#define WM8994_AIF2ADC_COMPMODE_SHIFT 1 /* AIF2ADC_COMPMODE */
+#define WM8994_AIF2ADC_COMPMODE_WIDTH 1 /* AIF2ADC_COMPMODE */
+#define WM8994_AIF2_LOOPBACK 0x0001 /* AIF2_LOOPBACK */
+#define WM8994_AIF2_LOOPBACK_MASK 0x0001 /* AIF2_LOOPBACK */
+#define WM8994_AIF2_LOOPBACK_SHIFT 0 /* AIF2_LOOPBACK */
+#define WM8994_AIF2_LOOPBACK_WIDTH 1 /* AIF2_LOOPBACK */
+
+/*
+ * R786 (0x312) - AIF2 Master/Slave
+ */
+#define WM8994_AIF2_TRI 0x8000 /* AIF2_TRI */
+#define WM8994_AIF2_TRI_MASK 0x8000 /* AIF2_TRI */
+#define WM8994_AIF2_TRI_SHIFT 15 /* AIF2_TRI */
+#define WM8994_AIF2_TRI_WIDTH 1 /* AIF2_TRI */
+#define WM8994_AIF2_MSTR 0x4000 /* AIF2_MSTR */
+#define WM8994_AIF2_MSTR_MASK 0x4000 /* AIF2_MSTR */
+#define WM8994_AIF2_MSTR_SHIFT 14 /* AIF2_MSTR */
+#define WM8994_AIF2_MSTR_WIDTH 1 /* AIF2_MSTR */
+#define WM8994_AIF2_CLK_FRC 0x2000 /* AIF2_CLK_FRC */
+#define WM8994_AIF2_CLK_FRC_MASK 0x2000 /* AIF2_CLK_FRC */
+#define WM8994_AIF2_CLK_FRC_SHIFT 13 /* AIF2_CLK_FRC */
+#define WM8994_AIF2_CLK_FRC_WIDTH 1 /* AIF2_CLK_FRC */
+#define WM8994_AIF2_LRCLK_FRC 0x1000 /* AIF2_LRCLK_FRC */
+#define WM8994_AIF2_LRCLK_FRC_MASK 0x1000 /* AIF2_LRCLK_FRC */
+#define WM8994_AIF2_LRCLK_FRC_SHIFT 12 /* AIF2_LRCLK_FRC */
+#define WM8994_AIF2_LRCLK_FRC_WIDTH 1 /* AIF2_LRCLK_FRC */
+
+/*
+ * R787 (0x313) - AIF2 BCLK
+ */
+#define WM8994_AIF2_BCLK_DIV_MASK 0x01F0 /* AIF2_BCLK_DIV - [8:4] */
+#define WM8994_AIF2_BCLK_DIV_SHIFT 4 /* AIF2_BCLK_DIV - [8:4] */
+#define WM8994_AIF2_BCLK_DIV_WIDTH 5 /* AIF2_BCLK_DIV - [8:4] */
+
+/*
+ * R788 (0x314) - AIF2ADC LRCLK
+ */
+#define WM8994_AIF2ADC_LRCLK_DIR 0x0800 /* AIF2ADC_LRCLK_DIR */
+#define WM8994_AIF2ADC_LRCLK_DIR_MASK 0x0800 /* AIF2ADC_LRCLK_DIR */
+#define WM8994_AIF2ADC_LRCLK_DIR_SHIFT 11 /* AIF2ADC_LRCLK_DIR */
+#define WM8994_AIF2ADC_LRCLK_DIR_WIDTH 1 /* AIF2ADC_LRCLK_DIR */
+#define WM8994_AIF2ADC_RATE_MASK 0x07FF /* AIF2ADC_RATE - [10:0] */
+#define WM8994_AIF2ADC_RATE_SHIFT 0 /* AIF2ADC_RATE - [10:0] */
+#define WM8994_AIF2ADC_RATE_WIDTH 11 /* AIF2ADC_RATE - [10:0] */
+
+/*
+ * R789 (0x315) - AIF2DAC LRCLK
+ */
+#define WM8994_AIF2DAC_LRCLK_DIR 0x0800 /* AIF2DAC_LRCLK_DIR */
+#define WM8994_AIF2DAC_LRCLK_DIR_MASK 0x0800 /* AIF2DAC_LRCLK_DIR */
+#define WM8994_AIF2DAC_LRCLK_DIR_SHIFT 11 /* AIF2DAC_LRCLK_DIR */
+#define WM8994_AIF2DAC_LRCLK_DIR_WIDTH 1 /* AIF2DAC_LRCLK_DIR */
+#define WM8994_AIF2DAC_RATE_MASK 0x07FF /* AIF2DAC_RATE - [10:0] */
+#define WM8994_AIF2DAC_RATE_SHIFT 0 /* AIF2DAC_RATE - [10:0] */
+#define WM8994_AIF2DAC_RATE_WIDTH 11 /* AIF2DAC_RATE - [10:0] */
+
+/*
+ * R790 (0x316) - AIF2DAC Data
+ */
+#define WM8994_AIF2DACL_DAT_INV 0x0002 /* AIF2DACL_DAT_INV */
+#define WM8994_AIF2DACL_DAT_INV_MASK 0x0002 /* AIF2DACL_DAT_INV */
+#define WM8994_AIF2DACL_DAT_INV_SHIFT 1 /* AIF2DACL_DAT_INV */
+#define WM8994_AIF2DACL_DAT_INV_WIDTH 1 /* AIF2DACL_DAT_INV */
+#define WM8994_AIF2DACR_DAT_INV 0x0001 /* AIF2DACR_DAT_INV */
+#define WM8994_AIF2DACR_DAT_INV_MASK 0x0001 /* AIF2DACR_DAT_INV */
+#define WM8994_AIF2DACR_DAT_INV_SHIFT 0 /* AIF2DACR_DAT_INV */
+#define WM8994_AIF2DACR_DAT_INV_WIDTH 1 /* AIF2DACR_DAT_INV */
+
+/*
+ * R791 (0x317) - AIF2ADC Data
+ */
+#define WM8994_AIF2ADCL_DAT_INV 0x0002 /* AIF2ADCL_DAT_INV */
+#define WM8994_AIF2ADCL_DAT_INV_MASK 0x0002 /* AIF2ADCL_DAT_INV */
+#define WM8994_AIF2ADCL_DAT_INV_SHIFT 1 /* AIF2ADCL_DAT_INV */
+#define WM8994_AIF2ADCL_DAT_INV_WIDTH 1 /* AIF2ADCL_DAT_INV */
+#define WM8994_AIF2ADCR_DAT_INV 0x0001 /* AIF2ADCR_DAT_INV */
+#define WM8994_AIF2ADCR_DAT_INV_MASK 0x0001 /* AIF2ADCR_DAT_INV */
+#define WM8994_AIF2ADCR_DAT_INV_SHIFT 0 /* AIF2ADCR_DAT_INV */
+#define WM8994_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */
+
+/*
+ * R1024 (0x400) - AIF1 ADC1 Left Volume
+ */
+#define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */
+#define WM8994_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */
+#define WM8994_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */
+#define WM8994_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */
+#define WM8994_AIF1ADC1L_VOL_MASK 0x00FF /* AIF1ADC1L_VOL - [7:0] */
+#define WM8994_AIF1ADC1L_VOL_SHIFT 0 /* AIF1ADC1L_VOL - [7:0] */
+#define WM8994_AIF1ADC1L_VOL_WIDTH 8 /* AIF1ADC1L_VOL - [7:0] */
+
+/*
+ * R1025 (0x401) - AIF1 ADC1 Right Volume
+ */
+#define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */
+#define WM8994_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */
+#define WM8994_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */
+#define WM8994_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */
+#define WM8994_AIF1ADC1R_VOL_MASK 0x00FF /* AIF1ADC1R_VOL - [7:0] */
+#define WM8994_AIF1ADC1R_VOL_SHIFT 0 /* AIF1ADC1R_VOL - [7:0] */
+#define WM8994_AIF1ADC1R_VOL_WIDTH 8 /* AIF1ADC1R_VOL - [7:0] */
+
+/*
+ * R1026 (0x402) - AIF1 DAC1 Left Volume
+ */
+#define WM8994_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */
+#define WM8994_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */
+#define WM8994_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */
+#define WM8994_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */
+#define WM8994_AIF1DAC1L_VOL_MASK 0x00FF /* AIF1DAC1L_VOL - [7:0] */
+#define WM8994_AIF1DAC1L_VOL_SHIFT 0 /* AIF1DAC1L_VOL - [7:0] */
+#define WM8994_AIF1DAC1L_VOL_WIDTH 8 /* AIF1DAC1L_VOL - [7:0] */
+
+/*
+ * R1027 (0x403) - AIF1 DAC1 Right Volume
+ */
+#define WM8994_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */
+#define WM8994_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */
+#define WM8994_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */
+#define WM8994_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */
+#define WM8994_AIF1DAC1R_VOL_MASK 0x00FF /* AIF1DAC1R_VOL - [7:0] */
+#define WM8994_AIF1DAC1R_VOL_SHIFT 0 /* AIF1DAC1R_VOL - [7:0] */
+#define WM8994_AIF1DAC1R_VOL_WIDTH 8 /* AIF1DAC1R_VOL - [7:0] */
+
+/*
+ * R1028 (0x404) - AIF1 ADC2 Left Volume
+ */
+#define WM8994_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */
+#define WM8994_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */
+#define WM8994_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */
+#define WM8994_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */
+#define WM8994_AIF1ADC2L_VOL_MASK 0x00FF /* AIF1ADC2L_VOL - [7:0] */
+#define WM8994_AIF1ADC2L_VOL_SHIFT 0 /* AIF1ADC2L_VOL - [7:0] */
+#define WM8994_AIF1ADC2L_VOL_WIDTH 8 /* AIF1ADC2L_VOL - [7:0] */
+
+/*
+ * R1029 (0x405) - AIF1 ADC2 Right Volume
+ */
+#define WM8994_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */
+#define WM8994_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */
+#define WM8994_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */
+#define WM8994_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */
+#define WM8994_AIF1ADC2R_VOL_MASK 0x00FF /* AIF1ADC2R_VOL - [7:0] */
+#define WM8994_AIF1ADC2R_VOL_SHIFT 0 /* AIF1ADC2R_VOL - [7:0] */
+#define WM8994_AIF1ADC2R_VOL_WIDTH 8 /* AIF1ADC2R_VOL - [7:0] */
+
+/*
+ * R1030 (0x406) - AIF1 DAC2 Left Volume
+ */
+#define WM8994_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */
+#define WM8994_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */
+#define WM8994_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */
+#define WM8994_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */
+#define WM8994_AIF1DAC2L_VOL_MASK 0x00FF /* AIF1DAC2L_VOL - [7:0] */
+#define WM8994_AIF1DAC2L_VOL_SHIFT 0 /* AIF1DAC2L_VOL - [7:0] */
+#define WM8994_AIF1DAC2L_VOL_WIDTH 8 /* AIF1DAC2L_VOL - [7:0] */
+
+/*
+ * R1031 (0x407) - AIF1 DAC2 Right Volume
+ */
+#define WM8994_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */
+#define WM8994_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */
+#define WM8994_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */
+#define WM8994_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */
+#define WM8994_AIF1DAC2R_VOL_MASK 0x00FF /* AIF1DAC2R_VOL - [7:0] */
+#define WM8994_AIF1DAC2R_VOL_SHIFT 0 /* AIF1DAC2R_VOL - [7:0] */
+#define WM8994_AIF1DAC2R_VOL_WIDTH 8 /* AIF1DAC2R_VOL - [7:0] */
+
+/*
+ * R1040 (0x410) - AIF1 ADC1 Filters
+ */
+#define WM8994_AIF1ADC_4FS 0x8000 /* AIF1ADC_4FS */
+#define WM8994_AIF1ADC_4FS_MASK 0x8000 /* AIF1ADC_4FS */
+#define WM8994_AIF1ADC_4FS_SHIFT 15 /* AIF1ADC_4FS */
+#define WM8994_AIF1ADC_4FS_WIDTH 1 /* AIF1ADC_4FS */
+#define WM8994_AIF1ADC1_HPF_CUT_MASK 0x6000 /* AIF1ADC1_HPF_CUT - [14:13] */
+#define WM8994_AIF1ADC1_HPF_CUT_SHIFT 13 /* AIF1ADC1_HPF_CUT - [14:13] */
+#define WM8994_AIF1ADC1_HPF_CUT_WIDTH 2 /* AIF1ADC1_HPF_CUT - [14:13] */
+#define WM8994_AIF1ADC1L_HPF 0x1000 /* AIF1ADC1L_HPF */
+#define WM8994_AIF1ADC1L_HPF_MASK 0x1000 /* AIF1ADC1L_HPF */
+#define WM8994_AIF1ADC1L_HPF_SHIFT 12 /* AIF1ADC1L_HPF */
+#define WM8994_AIF1ADC1L_HPF_WIDTH 1 /* AIF1ADC1L_HPF */
+#define WM8994_AIF1ADC1R_HPF 0x0800 /* AIF1ADC1R_HPF */
+#define WM8994_AIF1ADC1R_HPF_MASK 0x0800 /* AIF1ADC1R_HPF */
+#define WM8994_AIF1ADC1R_HPF_SHIFT 11 /* AIF1ADC1R_HPF */
+#define WM8994_AIF1ADC1R_HPF_WIDTH 1 /* AIF1ADC1R_HPF */
+
+/*
+ * R1041 (0x411) - AIF1 ADC2 Filters
+ */
+#define WM8994_AIF1ADC2_HPF_CUT_MASK 0x6000 /* AIF1ADC2_HPF_CUT - [14:13] */
+#define WM8994_AIF1ADC2_HPF_CUT_SHIFT 13 /* AIF1ADC2_HPF_CUT - [14:13] */
+#define WM8994_AIF1ADC2_HPF_CUT_WIDTH 2 /* AIF1ADC2_HPF_CUT - [14:13] */
+#define WM8994_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */
+#define WM8994_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */
+#define WM8994_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */
+#define WM8994_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */
+#define WM8994_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */
+#define WM8994_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */
+#define WM8994_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */
+#define WM8994_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */
+
+/*
+ * R1056 (0x420) - AIF1 DAC1 Filters (1)
+ */
+#define WM8994_AIF1DAC1_MUTE 0x0200 /* AIF1DAC1_MUTE */
+#define WM8994_AIF1DAC1_MUTE_MASK 0x0200 /* AIF1DAC1_MUTE */
+#define WM8994_AIF1DAC1_MUTE_SHIFT 9 /* AIF1DAC1_MUTE */
+#define WM8994_AIF1DAC1_MUTE_WIDTH 1 /* AIF1DAC1_MUTE */
+#define WM8994_AIF1DAC1_MONO 0x0080 /* AIF1DAC1_MONO */
+#define WM8994_AIF1DAC1_MONO_MASK 0x0080 /* AIF1DAC1_MONO */
+#define WM8994_AIF1DAC1_MONO_SHIFT 7 /* AIF1DAC1_MONO */
+#define WM8994_AIF1DAC1_MONO_WIDTH 1 /* AIF1DAC1_MONO */
+#define WM8994_AIF1DAC1_MUTERATE 0x0020 /* AIF1DAC1_MUTERATE */
+#define WM8994_AIF1DAC1_MUTERATE_MASK 0x0020 /* AIF1DAC1_MUTERATE */
+#define WM8994_AIF1DAC1_MUTERATE_SHIFT 5 /* AIF1DAC1_MUTERATE */
+#define WM8994_AIF1DAC1_MUTERATE_WIDTH 1 /* AIF1DAC1_MUTERATE */
+#define WM8994_AIF1DAC1_UNMUTE_RAMP 0x0010 /* AIF1DAC1_UNMUTE_RAMP */
+#define WM8994_AIF1DAC1_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC1_UNMUTE_RAMP */
+#define WM8994_AIF1DAC1_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC1_UNMUTE_RAMP */
+#define WM8994_AIF1DAC1_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC1_UNMUTE_RAMP */
+#define WM8994_AIF1DAC1_DEEMP_MASK 0x0006 /* AIF1DAC1_DEEMP - [2:1] */
+#define WM8994_AIF1DAC1_DEEMP_SHIFT 1 /* AIF1DAC1_DEEMP - [2:1] */
+#define WM8994_AIF1DAC1_DEEMP_WIDTH 2 /* AIF1DAC1_DEEMP - [2:1] */
+
+/*
+ * R1057 (0x421) - AIF1 DAC1 Filters (2)
+ */
+#define WM8994_AIF1DAC1_3D_GAIN_MASK 0x3E00 /* AIF1DAC1_3D_GAIN - [13:9] */
+#define WM8994_AIF1DAC1_3D_GAIN_SHIFT 9 /* AIF1DAC1_3D_GAIN - [13:9] */
+#define WM8994_AIF1DAC1_3D_GAIN_WIDTH 5 /* AIF1DAC1_3D_GAIN - [13:9] */
+#define WM8994_AIF1DAC1_3D_ENA 0x0100 /* AIF1DAC1_3D_ENA */
+#define WM8994_AIF1DAC1_3D_ENA_MASK 0x0100 /* AIF1DAC1_3D_ENA */
+#define WM8994_AIF1DAC1_3D_ENA_SHIFT 8 /* AIF1DAC1_3D_ENA */
+#define WM8994_AIF1DAC1_3D_ENA_WIDTH 1 /* AIF1DAC1_3D_ENA */
+
+/*
+ * R1058 (0x422) - AIF1 DAC2 Filters (1)
+ */
+#define WM8994_AIF1DAC2_MUTE 0x0200 /* AIF1DAC2_MUTE */
+#define WM8994_AIF1DAC2_MUTE_MASK 0x0200 /* AIF1DAC2_MUTE */
+#define WM8994_AIF1DAC2_MUTE_SHIFT 9 /* AIF1DAC2_MUTE */
+#define WM8994_AIF1DAC2_MUTE_WIDTH 1 /* AIF1DAC2_MUTE */
+#define WM8994_AIF1DAC2_MONO 0x0080 /* AIF1DAC2_MONO */
+#define WM8994_AIF1DAC2_MONO_MASK 0x0080 /* AIF1DAC2_MONO */
+#define WM8994_AIF1DAC2_MONO_SHIFT 7 /* AIF1DAC2_MONO */
+#define WM8994_AIF1DAC2_MONO_WIDTH 1 /* AIF1DAC2_MONO */
+#define WM8994_AIF1DAC2_MUTERATE 0x0020 /* AIF1DAC2_MUTERATE */
+#define WM8994_AIF1DAC2_MUTERATE_MASK 0x0020 /* AIF1DAC2_MUTERATE */
+#define WM8994_AIF1DAC2_MUTERATE_SHIFT 5 /* AIF1DAC2_MUTERATE */
+#define WM8994_AIF1DAC2_MUTERATE_WIDTH 1 /* AIF1DAC2_MUTERATE */
+#define WM8994_AIF1DAC2_UNMUTE_RAMP 0x0010 /* AIF1DAC2_UNMUTE_RAMP */
+#define WM8994_AIF1DAC2_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC2_UNMUTE_RAMP */
+#define WM8994_AIF1DAC2_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC2_UNMUTE_RAMP */
+#define WM8994_AIF1DAC2_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC2_UNMUTE_RAMP */
+#define WM8994_AIF1DAC2_DEEMP_MASK 0x0006 /* AIF1DAC2_DEEMP - [2:1] */
+#define WM8994_AIF1DAC2_DEEMP_SHIFT 1 /* AIF1DAC2_DEEMP - [2:1] */
+#define WM8994_AIF1DAC2_DEEMP_WIDTH 2 /* AIF1DAC2_DEEMP - [2:1] */
+
+/*
+ * R1059 (0x423) - AIF1 DAC2 Filters (2)
+ */
+#define WM8994_AIF1DAC2_3D_GAIN_MASK 0x3E00 /* AIF1DAC2_3D_GAIN - [13:9] */
+#define WM8994_AIF1DAC2_3D_GAIN_SHIFT 9 /* AIF1DAC2_3D_GAIN - [13:9] */
+#define WM8994_AIF1DAC2_3D_GAIN_WIDTH 5 /* AIF1DAC2_3D_GAIN - [13:9] */
+#define WM8994_AIF1DAC2_3D_ENA 0x0100 /* AIF1DAC2_3D_ENA */
+#define WM8994_AIF1DAC2_3D_ENA_MASK 0x0100 /* AIF1DAC2_3D_ENA */
+#define WM8994_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */
+#define WM8994_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */
+
+/*
+ * R1088 (0x440) - AIF1 DRC1 (1)
+ */
+#define WM8994_AIF1DRC1_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF1DRC1_SIG_DET_RMS_SHIFT 11 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF1DRC1_SIG_DET_RMS_WIDTH 5 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF1DRC1_SIG_DET_PK_MASK 0x0600 /* AIF1DRC1_SIG_DET_PK - [10:9] */
+#define WM8994_AIF1DRC1_SIG_DET_PK_SHIFT 9 /* AIF1DRC1_SIG_DET_PK - [10:9] */
+#define WM8994_AIF1DRC1_SIG_DET_PK_WIDTH 2 /* AIF1DRC1_SIG_DET_PK - [10:9] */
+#define WM8994_AIF1DRC1_NG_ENA 0x0100 /* AIF1DRC1_NG_ENA */
+#define WM8994_AIF1DRC1_NG_ENA_MASK 0x0100 /* AIF1DRC1_NG_ENA */
+#define WM8994_AIF1DRC1_NG_ENA_SHIFT 8 /* AIF1DRC1_NG_ENA */
+#define WM8994_AIF1DRC1_NG_ENA_WIDTH 1 /* AIF1DRC1_NG_ENA */
+#define WM8994_AIF1DRC1_SIG_DET_MODE 0x0080 /* AIF1DRC1_SIG_DET_MODE */
+#define WM8994_AIF1DRC1_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC1_SIG_DET_MODE */
+#define WM8994_AIF1DRC1_SIG_DET_MODE_SHIFT 7 /* AIF1DRC1_SIG_DET_MODE */
+#define WM8994_AIF1DRC1_SIG_DET_MODE_WIDTH 1 /* AIF1DRC1_SIG_DET_MODE */
+#define WM8994_AIF1DRC1_SIG_DET 0x0040 /* AIF1DRC1_SIG_DET */
+#define WM8994_AIF1DRC1_SIG_DET_MASK 0x0040 /* AIF1DRC1_SIG_DET */
+#define WM8994_AIF1DRC1_SIG_DET_SHIFT 6 /* AIF1DRC1_SIG_DET */
+#define WM8994_AIF1DRC1_SIG_DET_WIDTH 1 /* AIF1DRC1_SIG_DET */
+#define WM8994_AIF1DRC1_KNEE2_OP_ENA 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */
+#define WM8994_AIF1DRC1_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */
+#define WM8994_AIF1DRC1_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC1_KNEE2_OP_ENA */
+#define WM8994_AIF1DRC1_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC1_KNEE2_OP_ENA */
+#define WM8994_AIF1DRC1_QR 0x0010 /* AIF1DRC1_QR */
+#define WM8994_AIF1DRC1_QR_MASK 0x0010 /* AIF1DRC1_QR */
+#define WM8994_AIF1DRC1_QR_SHIFT 4 /* AIF1DRC1_QR */
+#define WM8994_AIF1DRC1_QR_WIDTH 1 /* AIF1DRC1_QR */
+#define WM8994_AIF1DRC1_ANTICLIP 0x0008 /* AIF1DRC1_ANTICLIP */
+#define WM8994_AIF1DRC1_ANTICLIP_MASK 0x0008 /* AIF1DRC1_ANTICLIP */
+#define WM8994_AIF1DRC1_ANTICLIP_SHIFT 3 /* AIF1DRC1_ANTICLIP */
+#define WM8994_AIF1DRC1_ANTICLIP_WIDTH 1 /* AIF1DRC1_ANTICLIP */
+#define WM8994_AIF1DAC1_DRC_ENA 0x0004 /* AIF1DAC1_DRC_ENA */
+#define WM8994_AIF1DAC1_DRC_ENA_MASK 0x0004 /* AIF1DAC1_DRC_ENA */
+#define WM8994_AIF1DAC1_DRC_ENA_SHIFT 2 /* AIF1DAC1_DRC_ENA */
+#define WM8994_AIF1DAC1_DRC_ENA_WIDTH 1 /* AIF1DAC1_DRC_ENA */
+#define WM8994_AIF1ADC1L_DRC_ENA 0x0002 /* AIF1ADC1L_DRC_ENA */
+#define WM8994_AIF1ADC1L_DRC_ENA_MASK 0x0002 /* AIF1ADC1L_DRC_ENA */
+#define WM8994_AIF1ADC1L_DRC_ENA_SHIFT 1 /* AIF1ADC1L_DRC_ENA */
+#define WM8994_AIF1ADC1L_DRC_ENA_WIDTH 1 /* AIF1ADC1L_DRC_ENA */
+#define WM8994_AIF1ADC1R_DRC_ENA 0x0001 /* AIF1ADC1R_DRC_ENA */
+#define WM8994_AIF1ADC1R_DRC_ENA_MASK 0x0001 /* AIF1ADC1R_DRC_ENA */
+#define WM8994_AIF1ADC1R_DRC_ENA_SHIFT 0 /* AIF1ADC1R_DRC_ENA */
+#define WM8994_AIF1ADC1R_DRC_ENA_WIDTH 1 /* AIF1ADC1R_DRC_ENA */
+
+/*
+ * R1089 (0x441) - AIF1 DRC1 (2)
+ */
+#define WM8994_AIF1DRC1_ATK_MASK 0x1E00 /* AIF1DRC1_ATK - [12:9] */
+#define WM8994_AIF1DRC1_ATK_SHIFT 9 /* AIF1DRC1_ATK - [12:9] */
+#define WM8994_AIF1DRC1_ATK_WIDTH 4 /* AIF1DRC1_ATK - [12:9] */
+#define WM8994_AIF1DRC1_DCY_MASK 0x01E0 /* AIF1DRC1_DCY - [8:5] */
+#define WM8994_AIF1DRC1_DCY_SHIFT 5 /* AIF1DRC1_DCY - [8:5] */
+#define WM8994_AIF1DRC1_DCY_WIDTH 4 /* AIF1DRC1_DCY - [8:5] */
+#define WM8994_AIF1DRC1_MINGAIN_MASK 0x001C /* AIF1DRC1_MINGAIN - [4:2] */
+#define WM8994_AIF1DRC1_MINGAIN_SHIFT 2 /* AIF1DRC1_MINGAIN - [4:2] */
+#define WM8994_AIF1DRC1_MINGAIN_WIDTH 3 /* AIF1DRC1_MINGAIN - [4:2] */
+#define WM8994_AIF1DRC1_MAXGAIN_MASK 0x0003 /* AIF1DRC1_MAXGAIN - [1:0] */
+#define WM8994_AIF1DRC1_MAXGAIN_SHIFT 0 /* AIF1DRC1_MAXGAIN - [1:0] */
+#define WM8994_AIF1DRC1_MAXGAIN_WIDTH 2 /* AIF1DRC1_MAXGAIN - [1:0] */
+
+/*
+ * R1090 (0x442) - AIF1 DRC1 (3)
+ */
+#define WM8994_AIF1DRC1_NG_MINGAIN_MASK 0xF000 /* AIF1DRC1_NG_MINGAIN - [15:12] */
+#define WM8994_AIF1DRC1_NG_MINGAIN_SHIFT 12 /* AIF1DRC1_NG_MINGAIN - [15:12] */
+#define WM8994_AIF1DRC1_NG_MINGAIN_WIDTH 4 /* AIF1DRC1_NG_MINGAIN - [15:12] */
+#define WM8994_AIF1DRC1_NG_EXP_MASK 0x0C00 /* AIF1DRC1_NG_EXP - [11:10] */
+#define WM8994_AIF1DRC1_NG_EXP_SHIFT 10 /* AIF1DRC1_NG_EXP - [11:10] */
+#define WM8994_AIF1DRC1_NG_EXP_WIDTH 2 /* AIF1DRC1_NG_EXP - [11:10] */
+#define WM8994_AIF1DRC1_QR_THR_MASK 0x0300 /* AIF1DRC1_QR_THR - [9:8] */
+#define WM8994_AIF1DRC1_QR_THR_SHIFT 8 /* AIF1DRC1_QR_THR - [9:8] */
+#define WM8994_AIF1DRC1_QR_THR_WIDTH 2 /* AIF1DRC1_QR_THR - [9:8] */
+#define WM8994_AIF1DRC1_QR_DCY_MASK 0x00C0 /* AIF1DRC1_QR_DCY - [7:6] */
+#define WM8994_AIF1DRC1_QR_DCY_SHIFT 6 /* AIF1DRC1_QR_DCY - [7:6] */
+#define WM8994_AIF1DRC1_QR_DCY_WIDTH 2 /* AIF1DRC1_QR_DCY - [7:6] */
+#define WM8994_AIF1DRC1_HI_COMP_MASK 0x0038 /* AIF1DRC1_HI_COMP - [5:3] */
+#define WM8994_AIF1DRC1_HI_COMP_SHIFT 3 /* AIF1DRC1_HI_COMP - [5:3] */
+#define WM8994_AIF1DRC1_HI_COMP_WIDTH 3 /* AIF1DRC1_HI_COMP - [5:3] */
+#define WM8994_AIF1DRC1_LO_COMP_MASK 0x0007 /* AIF1DRC1_LO_COMP - [2:0] */
+#define WM8994_AIF1DRC1_LO_COMP_SHIFT 0 /* AIF1DRC1_LO_COMP - [2:0] */
+#define WM8994_AIF1DRC1_LO_COMP_WIDTH 3 /* AIF1DRC1_LO_COMP - [2:0] */
+
+/*
+ * R1091 (0x443) - AIF1 DRC1 (4)
+ */
+#define WM8994_AIF1DRC1_KNEE_IP_MASK 0x07E0 /* AIF1DRC1_KNEE_IP - [10:5] */
+#define WM8994_AIF1DRC1_KNEE_IP_SHIFT 5 /* AIF1DRC1_KNEE_IP - [10:5] */
+#define WM8994_AIF1DRC1_KNEE_IP_WIDTH 6 /* AIF1DRC1_KNEE_IP - [10:5] */
+#define WM8994_AIF1DRC1_KNEE_OP_MASK 0x001F /* AIF1DRC1_KNEE_OP - [4:0] */
+#define WM8994_AIF1DRC1_KNEE_OP_SHIFT 0 /* AIF1DRC1_KNEE_OP - [4:0] */
+#define WM8994_AIF1DRC1_KNEE_OP_WIDTH 5 /* AIF1DRC1_KNEE_OP - [4:0] */
+
+/*
+ * R1092 (0x444) - AIF1 DRC1 (5)
+ */
+#define WM8994_AIF1DRC1_KNEE2_IP_MASK 0x03E0 /* AIF1DRC1_KNEE2_IP - [9:5] */
+#define WM8994_AIF1DRC1_KNEE2_IP_SHIFT 5 /* AIF1DRC1_KNEE2_IP - [9:5] */
+#define WM8994_AIF1DRC1_KNEE2_IP_WIDTH 5 /* AIF1DRC1_KNEE2_IP - [9:5] */
+#define WM8994_AIF1DRC1_KNEE2_OP_MASK 0x001F /* AIF1DRC1_KNEE2_OP - [4:0] */
+#define WM8994_AIF1DRC1_KNEE2_OP_SHIFT 0 /* AIF1DRC1_KNEE2_OP - [4:0] */
+#define WM8994_AIF1DRC1_KNEE2_OP_WIDTH 5 /* AIF1DRC1_KNEE2_OP - [4:0] */
+
+/*
+ * R1104 (0x450) - AIF1 DRC2 (1)
+ */
+#define WM8994_AIF1DRC2_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF1DRC2_SIG_DET_RMS_SHIFT 11 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF1DRC2_SIG_DET_RMS_WIDTH 5 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF1DRC2_SIG_DET_PK_MASK 0x0600 /* AIF1DRC2_SIG_DET_PK - [10:9] */
+#define WM8994_AIF1DRC2_SIG_DET_PK_SHIFT 9 /* AIF1DRC2_SIG_DET_PK - [10:9] */
+#define WM8994_AIF1DRC2_SIG_DET_PK_WIDTH 2 /* AIF1DRC2_SIG_DET_PK - [10:9] */
+#define WM8994_AIF1DRC2_NG_ENA 0x0100 /* AIF1DRC2_NG_ENA */
+#define WM8994_AIF1DRC2_NG_ENA_MASK 0x0100 /* AIF1DRC2_NG_ENA */
+#define WM8994_AIF1DRC2_NG_ENA_SHIFT 8 /* AIF1DRC2_NG_ENA */
+#define WM8994_AIF1DRC2_NG_ENA_WIDTH 1 /* AIF1DRC2_NG_ENA */
+#define WM8994_AIF1DRC2_SIG_DET_MODE 0x0080 /* AIF1DRC2_SIG_DET_MODE */
+#define WM8994_AIF1DRC2_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC2_SIG_DET_MODE */
+#define WM8994_AIF1DRC2_SIG_DET_MODE_SHIFT 7 /* AIF1DRC2_SIG_DET_MODE */
+#define WM8994_AIF1DRC2_SIG_DET_MODE_WIDTH 1 /* AIF1DRC2_SIG_DET_MODE */
+#define WM8994_AIF1DRC2_SIG_DET 0x0040 /* AIF1DRC2_SIG_DET */
+#define WM8994_AIF1DRC2_SIG_DET_MASK 0x0040 /* AIF1DRC2_SIG_DET */
+#define WM8994_AIF1DRC2_SIG_DET_SHIFT 6 /* AIF1DRC2_SIG_DET */
+#define WM8994_AIF1DRC2_SIG_DET_WIDTH 1 /* AIF1DRC2_SIG_DET */
+#define WM8994_AIF1DRC2_KNEE2_OP_ENA 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */
+#define WM8994_AIF1DRC2_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */
+#define WM8994_AIF1DRC2_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC2_KNEE2_OP_ENA */
+#define WM8994_AIF1DRC2_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC2_KNEE2_OP_ENA */
+#define WM8994_AIF1DRC2_QR 0x0010 /* AIF1DRC2_QR */
+#define WM8994_AIF1DRC2_QR_MASK 0x0010 /* AIF1DRC2_QR */
+#define WM8994_AIF1DRC2_QR_SHIFT 4 /* AIF1DRC2_QR */
+#define WM8994_AIF1DRC2_QR_WIDTH 1 /* AIF1DRC2_QR */
+#define WM8994_AIF1DRC2_ANTICLIP 0x0008 /* AIF1DRC2_ANTICLIP */
+#define WM8994_AIF1DRC2_ANTICLIP_MASK 0x0008 /* AIF1DRC2_ANTICLIP */
+#define WM8994_AIF1DRC2_ANTICLIP_SHIFT 3 /* AIF1DRC2_ANTICLIP */
+#define WM8994_AIF1DRC2_ANTICLIP_WIDTH 1 /* AIF1DRC2_ANTICLIP */
+#define WM8994_AIF1DAC2_DRC_ENA 0x0004 /* AIF1DAC2_DRC_ENA */
+#define WM8994_AIF1DAC2_DRC_ENA_MASK 0x0004 /* AIF1DAC2_DRC_ENA */
+#define WM8994_AIF1DAC2_DRC_ENA_SHIFT 2 /* AIF1DAC2_DRC_ENA */
+#define WM8994_AIF1DAC2_DRC_ENA_WIDTH 1 /* AIF1DAC2_DRC_ENA */
+#define WM8994_AIF1ADC2L_DRC_ENA 0x0002 /* AIF1ADC2L_DRC_ENA */
+#define WM8994_AIF1ADC2L_DRC_ENA_MASK 0x0002 /* AIF1ADC2L_DRC_ENA */
+#define WM8994_AIF1ADC2L_DRC_ENA_SHIFT 1 /* AIF1ADC2L_DRC_ENA */
+#define WM8994_AIF1ADC2L_DRC_ENA_WIDTH 1 /* AIF1ADC2L_DRC_ENA */
+#define WM8994_AIF1ADC2R_DRC_ENA 0x0001 /* AIF1ADC2R_DRC_ENA */
+#define WM8994_AIF1ADC2R_DRC_ENA_MASK 0x0001 /* AIF1ADC2R_DRC_ENA */
+#define WM8994_AIF1ADC2R_DRC_ENA_SHIFT 0 /* AIF1ADC2R_DRC_ENA */
+#define WM8994_AIF1ADC2R_DRC_ENA_WIDTH 1 /* AIF1ADC2R_DRC_ENA */
+
+/*
+ * R1105 (0x451) - AIF1 DRC2 (2)
+ */
+#define WM8994_AIF1DRC2_ATK_MASK 0x1E00 /* AIF1DRC2_ATK - [12:9] */
+#define WM8994_AIF1DRC2_ATK_SHIFT 9 /* AIF1DRC2_ATK - [12:9] */
+#define WM8994_AIF1DRC2_ATK_WIDTH 4 /* AIF1DRC2_ATK - [12:9] */
+#define WM8994_AIF1DRC2_DCY_MASK 0x01E0 /* AIF1DRC2_DCY - [8:5] */
+#define WM8994_AIF1DRC2_DCY_SHIFT 5 /* AIF1DRC2_DCY - [8:5] */
+#define WM8994_AIF1DRC2_DCY_WIDTH 4 /* AIF1DRC2_DCY - [8:5] */
+#define WM8994_AIF1DRC2_MINGAIN_MASK 0x001C /* AIF1DRC2_MINGAIN - [4:2] */
+#define WM8994_AIF1DRC2_MINGAIN_SHIFT 2 /* AIF1DRC2_MINGAIN - [4:2] */
+#define WM8994_AIF1DRC2_MINGAIN_WIDTH 3 /* AIF1DRC2_MINGAIN - [4:2] */
+#define WM8994_AIF1DRC2_MAXGAIN_MASK 0x0003 /* AIF1DRC2_MAXGAIN - [1:0] */
+#define WM8994_AIF1DRC2_MAXGAIN_SHIFT 0 /* AIF1DRC2_MAXGAIN - [1:0] */
+#define WM8994_AIF1DRC2_MAXGAIN_WIDTH 2 /* AIF1DRC2_MAXGAIN - [1:0] */
+
+/*
+ * R1106 (0x452) - AIF1 DRC2 (3)
+ */
+#define WM8994_AIF1DRC2_NG_MINGAIN_MASK 0xF000 /* AIF1DRC2_NG_MINGAIN - [15:12] */
+#define WM8994_AIF1DRC2_NG_MINGAIN_SHIFT 12 /* AIF1DRC2_NG_MINGAIN - [15:12] */
+#define WM8994_AIF1DRC2_NG_MINGAIN_WIDTH 4 /* AIF1DRC2_NG_MINGAIN - [15:12] */
+#define WM8994_AIF1DRC2_NG_EXP_MASK 0x0C00 /* AIF1DRC2_NG_EXP - [11:10] */
+#define WM8994_AIF1DRC2_NG_EXP_SHIFT 10 /* AIF1DRC2_NG_EXP - [11:10] */
+#define WM8994_AIF1DRC2_NG_EXP_WIDTH 2 /* AIF1DRC2_NG_EXP - [11:10] */
+#define WM8994_AIF1DRC2_QR_THR_MASK 0x0300 /* AIF1DRC2_QR_THR - [9:8] */
+#define WM8994_AIF1DRC2_QR_THR_SHIFT 8 /* AIF1DRC2_QR_THR - [9:8] */
+#define WM8994_AIF1DRC2_QR_THR_WIDTH 2 /* AIF1DRC2_QR_THR - [9:8] */
+#define WM8994_AIF1DRC2_QR_DCY_MASK 0x00C0 /* AIF1DRC2_QR_DCY - [7:6] */
+#define WM8994_AIF1DRC2_QR_DCY_SHIFT 6 /* AIF1DRC2_QR_DCY - [7:6] */
+#define WM8994_AIF1DRC2_QR_DCY_WIDTH 2 /* AIF1DRC2_QR_DCY - [7:6] */
+#define WM8994_AIF1DRC2_HI_COMP_MASK 0x0038 /* AIF1DRC2_HI_COMP - [5:3] */
+#define WM8994_AIF1DRC2_HI_COMP_SHIFT 3 /* AIF1DRC2_HI_COMP - [5:3] */
+#define WM8994_AIF1DRC2_HI_COMP_WIDTH 3 /* AIF1DRC2_HI_COMP - [5:3] */
+#define WM8994_AIF1DRC2_LO_COMP_MASK 0x0007 /* AIF1DRC2_LO_COMP - [2:0] */
+#define WM8994_AIF1DRC2_LO_COMP_SHIFT 0 /* AIF1DRC2_LO_COMP - [2:0] */
+#define WM8994_AIF1DRC2_LO_COMP_WIDTH 3 /* AIF1DRC2_LO_COMP - [2:0] */
+
+/*
+ * R1107 (0x453) - AIF1 DRC2 (4)
+ */
+#define WM8994_AIF1DRC2_KNEE_IP_MASK 0x07E0 /* AIF1DRC2_KNEE_IP - [10:5] */
+#define WM8994_AIF1DRC2_KNEE_IP_SHIFT 5 /* AIF1DRC2_KNEE_IP - [10:5] */
+#define WM8994_AIF1DRC2_KNEE_IP_WIDTH 6 /* AIF1DRC2_KNEE_IP - [10:5] */
+#define WM8994_AIF1DRC2_KNEE_OP_MASK 0x001F /* AIF1DRC2_KNEE_OP - [4:0] */
+#define WM8994_AIF1DRC2_KNEE_OP_SHIFT 0 /* AIF1DRC2_KNEE_OP - [4:0] */
+#define WM8994_AIF1DRC2_KNEE_OP_WIDTH 5 /* AIF1DRC2_KNEE_OP - [4:0] */
+
+/*
+ * R1108 (0x454) - AIF1 DRC2 (5)
+ */
+#define WM8994_AIF1DRC2_KNEE2_IP_MASK 0x03E0 /* AIF1DRC2_KNEE2_IP - [9:5] */
+#define WM8994_AIF1DRC2_KNEE2_IP_SHIFT 5 /* AIF1DRC2_KNEE2_IP - [9:5] */
+#define WM8994_AIF1DRC2_KNEE2_IP_WIDTH 5 /* AIF1DRC2_KNEE2_IP - [9:5] */
+#define WM8994_AIF1DRC2_KNEE2_OP_MASK 0x001F /* AIF1DRC2_KNEE2_OP - [4:0] */
+#define WM8994_AIF1DRC2_KNEE2_OP_SHIFT 0 /* AIF1DRC2_KNEE2_OP - [4:0] */
+#define WM8994_AIF1DRC2_KNEE2_OP_WIDTH 5 /* AIF1DRC2_KNEE2_OP - [4:0] */
+
+/*
+ * R1152 (0x480) - AIF1 DAC1 EQ Gains (1)
+ */
+#define WM8994_AIF1DAC1_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF1DAC1_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF1DAC1_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF1DAC1_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF1DAC1_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF1DAC1_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF1DAC1_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF1DAC1_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF1DAC1_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF1DAC1_EQ_ENA 0x0001 /* AIF1DAC1_EQ_ENA */
+#define WM8994_AIF1DAC1_EQ_ENA_MASK 0x0001 /* AIF1DAC1_EQ_ENA */
+#define WM8994_AIF1DAC1_EQ_ENA_SHIFT 0 /* AIF1DAC1_EQ_ENA */
+#define WM8994_AIF1DAC1_EQ_ENA_WIDTH 1 /* AIF1DAC1_EQ_ENA */
+
+/*
+ * R1153 (0x481) - AIF1 DAC1 EQ Gains (2)
+ */
+#define WM8994_AIF1DAC1_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF1DAC1_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF1DAC1_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF1DAC1_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
+#define WM8994_AIF1DAC1_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
+#define WM8994_AIF1DAC1_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
+
+/*
+ * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A
+ */
+#define WM8994_AIF1DAC1_EQ_B1_A_MASK 0xFFFF /* AIF1DAC1_EQ_B1_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B1_A_SHIFT 0 /* AIF1DAC1_EQ_B1_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B1_A_WIDTH 16 /* AIF1DAC1_EQ_B1_A - [15:0] */
+
+/*
+ * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B
+ */
+#define WM8994_AIF1DAC1_EQ_B1_B_MASK 0xFFFF /* AIF1DAC1_EQ_B1_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B1_B_SHIFT 0 /* AIF1DAC1_EQ_B1_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B1_B_WIDTH 16 /* AIF1DAC1_EQ_B1_B - [15:0] */
+
+/*
+ * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG
+ */
+#define WM8994_AIF1DAC1_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B1_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B1_PG_SHIFT 0 /* AIF1DAC1_EQ_B1_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B1_PG_WIDTH 16 /* AIF1DAC1_EQ_B1_PG - [15:0] */
+
+/*
+ * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A
+ */
+#define WM8994_AIF1DAC1_EQ_B2_A_MASK 0xFFFF /* AIF1DAC1_EQ_B2_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B2_A_SHIFT 0 /* AIF1DAC1_EQ_B2_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B2_A_WIDTH 16 /* AIF1DAC1_EQ_B2_A - [15:0] */
+
+/*
+ * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B
+ */
+#define WM8994_AIF1DAC1_EQ_B2_B_MASK 0xFFFF /* AIF1DAC1_EQ_B2_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B2_B_SHIFT 0 /* AIF1DAC1_EQ_B2_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B2_B_WIDTH 16 /* AIF1DAC1_EQ_B2_B - [15:0] */
+
+/*
+ * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C
+ */
+#define WM8994_AIF1DAC1_EQ_B2_C_MASK 0xFFFF /* AIF1DAC1_EQ_B2_C - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B2_C_SHIFT 0 /* AIF1DAC1_EQ_B2_C - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B2_C_WIDTH 16 /* AIF1DAC1_EQ_B2_C - [15:0] */
+
+/*
+ * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG
+ */
+#define WM8994_AIF1DAC1_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B2_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B2_PG_SHIFT 0 /* AIF1DAC1_EQ_B2_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B2_PG_WIDTH 16 /* AIF1DAC1_EQ_B2_PG - [15:0] */
+
+/*
+ * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A
+ */
+#define WM8994_AIF1DAC1_EQ_B3_A_MASK 0xFFFF /* AIF1DAC1_EQ_B3_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B3_A_SHIFT 0 /* AIF1DAC1_EQ_B3_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B3_A_WIDTH 16 /* AIF1DAC1_EQ_B3_A - [15:0] */
+
+/*
+ * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B
+ */
+#define WM8994_AIF1DAC1_EQ_B3_B_MASK 0xFFFF /* AIF1DAC1_EQ_B3_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B3_B_SHIFT 0 /* AIF1DAC1_EQ_B3_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B3_B_WIDTH 16 /* AIF1DAC1_EQ_B3_B - [15:0] */
+
+/*
+ * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C
+ */
+#define WM8994_AIF1DAC1_EQ_B3_C_MASK 0xFFFF /* AIF1DAC1_EQ_B3_C - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B3_C_SHIFT 0 /* AIF1DAC1_EQ_B3_C - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B3_C_WIDTH 16 /* AIF1DAC1_EQ_B3_C - [15:0] */
+
+/*
+ * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG
+ */
+#define WM8994_AIF1DAC1_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B3_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B3_PG_SHIFT 0 /* AIF1DAC1_EQ_B3_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B3_PG_WIDTH 16 /* AIF1DAC1_EQ_B3_PG - [15:0] */
+
+/*
+ * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A
+ */
+#define WM8994_AIF1DAC1_EQ_B4_A_MASK 0xFFFF /* AIF1DAC1_EQ_B4_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B4_A_SHIFT 0 /* AIF1DAC1_EQ_B4_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B4_A_WIDTH 16 /* AIF1DAC1_EQ_B4_A - [15:0] */
+
+/*
+ * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B
+ */
+#define WM8994_AIF1DAC1_EQ_B4_B_MASK 0xFFFF /* AIF1DAC1_EQ_B4_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B4_B_SHIFT 0 /* AIF1DAC1_EQ_B4_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B4_B_WIDTH 16 /* AIF1DAC1_EQ_B4_B - [15:0] */
+
+/*
+ * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C
+ */
+#define WM8994_AIF1DAC1_EQ_B4_C_MASK 0xFFFF /* AIF1DAC1_EQ_B4_C - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B4_C_SHIFT 0 /* AIF1DAC1_EQ_B4_C - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B4_C_WIDTH 16 /* AIF1DAC1_EQ_B4_C - [15:0] */
+
+/*
+ * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG
+ */
+#define WM8994_AIF1DAC1_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B4_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B4_PG_SHIFT 0 /* AIF1DAC1_EQ_B4_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B4_PG_WIDTH 16 /* AIF1DAC1_EQ_B4_PG - [15:0] */
+
+/*
+ * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A
+ */
+#define WM8994_AIF1DAC1_EQ_B5_A_MASK 0xFFFF /* AIF1DAC1_EQ_B5_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B5_A_SHIFT 0 /* AIF1DAC1_EQ_B5_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B5_A_WIDTH 16 /* AIF1DAC1_EQ_B5_A - [15:0] */
+
+/*
+ * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B
+ */
+#define WM8994_AIF1DAC1_EQ_B5_B_MASK 0xFFFF /* AIF1DAC1_EQ_B5_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B5_B_SHIFT 0 /* AIF1DAC1_EQ_B5_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B5_B_WIDTH 16 /* AIF1DAC1_EQ_B5_B - [15:0] */
+
+/*
+ * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG
+ */
+#define WM8994_AIF1DAC1_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B5_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B5_PG_SHIFT 0 /* AIF1DAC1_EQ_B5_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B5_PG_WIDTH 16 /* AIF1DAC1_EQ_B5_PG - [15:0] */
+
+/*
+ * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1)
+ */
+#define WM8994_AIF1DAC2_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF1DAC2_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF1DAC2_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF1DAC2_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF1DAC2_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF1DAC2_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF1DAC2_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF1DAC2_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF1DAC2_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF1DAC2_EQ_ENA 0x0001 /* AIF1DAC2_EQ_ENA */
+#define WM8994_AIF1DAC2_EQ_ENA_MASK 0x0001 /* AIF1DAC2_EQ_ENA */
+#define WM8994_AIF1DAC2_EQ_ENA_SHIFT 0 /* AIF1DAC2_EQ_ENA */
+#define WM8994_AIF1DAC2_EQ_ENA_WIDTH 1 /* AIF1DAC2_EQ_ENA */
+
+/*
+ * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2)
+ */
+#define WM8994_AIF1DAC2_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF1DAC2_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF1DAC2_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF1DAC2_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
+#define WM8994_AIF1DAC2_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
+#define WM8994_AIF1DAC2_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
+
+/*
+ * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A
+ */
+#define WM8994_AIF1DAC2_EQ_B1_A_MASK 0xFFFF /* AIF1DAC2_EQ_B1_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B1_A_SHIFT 0 /* AIF1DAC2_EQ_B1_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B1_A_WIDTH 16 /* AIF1DAC2_EQ_B1_A - [15:0] */
+
+/*
+ * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B
+ */
+#define WM8994_AIF1DAC2_EQ_B1_B_MASK 0xFFFF /* AIF1DAC2_EQ_B1_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B1_B_SHIFT 0 /* AIF1DAC2_EQ_B1_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B1_B_WIDTH 16 /* AIF1DAC2_EQ_B1_B - [15:0] */
+
+/*
+ * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG
+ */
+#define WM8994_AIF1DAC2_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B1_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B1_PG_SHIFT 0 /* AIF1DAC2_EQ_B1_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B1_PG_WIDTH 16 /* AIF1DAC2_EQ_B1_PG - [15:0] */
+
+/*
+ * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A
+ */
+#define WM8994_AIF1DAC2_EQ_B2_A_MASK 0xFFFF /* AIF1DAC2_EQ_B2_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B2_A_SHIFT 0 /* AIF1DAC2_EQ_B2_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B2_A_WIDTH 16 /* AIF1DAC2_EQ_B2_A - [15:0] */
+
+/*
+ * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B
+ */
+#define WM8994_AIF1DAC2_EQ_B2_B_MASK 0xFFFF /* AIF1DAC2_EQ_B2_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B2_B_SHIFT 0 /* AIF1DAC2_EQ_B2_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B2_B_WIDTH 16 /* AIF1DAC2_EQ_B2_B - [15:0] */
+
+/*
+ * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C
+ */
+#define WM8994_AIF1DAC2_EQ_B2_C_MASK 0xFFFF /* AIF1DAC2_EQ_B2_C - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B2_C_SHIFT 0 /* AIF1DAC2_EQ_B2_C - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B2_C_WIDTH 16 /* AIF1DAC2_EQ_B2_C - [15:0] */
+
+/*
+ * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG
+ */
+#define WM8994_AIF1DAC2_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B2_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B2_PG_SHIFT 0 /* AIF1DAC2_EQ_B2_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B2_PG_WIDTH 16 /* AIF1DAC2_EQ_B2_PG - [15:0] */
+
+/*
+ * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A
+ */
+#define WM8994_AIF1DAC2_EQ_B3_A_MASK 0xFFFF /* AIF1DAC2_EQ_B3_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B3_A_SHIFT 0 /* AIF1DAC2_EQ_B3_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B3_A_WIDTH 16 /* AIF1DAC2_EQ_B3_A - [15:0] */
+
+/*
+ * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B
+ */
+#define WM8994_AIF1DAC2_EQ_B3_B_MASK 0xFFFF /* AIF1DAC2_EQ_B3_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B3_B_SHIFT 0 /* AIF1DAC2_EQ_B3_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B3_B_WIDTH 16 /* AIF1DAC2_EQ_B3_B - [15:0] */
+
+/*
+ * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C
+ */
+#define WM8994_AIF1DAC2_EQ_B3_C_MASK 0xFFFF /* AIF1DAC2_EQ_B3_C - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B3_C_SHIFT 0 /* AIF1DAC2_EQ_B3_C - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B3_C_WIDTH 16 /* AIF1DAC2_EQ_B3_C - [15:0] */
+
+/*
+ * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG
+ */
+#define WM8994_AIF1DAC2_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B3_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B3_PG_SHIFT 0 /* AIF1DAC2_EQ_B3_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B3_PG_WIDTH 16 /* AIF1DAC2_EQ_B3_PG - [15:0] */
+
+/*
+ * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A
+ */
+#define WM8994_AIF1DAC2_EQ_B4_A_MASK 0xFFFF /* AIF1DAC2_EQ_B4_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B4_A_SHIFT 0 /* AIF1DAC2_EQ_B4_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B4_A_WIDTH 16 /* AIF1DAC2_EQ_B4_A - [15:0] */
+
+/*
+ * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B
+ */
+#define WM8994_AIF1DAC2_EQ_B4_B_MASK 0xFFFF /* AIF1DAC2_EQ_B4_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B4_B_SHIFT 0 /* AIF1DAC2_EQ_B4_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B4_B_WIDTH 16 /* AIF1DAC2_EQ_B4_B - [15:0] */
+
+/*
+ * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C
+ */
+#define WM8994_AIF1DAC2_EQ_B4_C_MASK 0xFFFF /* AIF1DAC2_EQ_B4_C - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B4_C_SHIFT 0 /* AIF1DAC2_EQ_B4_C - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B4_C_WIDTH 16 /* AIF1DAC2_EQ_B4_C - [15:0] */
+
+/*
+ * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG
+ */
+#define WM8994_AIF1DAC2_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B4_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B4_PG_SHIFT 0 /* AIF1DAC2_EQ_B4_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B4_PG_WIDTH 16 /* AIF1DAC2_EQ_B4_PG - [15:0] */
+
+/*
+ * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A
+ */
+#define WM8994_AIF1DAC2_EQ_B5_A_MASK 0xFFFF /* AIF1DAC2_EQ_B5_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B5_A_SHIFT 0 /* AIF1DAC2_EQ_B5_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B5_A_WIDTH 16 /* AIF1DAC2_EQ_B5_A - [15:0] */
+
+/*
+ * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B
+ */
+#define WM8994_AIF1DAC2_EQ_B5_B_MASK 0xFFFF /* AIF1DAC2_EQ_B5_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B5_B_SHIFT 0 /* AIF1DAC2_EQ_B5_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B5_B_WIDTH 16 /* AIF1DAC2_EQ_B5_B - [15:0] */
+
+/*
+ * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG
+ */
+#define WM8994_AIF1DAC2_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B5_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B5_PG_SHIFT 0 /* AIF1DAC2_EQ_B5_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B5_PG_WIDTH 16 /* AIF1DAC2_EQ_B5_PG - [15:0] */
+
+/*
+ * R1280 (0x500) - AIF2 ADC Left Volume
+ */
+#define WM8994_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */
+#define WM8994_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */
+#define WM8994_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */
+#define WM8994_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */
+#define WM8994_AIF2ADCL_VOL_MASK 0x00FF /* AIF2ADCL_VOL - [7:0] */
+#define WM8994_AIF2ADCL_VOL_SHIFT 0 /* AIF2ADCL_VOL - [7:0] */
+#define WM8994_AIF2ADCL_VOL_WIDTH 8 /* AIF2ADCL_VOL - [7:0] */
+
+/*
+ * R1281 (0x501) - AIF2 ADC Right Volume
+ */
+#define WM8994_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */
+#define WM8994_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */
+#define WM8994_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */
+#define WM8994_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */
+#define WM8994_AIF2ADCR_VOL_MASK 0x00FF /* AIF2ADCR_VOL - [7:0] */
+#define WM8994_AIF2ADCR_VOL_SHIFT 0 /* AIF2ADCR_VOL - [7:0] */
+#define WM8994_AIF2ADCR_VOL_WIDTH 8 /* AIF2ADCR_VOL - [7:0] */
+
+/*
+ * R1282 (0x502) - AIF2 DAC Left Volume
+ */
+#define WM8994_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */
+#define WM8994_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */
+#define WM8994_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */
+#define WM8994_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */
+#define WM8994_AIF2DACL_VOL_MASK 0x00FF /* AIF2DACL_VOL - [7:0] */
+#define WM8994_AIF2DACL_VOL_SHIFT 0 /* AIF2DACL_VOL - [7:0] */
+#define WM8994_AIF2DACL_VOL_WIDTH 8 /* AIF2DACL_VOL - [7:0] */
+
+/*
+ * R1283 (0x503) - AIF2 DAC Right Volume
+ */
+#define WM8994_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */
+#define WM8994_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */
+#define WM8994_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */
+#define WM8994_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */
+#define WM8994_AIF2DACR_VOL_MASK 0x00FF /* AIF2DACR_VOL - [7:0] */
+#define WM8994_AIF2DACR_VOL_SHIFT 0 /* AIF2DACR_VOL - [7:0] */
+#define WM8994_AIF2DACR_VOL_WIDTH 8 /* AIF2DACR_VOL - [7:0] */
+
+/*
+ * R1296 (0x510) - AIF2 ADC Filters
+ */
+#define WM8994_AIF2ADC_4FS 0x8000 /* AIF2ADC_4FS */
+#define WM8994_AIF2ADC_4FS_MASK 0x8000 /* AIF2ADC_4FS */
+#define WM8994_AIF2ADC_4FS_SHIFT 15 /* AIF2ADC_4FS */
+#define WM8994_AIF2ADC_4FS_WIDTH 1 /* AIF2ADC_4FS */
+#define WM8994_AIF2ADC_HPF_CUT_MASK 0x6000 /* AIF2ADC_HPF_CUT - [14:13] */
+#define WM8994_AIF2ADC_HPF_CUT_SHIFT 13 /* AIF2ADC_HPF_CUT - [14:13] */
+#define WM8994_AIF2ADC_HPF_CUT_WIDTH 2 /* AIF2ADC_HPF_CUT - [14:13] */
+#define WM8994_AIF2ADCL_HPF 0x1000 /* AIF2ADCL_HPF */
+#define WM8994_AIF2ADCL_HPF_MASK 0x1000 /* AIF2ADCL_HPF */
+#define WM8994_AIF2ADCL_HPF_SHIFT 12 /* AIF2ADCL_HPF */
+#define WM8994_AIF2ADCL_HPF_WIDTH 1 /* AIF2ADCL_HPF */
+#define WM8994_AIF2ADCR_HPF 0x0800 /* AIF2ADCR_HPF */
+#define WM8994_AIF2ADCR_HPF_MASK 0x0800 /* AIF2ADCR_HPF */
+#define WM8994_AIF2ADCR_HPF_SHIFT 11 /* AIF2ADCR_HPF */
+#define WM8994_AIF2ADCR_HPF_WIDTH 1 /* AIF2ADCR_HPF */
+
+/*
+ * R1312 (0x520) - AIF2 DAC Filters (1)
+ */
+#define WM8994_AIF2DAC_MUTE 0x0200 /* AIF2DAC_MUTE */
+#define WM8994_AIF2DAC_MUTE_MASK 0x0200 /* AIF2DAC_MUTE */
+#define WM8994_AIF2DAC_MUTE_SHIFT 9 /* AIF2DAC_MUTE */
+#define WM8994_AIF2DAC_MUTE_WIDTH 1 /* AIF2DAC_MUTE */
+#define WM8994_AIF2DAC_MONO 0x0080 /* AIF2DAC_MONO */
+#define WM8994_AIF2DAC_MONO_MASK 0x0080 /* AIF2DAC_MONO */
+#define WM8994_AIF2DAC_MONO_SHIFT 7 /* AIF2DAC_MONO */
+#define WM8994_AIF2DAC_MONO_WIDTH 1 /* AIF2DAC_MONO */
+#define WM8994_AIF2DAC_MUTERATE 0x0020 /* AIF2DAC_MUTERATE */
+#define WM8994_AIF2DAC_MUTERATE_MASK 0x0020 /* AIF2DAC_MUTERATE */
+#define WM8994_AIF2DAC_MUTERATE_SHIFT 5 /* AIF2DAC_MUTERATE */
+#define WM8994_AIF2DAC_MUTERATE_WIDTH 1 /* AIF2DAC_MUTERATE */
+#define WM8994_AIF2DAC_UNMUTE_RAMP 0x0010 /* AIF2DAC_UNMUTE_RAMP */
+#define WM8994_AIF2DAC_UNMUTE_RAMP_MASK 0x0010 /* AIF2DAC_UNMUTE_RAMP */
+#define WM8994_AIF2DAC_UNMUTE_RAMP_SHIFT 4 /* AIF2DAC_UNMUTE_RAMP */
+#define WM8994_AIF2DAC_UNMUTE_RAMP_WIDTH 1 /* AIF2DAC_UNMUTE_RAMP */
+#define WM8994_AIF2DAC_DEEMP_MASK 0x0006 /* AIF2DAC_DEEMP - [2:1] */
+#define WM8994_AIF2DAC_DEEMP_SHIFT 1 /* AIF2DAC_DEEMP - [2:1] */
+#define WM8994_AIF2DAC_DEEMP_WIDTH 2 /* AIF2DAC_DEEMP - [2:1] */
+
+/*
+ * R1313 (0x521) - AIF2 DAC Filters (2)
+ */
+#define WM8994_AIF2DAC_3D_GAIN_MASK 0x3E00 /* AIF2DAC_3D_GAIN - [13:9] */
+#define WM8994_AIF2DAC_3D_GAIN_SHIFT 9 /* AIF2DAC_3D_GAIN - [13:9] */
+#define WM8994_AIF2DAC_3D_GAIN_WIDTH 5 /* AIF2DAC_3D_GAIN - [13:9] */
+#define WM8994_AIF2DAC_3D_ENA 0x0100 /* AIF2DAC_3D_ENA */
+#define WM8994_AIF2DAC_3D_ENA_MASK 0x0100 /* AIF2DAC_3D_ENA */
+#define WM8994_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */
+#define WM8994_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */
+
+/*
+ * R1344 (0x540) - AIF2 DRC (1)
+ */
+#define WM8994_AIF2DRC_SIG_DET_RMS_MASK 0xF800 /* AIF2DRC_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF2DRC_SIG_DET_RMS_SHIFT 11 /* AIF2DRC_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF2DRC_SIG_DET_RMS_WIDTH 5 /* AIF2DRC_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF2DRC_SIG_DET_PK_MASK 0x0600 /* AIF2DRC_SIG_DET_PK - [10:9] */
+#define WM8994_AIF2DRC_SIG_DET_PK_SHIFT 9 /* AIF2DRC_SIG_DET_PK - [10:9] */
+#define WM8994_AIF2DRC_SIG_DET_PK_WIDTH 2 /* AIF2DRC_SIG_DET_PK - [10:9] */
+#define WM8994_AIF2DRC_NG_ENA 0x0100 /* AIF2DRC_NG_ENA */
+#define WM8994_AIF2DRC_NG_ENA_MASK 0x0100 /* AIF2DRC_NG_ENA */
+#define WM8994_AIF2DRC_NG_ENA_SHIFT 8 /* AIF2DRC_NG_ENA */
+#define WM8994_AIF2DRC_NG_ENA_WIDTH 1 /* AIF2DRC_NG_ENA */
+#define WM8994_AIF2DRC_SIG_DET_MODE 0x0080 /* AIF2DRC_SIG_DET_MODE */
+#define WM8994_AIF2DRC_SIG_DET_MODE_MASK 0x0080 /* AIF2DRC_SIG_DET_MODE */
+#define WM8994_AIF2DRC_SIG_DET_MODE_SHIFT 7 /* AIF2DRC_SIG_DET_MODE */
+#define WM8994_AIF2DRC_SIG_DET_MODE_WIDTH 1 /* AIF2DRC_SIG_DET_MODE */
+#define WM8994_AIF2DRC_SIG_DET 0x0040 /* AIF2DRC_SIG_DET */
+#define WM8994_AIF2DRC_SIG_DET_MASK 0x0040 /* AIF2DRC_SIG_DET */
+#define WM8994_AIF2DRC_SIG_DET_SHIFT 6 /* AIF2DRC_SIG_DET */
+#define WM8994_AIF2DRC_SIG_DET_WIDTH 1 /* AIF2DRC_SIG_DET */
+#define WM8994_AIF2DRC_KNEE2_OP_ENA 0x0020 /* AIF2DRC_KNEE2_OP_ENA */
+#define WM8994_AIF2DRC_KNEE2_OP_ENA_MASK 0x0020 /* AIF2DRC_KNEE2_OP_ENA */
+#define WM8994_AIF2DRC_KNEE2_OP_ENA_SHIFT 5 /* AIF2DRC_KNEE2_OP_ENA */
+#define WM8994_AIF2DRC_KNEE2_OP_ENA_WIDTH 1 /* AIF2DRC_KNEE2_OP_ENA */
+#define WM8994_AIF2DRC_QR 0x0010 /* AIF2DRC_QR */
+#define WM8994_AIF2DRC_QR_MASK 0x0010 /* AIF2DRC_QR */
+#define WM8994_AIF2DRC_QR_SHIFT 4 /* AIF2DRC_QR */
+#define WM8994_AIF2DRC_QR_WIDTH 1 /* AIF2DRC_QR */
+#define WM8994_AIF2DRC_ANTICLIP 0x0008 /* AIF2DRC_ANTICLIP */
+#define WM8994_AIF2DRC_ANTICLIP_MASK 0x0008 /* AIF2DRC_ANTICLIP */
+#define WM8994_AIF2DRC_ANTICLIP_SHIFT 3 /* AIF2DRC_ANTICLIP */
+#define WM8994_AIF2DRC_ANTICLIP_WIDTH 1 /* AIF2DRC_ANTICLIP */
+#define WM8994_AIF2DAC_DRC_ENA 0x0004 /* AIF2DAC_DRC_ENA */
+#define WM8994_AIF2DAC_DRC_ENA_MASK 0x0004 /* AIF2DAC_DRC_ENA */
+#define WM8994_AIF2DAC_DRC_ENA_SHIFT 2 /* AIF2DAC_DRC_ENA */
+#define WM8994_AIF2DAC_DRC_ENA_WIDTH 1 /* AIF2DAC_DRC_ENA */
+#define WM8994_AIF2ADCL_DRC_ENA 0x0002 /* AIF2ADCL_DRC_ENA */
+#define WM8994_AIF2ADCL_DRC_ENA_MASK 0x0002 /* AIF2ADCL_DRC_ENA */
+#define WM8994_AIF2ADCL_DRC_ENA_SHIFT 1 /* AIF2ADCL_DRC_ENA */
+#define WM8994_AIF2ADCL_DRC_ENA_WIDTH 1 /* AIF2ADCL_DRC_ENA */
+#define WM8994_AIF2ADCR_DRC_ENA 0x0001 /* AIF2ADCR_DRC_ENA */
+#define WM8994_AIF2ADCR_DRC_ENA_MASK 0x0001 /* AIF2ADCR_DRC_ENA */
+#define WM8994_AIF2ADCR_DRC_ENA_SHIFT 0 /* AIF2ADCR_DRC_ENA */
+#define WM8994_AIF2ADCR_DRC_ENA_WIDTH 1 /* AIF2ADCR_DRC_ENA */
+
+/*
+ * R1345 (0x541) - AIF2 DRC (2)
+ */
+#define WM8994_AIF2DRC_ATK_MASK 0x1E00 /* AIF2DRC_ATK - [12:9] */
+#define WM8994_AIF2DRC_ATK_SHIFT 9 /* AIF2DRC_ATK - [12:9] */
+#define WM8994_AIF2DRC_ATK_WIDTH 4 /* AIF2DRC_ATK - [12:9] */
+#define WM8994_AIF2DRC_DCY_MASK 0x01E0 /* AIF2DRC_DCY - [8:5] */
+#define WM8994_AIF2DRC_DCY_SHIFT 5 /* AIF2DRC_DCY - [8:5] */
+#define WM8994_AIF2DRC_DCY_WIDTH 4 /* AIF2DRC_DCY - [8:5] */
+#define WM8994_AIF2DRC_MINGAIN_MASK 0x001C /* AIF2DRC_MINGAIN - [4:2] */
+#define WM8994_AIF2DRC_MINGAIN_SHIFT 2 /* AIF2DRC_MINGAIN - [4:2] */
+#define WM8994_AIF2DRC_MINGAIN_WIDTH 3 /* AIF2DRC_MINGAIN - [4:2] */
+#define WM8994_AIF2DRC_MAXGAIN_MASK 0x0003 /* AIF2DRC_MAXGAIN - [1:0] */
+#define WM8994_AIF2DRC_MAXGAIN_SHIFT 0 /* AIF2DRC_MAXGAIN - [1:0] */
+#define WM8994_AIF2DRC_MAXGAIN_WIDTH 2 /* AIF2DRC_MAXGAIN - [1:0] */
+
+/*
+ * R1346 (0x542) - AIF2 DRC (3)
+ */
+#define WM8994_AIF2DRC_NG_MINGAIN_MASK 0xF000 /* AIF2DRC_NG_MINGAIN - [15:12] */
+#define WM8994_AIF2DRC_NG_MINGAIN_SHIFT 12 /* AIF2DRC_NG_MINGAIN - [15:12] */
+#define WM8994_AIF2DRC_NG_MINGAIN_WIDTH 4 /* AIF2DRC_NG_MINGAIN - [15:12] */
+#define WM8994_AIF2DRC_NG_EXP_MASK 0x0C00 /* AIF2DRC_NG_EXP - [11:10] */
+#define WM8994_AIF2DRC_NG_EXP_SHIFT 10 /* AIF2DRC_NG_EXP - [11:10] */
+#define WM8994_AIF2DRC_NG_EXP_WIDTH 2 /* AIF2DRC_NG_EXP - [11:10] */
+#define WM8994_AIF2DRC_QR_THR_MASK 0x0300 /* AIF2DRC_QR_THR - [9:8] */
+#define WM8994_AIF2DRC_QR_THR_SHIFT 8 /* AIF2DRC_QR_THR - [9:8] */
+#define WM8994_AIF2DRC_QR_THR_WIDTH 2 /* AIF2DRC_QR_THR - [9:8] */
+#define WM8994_AIF2DRC_QR_DCY_MASK 0x00C0 /* AIF2DRC_QR_DCY - [7:6] */
+#define WM8994_AIF2DRC_QR_DCY_SHIFT 6 /* AIF2DRC_QR_DCY - [7:6] */
+#define WM8994_AIF2DRC_QR_DCY_WIDTH 2 /* AIF2DRC_QR_DCY - [7:6] */
+#define WM8994_AIF2DRC_HI_COMP_MASK 0x0038 /* AIF2DRC_HI_COMP - [5:3] */
+#define WM8994_AIF2DRC_HI_COMP_SHIFT 3 /* AIF2DRC_HI_COMP - [5:3] */
+#define WM8994_AIF2DRC_HI_COMP_WIDTH 3 /* AIF2DRC_HI_COMP - [5:3] */
+#define WM8994_AIF2DRC_LO_COMP_MASK 0x0007 /* AIF2DRC_LO_COMP - [2:0] */
+#define WM8994_AIF2DRC_LO_COMP_SHIFT 0 /* AIF2DRC_LO_COMP - [2:0] */
+#define WM8994_AIF2DRC_LO_COMP_WIDTH 3 /* AIF2DRC_LO_COMP - [2:0] */
+
+/*
+ * R1347 (0x543) - AIF2 DRC (4)
+ */
+#define WM8994_AIF2DRC_KNEE_IP_MASK 0x07E0 /* AIF2DRC_KNEE_IP - [10:5] */
+#define WM8994_AIF2DRC_KNEE_IP_SHIFT 5 /* AIF2DRC_KNEE_IP - [10:5] */
+#define WM8994_AIF2DRC_KNEE_IP_WIDTH 6 /* AIF2DRC_KNEE_IP - [10:5] */
+#define WM8994_AIF2DRC_KNEE_OP_MASK 0x001F /* AIF2DRC_KNEE_OP - [4:0] */
+#define WM8994_AIF2DRC_KNEE_OP_SHIFT 0 /* AIF2DRC_KNEE_OP - [4:0] */
+#define WM8994_AIF2DRC_KNEE_OP_WIDTH 5 /* AIF2DRC_KNEE_OP - [4:0] */
+
+/*
+ * R1348 (0x544) - AIF2 DRC (5)
+ */
+#define WM8994_AIF2DRC_KNEE2_IP_MASK 0x03E0 /* AIF2DRC_KNEE2_IP - [9:5] */
+#define WM8994_AIF2DRC_KNEE2_IP_SHIFT 5 /* AIF2DRC_KNEE2_IP - [9:5] */
+#define WM8994_AIF2DRC_KNEE2_IP_WIDTH 5 /* AIF2DRC_KNEE2_IP - [9:5] */
+#define WM8994_AIF2DRC_KNEE2_OP_MASK 0x001F /* AIF2DRC_KNEE2_OP - [4:0] */
+#define WM8994_AIF2DRC_KNEE2_OP_SHIFT 0 /* AIF2DRC_KNEE2_OP - [4:0] */
+#define WM8994_AIF2DRC_KNEE2_OP_WIDTH 5 /* AIF2DRC_KNEE2_OP - [4:0] */
+
+/*
+ * R1408 (0x580) - AIF2 EQ Gains (1)
+ */
+#define WM8994_AIF2DAC_EQ_B1_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF2DAC_EQ_B1_GAIN_SHIFT 11 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF2DAC_EQ_B1_GAIN_WIDTH 5 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF2DAC_EQ_B2_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF2DAC_EQ_B2_GAIN_SHIFT 6 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF2DAC_EQ_B2_GAIN_WIDTH 5 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF2DAC_EQ_B3_GAIN_MASK 0x003E /* AIF2DAC_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF2DAC_EQ_B3_GAIN_SHIFT 1 /* AIF2DAC_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF2DAC_EQ_B3_GAIN_WIDTH 5 /* AIF2DAC_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF2DAC_EQ_ENA 0x0001 /* AIF2DAC_EQ_ENA */
+#define WM8994_AIF2DAC_EQ_ENA_MASK 0x0001 /* AIF2DAC_EQ_ENA */
+#define WM8994_AIF2DAC_EQ_ENA_SHIFT 0 /* AIF2DAC_EQ_ENA */
+#define WM8994_AIF2DAC_EQ_ENA_WIDTH 1 /* AIF2DAC_EQ_ENA */
+
+/*
+ * R1409 (0x581) - AIF2 EQ Gains (2)
+ */
+#define WM8994_AIF2DAC_EQ_B4_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF2DAC_EQ_B4_GAIN_SHIFT 11 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF2DAC_EQ_B4_GAIN_WIDTH 5 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF2DAC_EQ_B5_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
+#define WM8994_AIF2DAC_EQ_B5_GAIN_SHIFT 6 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
+#define WM8994_AIF2DAC_EQ_B5_GAIN_WIDTH 5 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
+
+/*
+ * R1410 (0x582) - AIF2 EQ Band 1 A
+ */
+#define WM8994_AIF2DAC_EQ_B1_A_MASK 0xFFFF /* AIF2DAC_EQ_B1_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B1_A_SHIFT 0 /* AIF2DAC_EQ_B1_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B1_A_WIDTH 16 /* AIF2DAC_EQ_B1_A - [15:0] */
+
+/*
+ * R1411 (0x583) - AIF2 EQ Band 1 B
+ */
+#define WM8994_AIF2DAC_EQ_B1_B_MASK 0xFFFF /* AIF2DAC_EQ_B1_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B1_B_SHIFT 0 /* AIF2DAC_EQ_B1_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B1_B_WIDTH 16 /* AIF2DAC_EQ_B1_B - [15:0] */
+
+/*
+ * R1412 (0x584) - AIF2 EQ Band 1 PG
+ */
+#define WM8994_AIF2DAC_EQ_B1_PG_MASK 0xFFFF /* AIF2DAC_EQ_B1_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B1_PG_SHIFT 0 /* AIF2DAC_EQ_B1_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B1_PG_WIDTH 16 /* AIF2DAC_EQ_B1_PG - [15:0] */
+
+/*
+ * R1413 (0x585) - AIF2 EQ Band 2 A
+ */
+#define WM8994_AIF2DAC_EQ_B2_A_MASK 0xFFFF /* AIF2DAC_EQ_B2_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B2_A_SHIFT 0 /* AIF2DAC_EQ_B2_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B2_A_WIDTH 16 /* AIF2DAC_EQ_B2_A - [15:0] */
+
+/*
+ * R1414 (0x586) - AIF2 EQ Band 2 B
+ */
+#define WM8994_AIF2DAC_EQ_B2_B_MASK 0xFFFF /* AIF2DAC_EQ_B2_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B2_B_SHIFT 0 /* AIF2DAC_EQ_B2_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B2_B_WIDTH 16 /* AIF2DAC_EQ_B2_B - [15:0] */
+
+/*
+ * R1415 (0x587) - AIF2 EQ Band 2 C
+ */
+#define WM8994_AIF2DAC_EQ_B2_C_MASK 0xFFFF /* AIF2DAC_EQ_B2_C - [15:0] */
+#define WM8994_AIF2DAC_EQ_B2_C_SHIFT 0 /* AIF2DAC_EQ_B2_C - [15:0] */
+#define WM8994_AIF2DAC_EQ_B2_C_WIDTH 16 /* AIF2DAC_EQ_B2_C - [15:0] */
+
+/*
+ * R1416 (0x588) - AIF2 EQ Band 2 PG
+ */
+#define WM8994_AIF2DAC_EQ_B2_PG_MASK 0xFFFF /* AIF2DAC_EQ_B2_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B2_PG_SHIFT 0 /* AIF2DAC_EQ_B2_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B2_PG_WIDTH 16 /* AIF2DAC_EQ_B2_PG - [15:0] */
+
+/*
+ * R1417 (0x589) - AIF2 EQ Band 3 A
+ */
+#define WM8994_AIF2DAC_EQ_B3_A_MASK 0xFFFF /* AIF2DAC_EQ_B3_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B3_A_SHIFT 0 /* AIF2DAC_EQ_B3_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B3_A_WIDTH 16 /* AIF2DAC_EQ_B3_A - [15:0] */
+
+/*
+ * R1418 (0x58A) - AIF2 EQ Band 3 B
+ */
+#define WM8994_AIF2DAC_EQ_B3_B_MASK 0xFFFF /* AIF2DAC_EQ_B3_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B3_B_SHIFT 0 /* AIF2DAC_EQ_B3_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B3_B_WIDTH 16 /* AIF2DAC_EQ_B3_B - [15:0] */
+
+/*
+ * R1419 (0x58B) - AIF2 EQ Band 3 C
+ */
+#define WM8994_AIF2DAC_EQ_B3_C_MASK 0xFFFF /* AIF2DAC_EQ_B3_C - [15:0] */
+#define WM8994_AIF2DAC_EQ_B3_C_SHIFT 0 /* AIF2DAC_EQ_B3_C - [15:0] */
+#define WM8994_AIF2DAC_EQ_B3_C_WIDTH 16 /* AIF2DAC_EQ_B3_C - [15:0] */
+
+/*
+ * R1420 (0x58C) - AIF2 EQ Band 3 PG
+ */
+#define WM8994_AIF2DAC_EQ_B3_PG_MASK 0xFFFF /* AIF2DAC_EQ_B3_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B3_PG_SHIFT 0 /* AIF2DAC_EQ_B3_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B3_PG_WIDTH 16 /* AIF2DAC_EQ_B3_PG - [15:0] */
+
+/*
+ * R1421 (0x58D) - AIF2 EQ Band 4 A
+ */
+#define WM8994_AIF2DAC_EQ_B4_A_MASK 0xFFFF /* AIF2DAC_EQ_B4_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B4_A_SHIFT 0 /* AIF2DAC_EQ_B4_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B4_A_WIDTH 16 /* AIF2DAC_EQ_B4_A - [15:0] */
+
+/*
+ * R1422 (0x58E) - AIF2 EQ Band 4 B
+ */
+#define WM8994_AIF2DAC_EQ_B4_B_MASK 0xFFFF /* AIF2DAC_EQ_B4_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B4_B_SHIFT 0 /* AIF2DAC_EQ_B4_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B4_B_WIDTH 16 /* AIF2DAC_EQ_B4_B - [15:0] */
+
+/*
+ * R1423 (0x58F) - AIF2 EQ Band 4 C
+ */
+#define WM8994_AIF2DAC_EQ_B4_C_MASK 0xFFFF /* AIF2DAC_EQ_B4_C - [15:0] */
+#define WM8994_AIF2DAC_EQ_B4_C_SHIFT 0 /* AIF2DAC_EQ_B4_C - [15:0] */
+#define WM8994_AIF2DAC_EQ_B4_C_WIDTH 16 /* AIF2DAC_EQ_B4_C - [15:0] */
+
+/*
+ * R1424 (0x590) - AIF2 EQ Band 4 PG
+ */
+#define WM8994_AIF2DAC_EQ_B4_PG_MASK 0xFFFF /* AIF2DAC_EQ_B4_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B4_PG_SHIFT 0 /* AIF2DAC_EQ_B4_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B4_PG_WIDTH 16 /* AIF2DAC_EQ_B4_PG - [15:0] */
+
+/*
+ * R1425 (0x591) - AIF2 EQ Band 5 A
+ */
+#define WM8994_AIF2DAC_EQ_B5_A_MASK 0xFFFF /* AIF2DAC_EQ_B5_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B5_A_SHIFT 0 /* AIF2DAC_EQ_B5_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B5_A_WIDTH 16 /* AIF2DAC_EQ_B5_A - [15:0] */
+
+/*
+ * R1426 (0x592) - AIF2 EQ Band 5 B
+ */
+#define WM8994_AIF2DAC_EQ_B5_B_MASK 0xFFFF /* AIF2DAC_EQ_B5_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B5_B_SHIFT 0 /* AIF2DAC_EQ_B5_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B5_B_WIDTH 16 /* AIF2DAC_EQ_B5_B - [15:0] */
+
+/*
+ * R1427 (0x593) - AIF2 EQ Band 5 PG
+ */
+#define WM8994_AIF2DAC_EQ_B5_PG_MASK 0xFFFF /* AIF2DAC_EQ_B5_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B5_PG_SHIFT 0 /* AIF2DAC_EQ_B5_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B5_PG_WIDTH 16 /* AIF2DAC_EQ_B5_PG - [15:0] */
+
+/*
+ * R1536 (0x600) - DAC1 Mixer Volumes
+ */
+#define WM8994_ADCR_DAC1_VOL_MASK 0x01E0 /* ADCR_DAC1_VOL - [8:5] */
+#define WM8994_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [8:5] */
+#define WM8994_ADCR_DAC1_VOL_WIDTH 4 /* ADCR_DAC1_VOL - [8:5] */
+#define WM8994_ADCL_DAC1_VOL_MASK 0x000F /* ADCL_DAC1_VOL - [3:0] */
+#define WM8994_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [3:0] */
+#define WM8994_ADCL_DAC1_VOL_WIDTH 4 /* ADCL_DAC1_VOL - [3:0] */
+
+/*
+ * R1537 (0x601) - DAC1 Left Mixer Routing
+ */
+#define WM8994_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */
+#define WM8994_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */
+#define WM8994_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */
+#define WM8994_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */
+#define WM8994_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */
+#define WM8994_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */
+#define WM8994_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */
+#define WM8994_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */
+#define WM8994_AIF2DACL_TO_DAC1L 0x0004 /* AIF2DACL_TO_DAC1L */
+#define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004 /* AIF2DACL_TO_DAC1L */
+#define WM8994_AIF2DACL_TO_DAC1L_SHIFT 2 /* AIF2DACL_TO_DAC1L */
+#define WM8994_AIF2DACL_TO_DAC1L_WIDTH 1 /* AIF2DACL_TO_DAC1L */
+#define WM8994_AIF1DAC2L_TO_DAC1L 0x0002 /* AIF1DAC2L_TO_DAC1L */
+#define WM8994_AIF1DAC2L_TO_DAC1L_MASK 0x0002 /* AIF1DAC2L_TO_DAC1L */
+#define WM8994_AIF1DAC2L_TO_DAC1L_SHIFT 1 /* AIF1DAC2L_TO_DAC1L */
+#define WM8994_AIF1DAC2L_TO_DAC1L_WIDTH 1 /* AIF1DAC2L_TO_DAC1L */
+#define WM8994_AIF1DAC1L_TO_DAC1L 0x0001 /* AIF1DAC1L_TO_DAC1L */
+#define WM8994_AIF1DAC1L_TO_DAC1L_MASK 0x0001 /* AIF1DAC1L_TO_DAC1L */
+#define WM8994_AIF1DAC1L_TO_DAC1L_SHIFT 0 /* AIF1DAC1L_TO_DAC1L */
+#define WM8994_AIF1DAC1L_TO_DAC1L_WIDTH 1 /* AIF1DAC1L_TO_DAC1L */
+
+/*
+ * R1538 (0x602) - DAC1 Right Mixer Routing
+ */
+#define WM8994_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */
+#define WM8994_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */
+#define WM8994_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */
+#define WM8994_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */
+#define WM8994_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */
+#define WM8994_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */
+#define WM8994_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */
+#define WM8994_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */
+#define WM8994_AIF2DACR_TO_DAC1R 0x0004 /* AIF2DACR_TO_DAC1R */
+#define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004 /* AIF2DACR_TO_DAC1R */
+#define WM8994_AIF2DACR_TO_DAC1R_SHIFT 2 /* AIF2DACR_TO_DAC1R */
+#define WM8994_AIF2DACR_TO_DAC1R_WIDTH 1 /* AIF2DACR_TO_DAC1R */
+#define WM8994_AIF1DAC2R_TO_DAC1R 0x0002 /* AIF1DAC2R_TO_DAC1R */
+#define WM8994_AIF1DAC2R_TO_DAC1R_MASK 0x0002 /* AIF1DAC2R_TO_DAC1R */
+#define WM8994_AIF1DAC2R_TO_DAC1R_SHIFT 1 /* AIF1DAC2R_TO_DAC1R */
+#define WM8994_AIF1DAC2R_TO_DAC1R_WIDTH 1 /* AIF1DAC2R_TO_DAC1R */
+#define WM8994_AIF1DAC1R_TO_DAC1R 0x0001 /* AIF1DAC1R_TO_DAC1R */
+#define WM8994_AIF1DAC1R_TO_DAC1R_MASK 0x0001 /* AIF1DAC1R_TO_DAC1R */
+#define WM8994_AIF1DAC1R_TO_DAC1R_SHIFT 0 /* AIF1DAC1R_TO_DAC1R */
+#define WM8994_AIF1DAC1R_TO_DAC1R_WIDTH 1 /* AIF1DAC1R_TO_DAC1R */
+
+/*
+ * R1539 (0x603) - DAC2 Mixer Volumes
+ */
+#define WM8994_ADCR_DAC2_VOL_MASK 0x01E0 /* ADCR_DAC2_VOL - [8:5] */
+#define WM8994_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [8:5] */
+#define WM8994_ADCR_DAC2_VOL_WIDTH 4 /* ADCR_DAC2_VOL - [8:5] */
+#define WM8994_ADCL_DAC2_VOL_MASK 0x000F /* ADCL_DAC2_VOL - [3:0] */
+#define WM8994_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [3:0] */
+#define WM8994_ADCL_DAC2_VOL_WIDTH 4 /* ADCL_DAC2_VOL - [3:0] */
+
+/*
+ * R1540 (0x604) - DAC2 Left Mixer Routing
+ */
+#define WM8994_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */
+#define WM8994_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */
+#define WM8994_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */
+#define WM8994_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */
+#define WM8994_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */
+#define WM8994_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */
+#define WM8994_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */
+#define WM8994_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */
+#define WM8994_AIF2DACL_TO_DAC2L 0x0004 /* AIF2DACL_TO_DAC2L */
+#define WM8994_AIF2DACL_TO_DAC2L_MASK 0x0004 /* AIF2DACL_TO_DAC2L */
+#define WM8994_AIF2DACL_TO_DAC2L_SHIFT 2 /* AIF2DACL_TO_DAC2L */
+#define WM8994_AIF2DACL_TO_DAC2L_WIDTH 1 /* AIF2DACL_TO_DAC2L */
+#define WM8994_AIF1DAC2L_TO_DAC2L 0x0002 /* AIF1DAC2L_TO_DAC2L */
+#define WM8994_AIF1DAC2L_TO_DAC2L_MASK 0x0002 /* AIF1DAC2L_TO_DAC2L */
+#define WM8994_AIF1DAC2L_TO_DAC2L_SHIFT 1 /* AIF1DAC2L_TO_DAC2L */
+#define WM8994_AIF1DAC2L_TO_DAC2L_WIDTH 1 /* AIF1DAC2L_TO_DAC2L */
+#define WM8994_AIF1DAC1L_TO_DAC2L 0x0001 /* AIF1DAC1L_TO_DAC2L */
+#define WM8994_AIF1DAC1L_TO_DAC2L_MASK 0x0001 /* AIF1DAC1L_TO_DAC2L */
+#define WM8994_AIF1DAC1L_TO_DAC2L_SHIFT 0 /* AIF1DAC1L_TO_DAC2L */
+#define WM8994_AIF1DAC1L_TO_DAC2L_WIDTH 1 /* AIF1DAC1L_TO_DAC2L */
+
+/*
+ * R1541 (0x605) - DAC2 Right Mixer Routing
+ */
+#define WM8994_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */
+#define WM8994_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */
+#define WM8994_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */
+#define WM8994_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */
+#define WM8994_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */
+#define WM8994_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */
+#define WM8994_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */
+#define WM8994_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */
+#define WM8994_AIF2DACR_TO_DAC2R 0x0004 /* AIF2DACR_TO_DAC2R */
+#define WM8994_AIF2DACR_TO_DAC2R_MASK 0x0004 /* AIF2DACR_TO_DAC2R */
+#define WM8994_AIF2DACR_TO_DAC2R_SHIFT 2 /* AIF2DACR_TO_DAC2R */
+#define WM8994_AIF2DACR_TO_DAC2R_WIDTH 1 /* AIF2DACR_TO_DAC2R */
+#define WM8994_AIF1DAC2R_TO_DAC2R 0x0002 /* AIF1DAC2R_TO_DAC2R */
+#define WM8994_AIF1DAC2R_TO_DAC2R_MASK 0x0002 /* AIF1DAC2R_TO_DAC2R */
+#define WM8994_AIF1DAC2R_TO_DAC2R_SHIFT 1 /* AIF1DAC2R_TO_DAC2R */
+#define WM8994_AIF1DAC2R_TO_DAC2R_WIDTH 1 /* AIF1DAC2R_TO_DAC2R */
+#define WM8994_AIF1DAC1R_TO_DAC2R 0x0001 /* AIF1DAC1R_TO_DAC2R */
+#define WM8994_AIF1DAC1R_TO_DAC2R_MASK 0x0001 /* AIF1DAC1R_TO_DAC2R */
+#define WM8994_AIF1DAC1R_TO_DAC2R_SHIFT 0 /* AIF1DAC1R_TO_DAC2R */
+#define WM8994_AIF1DAC1R_TO_DAC2R_WIDTH 1 /* AIF1DAC1R_TO_DAC2R */
+
+/*
+ * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing
+ */
+#define WM8994_ADC1L_TO_AIF1ADC1L 0x0002 /* ADC1L_TO_AIF1ADC1L */
+#define WM8994_ADC1L_TO_AIF1ADC1L_MASK 0x0002 /* ADC1L_TO_AIF1ADC1L */
+#define WM8994_ADC1L_TO_AIF1ADC1L_SHIFT 1 /* ADC1L_TO_AIF1ADC1L */
+#define WM8994_ADC1L_TO_AIF1ADC1L_WIDTH 1 /* ADC1L_TO_AIF1ADC1L */
+#define WM8994_AIF2DACL_TO_AIF1ADC1L 0x0001 /* AIF2DACL_TO_AIF1ADC1L */
+#define WM8994_AIF2DACL_TO_AIF1ADC1L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC1L */
+#define WM8994_AIF2DACL_TO_AIF1ADC1L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC1L */
+#define WM8994_AIF2DACL_TO_AIF1ADC1L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC1L */
+
+/*
+ * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing
+ */
+#define WM8994_ADC1R_TO_AIF1ADC1R 0x0002 /* ADC1R_TO_AIF1ADC1R */
+#define WM8994_ADC1R_TO_AIF1ADC1R_MASK 0x0002 /* ADC1R_TO_AIF1ADC1R */
+#define WM8994_ADC1R_TO_AIF1ADC1R_SHIFT 1 /* ADC1R_TO_AIF1ADC1R */
+#define WM8994_ADC1R_TO_AIF1ADC1R_WIDTH 1 /* ADC1R_TO_AIF1ADC1R */
+#define WM8994_AIF2DACR_TO_AIF1ADC1R 0x0001 /* AIF2DACR_TO_AIF1ADC1R */
+#define WM8994_AIF2DACR_TO_AIF1ADC1R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC1R */
+#define WM8994_AIF2DACR_TO_AIF1ADC1R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC1R */
+#define WM8994_AIF2DACR_TO_AIF1ADC1R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC1R */
+
+/*
+ * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing
+ */
+#define WM8994_ADC2L_TO_AIF1ADC2L 0x0002 /* ADC2L_TO_AIF1ADC2L */
+#define WM8994_ADC2L_TO_AIF1ADC2L_MASK 0x0002 /* ADC2L_TO_AIF1ADC2L */
+#define WM8994_ADC2L_TO_AIF1ADC2L_SHIFT 1 /* ADC2L_TO_AIF1ADC2L */
+#define WM8994_ADC2L_TO_AIF1ADC2L_WIDTH 1 /* ADC2L_TO_AIF1ADC2L */
+#define WM8994_AIF2DACL_TO_AIF1ADC2L 0x0001 /* AIF2DACL_TO_AIF1ADC2L */
+#define WM8994_AIF2DACL_TO_AIF1ADC2L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC2L */
+#define WM8994_AIF2DACL_TO_AIF1ADC2L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC2L */
+#define WM8994_AIF2DACL_TO_AIF1ADC2L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC2L */
+
+/*
+ * R1545 (0x609) - AIF1 ADC2 Right mixer Routing
+ */
+#define WM8994_ADC2R_TO_AIF1ADC2R 0x0002 /* ADC2R_TO_AIF1ADC2R */
+#define WM8994_ADC2R_TO_AIF1ADC2R_MASK 0x0002 /* ADC2R_TO_AIF1ADC2R */
+#define WM8994_ADC2R_TO_AIF1ADC2R_SHIFT 1 /* ADC2R_TO_AIF1ADC2R */
+#define WM8994_ADC2R_TO_AIF1ADC2R_WIDTH 1 /* ADC2R_TO_AIF1ADC2R */
+#define WM8994_AIF2DACR_TO_AIF1ADC2R 0x0001 /* AIF2DACR_TO_AIF1ADC2R */
+#define WM8994_AIF2DACR_TO_AIF1ADC2R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC2R */
+#define WM8994_AIF2DACR_TO_AIF1ADC2R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC2R */
+#define WM8994_AIF2DACR_TO_AIF1ADC2R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC2R */
+
+/*
+ * R1552 (0x610) - DAC1 Left Volume
+ */
+#define WM8994_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */
+#define WM8994_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */
+#define WM8994_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */
+#define WM8994_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */
+#define WM8994_DAC1_VU 0x0100 /* DAC1_VU */
+#define WM8994_DAC1_VU_MASK 0x0100 /* DAC1_VU */
+#define WM8994_DAC1_VU_SHIFT 8 /* DAC1_VU */
+#define WM8994_DAC1_VU_WIDTH 1 /* DAC1_VU */
+#define WM8994_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */
+#define WM8994_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */
+#define WM8994_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */
+
+/*
+ * R1553 (0x611) - DAC1 Right Volume
+ */
+#define WM8994_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */
+#define WM8994_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */
+#define WM8994_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */
+#define WM8994_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */
+#define WM8994_DAC1_VU 0x0100 /* DAC1_VU */
+#define WM8994_DAC1_VU_MASK 0x0100 /* DAC1_VU */
+#define WM8994_DAC1_VU_SHIFT 8 /* DAC1_VU */
+#define WM8994_DAC1_VU_WIDTH 1 /* DAC1_VU */
+#define WM8994_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */
+#define WM8994_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */
+#define WM8994_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */
+
+/*
+ * R1554 (0x612) - DAC2 Left Volume
+ */
+#define WM8994_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */
+#define WM8994_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */
+#define WM8994_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */
+#define WM8994_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */
+#define WM8994_DAC2_VU 0x0100 /* DAC2_VU */
+#define WM8994_DAC2_VU_MASK 0x0100 /* DAC2_VU */
+#define WM8994_DAC2_VU_SHIFT 8 /* DAC2_VU */
+#define WM8994_DAC2_VU_WIDTH 1 /* DAC2_VU */
+#define WM8994_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */
+#define WM8994_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */
+#define WM8994_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */
+
+/*
+ * R1555 (0x613) - DAC2 Right Volume
+ */
+#define WM8994_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */
+#define WM8994_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */
+#define WM8994_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */
+#define WM8994_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */
+#define WM8994_DAC2_VU 0x0100 /* DAC2_VU */
+#define WM8994_DAC2_VU_MASK 0x0100 /* DAC2_VU */
+#define WM8994_DAC2_VU_SHIFT 8 /* DAC2_VU */
+#define WM8994_DAC2_VU_WIDTH 1 /* DAC2_VU */
+#define WM8994_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */
+#define WM8994_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */
+#define WM8994_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */
+
+/*
+ * R1556 (0x614) - DAC Softmute
+ */
+#define WM8994_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */
+#define WM8994_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */
+#define WM8994_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */
+#define WM8994_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */
+#define WM8994_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */
+#define WM8994_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */
+#define WM8994_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */
+#define WM8994_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
+
+/*
+ * R1568 (0x620) - Oversampling
+ */
+#define WM8994_ADC_OSR128 0x0002 /* ADC_OSR128 */
+#define WM8994_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */
+#define WM8994_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */
+#define WM8994_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */
+#define WM8994_DAC_OSR128 0x0001 /* DAC_OSR128 */
+#define WM8994_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */
+#define WM8994_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */
+#define WM8994_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */
+
+/*
+ * R1569 (0x621) - Sidetone
+ */
+#define WM8994_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */
+#define WM8994_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */
+#define WM8994_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */
+#define WM8994_ST_HPF 0x0040 /* ST_HPF */
+#define WM8994_ST_HPF_MASK 0x0040 /* ST_HPF */
+#define WM8994_ST_HPF_SHIFT 6 /* ST_HPF */
+#define WM8994_ST_HPF_WIDTH 1 /* ST_HPF */
+#define WM8994_STR_SEL 0x0002 /* STR_SEL */
+#define WM8994_STR_SEL_MASK 0x0002 /* STR_SEL */
+#define WM8994_STR_SEL_SHIFT 1 /* STR_SEL */
+#define WM8994_STR_SEL_WIDTH 1 /* STR_SEL */
+#define WM8994_STL_SEL 0x0001 /* STL_SEL */
+#define WM8994_STL_SEL_MASK 0x0001 /* STL_SEL */
+#define WM8994_STL_SEL_SHIFT 0 /* STL_SEL */
+#define WM8994_STL_SEL_WIDTH 1 /* STL_SEL */
+
+/*
+ * R1824 (0x720) - Pull Control (1)
+ */
+#define WM8994_DMICDAT2_PU 0x0800 /* DMICDAT2_PU */
+#define WM8994_DMICDAT2_PU_MASK 0x0800 /* DMICDAT2_PU */
+#define WM8994_DMICDAT2_PU_SHIFT 11 /* DMICDAT2_PU */
+#define WM8994_DMICDAT2_PU_WIDTH 1 /* DMICDAT2_PU */
+#define WM8994_DMICDAT2_PD 0x0400 /* DMICDAT2_PD */
+#define WM8994_DMICDAT2_PD_MASK 0x0400 /* DMICDAT2_PD */
+#define WM8994_DMICDAT2_PD_SHIFT 10 /* DMICDAT2_PD */
+#define WM8994_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
+#define WM8994_DMICDAT1_PU 0x0200 /* DMICDAT1_PU */
+#define WM8994_DMICDAT1_PU_MASK 0x0200 /* DMICDAT1_PU */
+#define WM8994_DMICDAT1_PU_SHIFT 9 /* DMICDAT1_PU */
+#define WM8994_DMICDAT1_PU_WIDTH 1 /* DMICDAT1_PU */
+#define WM8994_DMICDAT1_PD 0x0100 /* DMICDAT1_PD */
+#define WM8994_DMICDAT1_PD_MASK 0x0100 /* DMICDAT1_PD */
+#define WM8994_DMICDAT1_PD_SHIFT 8 /* DMICDAT1_PD */
+#define WM8994_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
+#define WM8994_MCLK1_PU 0x0080 /* MCLK1_PU */
+#define WM8994_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */
+#define WM8994_MCLK1_PU_SHIFT 7 /* MCLK1_PU */
+#define WM8994_MCLK1_PU_WIDTH 1 /* MCLK1_PU */
+#define WM8994_MCLK1_PD 0x0040 /* MCLK1_PD */
+#define WM8994_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */
+#define WM8994_MCLK1_PD_SHIFT 6 /* MCLK1_PD */
+#define WM8994_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
+#define WM8994_DACDAT1_PU 0x0020 /* DACDAT1_PU */
+#define WM8994_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */
+#define WM8994_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */
+#define WM8994_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */
+#define WM8994_DACDAT1_PD 0x0010 /* DACDAT1_PD */
+#define WM8994_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */
+#define WM8994_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */
+#define WM8994_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */
+#define WM8994_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */
+#define WM8994_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */
+#define WM8994_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */
+#define WM8994_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */
+#define WM8994_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */
+#define WM8994_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */
+#define WM8994_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */
+#define WM8994_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */
+#define WM8994_BCLK1_PU 0x0002 /* BCLK1_PU */
+#define WM8994_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */
+#define WM8994_BCLK1_PU_SHIFT 1 /* BCLK1_PU */
+#define WM8994_BCLK1_PU_WIDTH 1 /* BCLK1_PU */
+#define WM8994_BCLK1_PD 0x0001 /* BCLK1_PD */
+#define WM8994_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */
+#define WM8994_BCLK1_PD_SHIFT 0 /* BCLK1_PD */
+#define WM8994_BCLK1_PD_WIDTH 1 /* BCLK1_PD */
+
+/*
+ * R1825 (0x721) - Pull Control (2)
+ */
+#define WM8994_CSNADDR_PD 0x0100 /* CSNADDR_PD */
+#define WM8994_CSNADDR_PD_MASK 0x0100 /* CSNADDR_PD */
+#define WM8994_CSNADDR_PD_SHIFT 8 /* CSNADDR_PD */
+#define WM8994_CSNADDR_PD_WIDTH 1 /* CSNADDR_PD */
+#define WM8994_LDO2ENA_PD 0x0040 /* LDO2ENA_PD */
+#define WM8994_LDO2ENA_PD_MASK 0x0040 /* LDO2ENA_PD */
+#define WM8994_LDO2ENA_PD_SHIFT 6 /* LDO2ENA_PD */
+#define WM8994_LDO2ENA_PD_WIDTH 1 /* LDO2ENA_PD */
+#define WM8994_LDO1ENA_PD 0x0010 /* LDO1ENA_PD */
+#define WM8994_LDO1ENA_PD_MASK 0x0010 /* LDO1ENA_PD */
+#define WM8994_LDO1ENA_PD_SHIFT 4 /* LDO1ENA_PD */
+#define WM8994_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */
+#define WM8994_CIFMODE_PD 0x0004 /* CIFMODE_PD */
+#define WM8994_CIFMODE_PD_MASK 0x0004 /* CIFMODE_PD */
+#define WM8994_CIFMODE_PD_SHIFT 2 /* CIFMODE_PD */
+#define WM8994_CIFMODE_PD_WIDTH 1 /* CIFMODE_PD */
+#define WM8994_SPKMODE_PU 0x0002 /* SPKMODE_PU */
+#define WM8994_SPKMODE_PU_MASK 0x0002 /* SPKMODE_PU */
+#define WM8994_SPKMODE_PU_SHIFT 1 /* SPKMODE_PU */
+#define WM8994_SPKMODE_PU_WIDTH 1 /* SPKMODE_PU */
+
+/*
+ * R1840 (0x730) - Interrupt Status 1
+ */
+#define WM8994_GP11_EINT 0x0400 /* GP11_EINT */
+#define WM8994_GP11_EINT_MASK 0x0400 /* GP11_EINT */
+#define WM8994_GP11_EINT_SHIFT 10 /* GP11_EINT */
+#define WM8994_GP11_EINT_WIDTH 1 /* GP11_EINT */
+#define WM8994_GP10_EINT 0x0200 /* GP10_EINT */
+#define WM8994_GP10_EINT_MASK 0x0200 /* GP10_EINT */
+#define WM8994_GP10_EINT_SHIFT 9 /* GP10_EINT */
+#define WM8994_GP10_EINT_WIDTH 1 /* GP10_EINT */
+#define WM8994_GP9_EINT 0x0100 /* GP9_EINT */
+#define WM8994_GP9_EINT_MASK 0x0100 /* GP9_EINT */
+#define WM8994_GP9_EINT_SHIFT 8 /* GP9_EINT */
+#define WM8994_GP9_EINT_WIDTH 1 /* GP9_EINT */
+#define WM8994_GP8_EINT 0x0080 /* GP8_EINT */
+#define WM8994_GP8_EINT_MASK 0x0080 /* GP8_EINT */
+#define WM8994_GP8_EINT_SHIFT 7 /* GP8_EINT */
+#define WM8994_GP8_EINT_WIDTH 1 /* GP8_EINT */
+#define WM8994_GP7_EINT 0x0040 /* GP7_EINT */
+#define WM8994_GP7_EINT_MASK 0x0040 /* GP7_EINT */
+#define WM8994_GP7_EINT_SHIFT 6 /* GP7_EINT */
+#define WM8994_GP7_EINT_WIDTH 1 /* GP7_EINT */
+#define WM8994_GP6_EINT 0x0020 /* GP6_EINT */
+#define WM8994_GP6_EINT_MASK 0x0020 /* GP6_EINT */
+#define WM8994_GP6_EINT_SHIFT 5 /* GP6_EINT */
+#define WM8994_GP6_EINT_WIDTH 1 /* GP6_EINT */
+#define WM8994_GP5_EINT 0x0010 /* GP5_EINT */
+#define WM8994_GP5_EINT_MASK 0x0010 /* GP5_EINT */
+#define WM8994_GP5_EINT_SHIFT 4 /* GP5_EINT */
+#define WM8994_GP5_EINT_WIDTH 1 /* GP5_EINT */
+#define WM8994_GP4_EINT 0x0008 /* GP4_EINT */
+#define WM8994_GP4_EINT_MASK 0x0008 /* GP4_EINT */
+#define WM8994_GP4_EINT_SHIFT 3 /* GP4_EINT */
+#define WM8994_GP4_EINT_WIDTH 1 /* GP4_EINT */
+#define WM8994_GP3_EINT 0x0004 /* GP3_EINT */
+#define WM8994_GP3_EINT_MASK 0x0004 /* GP3_EINT */
+#define WM8994_GP3_EINT_SHIFT 2 /* GP3_EINT */
+#define WM8994_GP3_EINT_WIDTH 1 /* GP3_EINT */
+#define WM8994_GP2_EINT 0x0002 /* GP2_EINT */
+#define WM8994_GP2_EINT_MASK 0x0002 /* GP2_EINT */
+#define WM8994_GP2_EINT_SHIFT 1 /* GP2_EINT */
+#define WM8994_GP2_EINT_WIDTH 1 /* GP2_EINT */
+#define WM8994_GP1_EINT 0x0001 /* GP1_EINT */
+#define WM8994_GP1_EINT_MASK 0x0001 /* GP1_EINT */
+#define WM8994_GP1_EINT_SHIFT 0 /* GP1_EINT */
+#define WM8994_GP1_EINT_WIDTH 1 /* GP1_EINT */
+
+/*
+ * R1841 (0x731) - Interrupt Status 2
+ */
+#define WM8994_TEMP_WARN_EINT 0x8000 /* TEMP_WARN_EINT */
+#define WM8994_TEMP_WARN_EINT_MASK 0x8000 /* TEMP_WARN_EINT */
+#define WM8994_TEMP_WARN_EINT_SHIFT 15 /* TEMP_WARN_EINT */
+#define WM8994_TEMP_WARN_EINT_WIDTH 1 /* TEMP_WARN_EINT */
+#define WM8994_DCS_DONE_EINT 0x4000 /* DCS_DONE_EINT */
+#define WM8994_DCS_DONE_EINT_MASK 0x4000 /* DCS_DONE_EINT */
+#define WM8994_DCS_DONE_EINT_SHIFT 14 /* DCS_DONE_EINT */
+#define WM8994_DCS_DONE_EINT_WIDTH 1 /* DCS_DONE_EINT */
+#define WM8994_WSEQ_DONE_EINT 0x2000 /* WSEQ_DONE_EINT */
+#define WM8994_WSEQ_DONE_EINT_MASK 0x2000 /* WSEQ_DONE_EINT */
+#define WM8994_WSEQ_DONE_EINT_SHIFT 13 /* WSEQ_DONE_EINT */
+#define WM8994_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */
+#define WM8994_FIFOS_ERR_EINT 0x1000 /* FIFOS_ERR_EINT */
+#define WM8994_FIFOS_ERR_EINT_MASK 0x1000 /* FIFOS_ERR_EINT */
+#define WM8994_FIFOS_ERR_EINT_SHIFT 12 /* FIFOS_ERR_EINT */
+#define WM8994_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */
+#define WM8994_AIF2DRC_SIG_DET_EINT 0x0800 /* AIF2DRC_SIG_DET_EINT */
+#define WM8994_AIF2DRC_SIG_DET_EINT_MASK 0x0800 /* AIF2DRC_SIG_DET_EINT */
+#define WM8994_AIF2DRC_SIG_DET_EINT_SHIFT 11 /* AIF2DRC_SIG_DET_EINT */
+#define WM8994_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* AIF2DRC_SIG_DET_EINT */
+#define WM8994_AIF1DRC2_SIG_DET_EINT 0x0400 /* AIF1DRC2_SIG_DET_EINT */
+#define WM8994_AIF1DRC2_SIG_DET_EINT_MASK 0x0400 /* AIF1DRC2_SIG_DET_EINT */
+#define WM8994_AIF1DRC2_SIG_DET_EINT_SHIFT 10 /* AIF1DRC2_SIG_DET_EINT */
+#define WM8994_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* AIF1DRC2_SIG_DET_EINT */
+#define WM8994_AIF1DRC1_SIG_DET_EINT 0x0200 /* AIF1DRC1_SIG_DET_EINT */
+#define WM8994_AIF1DRC1_SIG_DET_EINT_MASK 0x0200 /* AIF1DRC1_SIG_DET_EINT */
+#define WM8994_AIF1DRC1_SIG_DET_EINT_SHIFT 9 /* AIF1DRC1_SIG_DET_EINT */
+#define WM8994_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* AIF1DRC1_SIG_DET_EINT */
+#define WM8994_SRC2_LOCK_EINT 0x0100 /* SRC2_LOCK_EINT */
+#define WM8994_SRC2_LOCK_EINT_MASK 0x0100 /* SRC2_LOCK_EINT */
+#define WM8994_SRC2_LOCK_EINT_SHIFT 8 /* SRC2_LOCK_EINT */
+#define WM8994_SRC2_LOCK_EINT_WIDTH 1 /* SRC2_LOCK_EINT */
+#define WM8994_SRC1_LOCK_EINT 0x0080 /* SRC1_LOCK_EINT */
+#define WM8994_SRC1_LOCK_EINT_MASK 0x0080 /* SRC1_LOCK_EINT */
+#define WM8994_SRC1_LOCK_EINT_SHIFT 7 /* SRC1_LOCK_EINT */
+#define WM8994_SRC1_LOCK_EINT_WIDTH 1 /* SRC1_LOCK_EINT */
+#define WM8994_FLL2_LOCK_EINT 0x0040 /* FLL2_LOCK_EINT */
+#define WM8994_FLL2_LOCK_EINT_MASK 0x0040 /* FLL2_LOCK_EINT */
+#define WM8994_FLL2_LOCK_EINT_SHIFT 6 /* FLL2_LOCK_EINT */
+#define WM8994_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */
+#define WM8994_FLL1_LOCK_EINT 0x0020 /* FLL1_LOCK_EINT */
+#define WM8994_FLL1_LOCK_EINT_MASK 0x0020 /* FLL1_LOCK_EINT */
+#define WM8994_FLL1_LOCK_EINT_SHIFT 5 /* FLL1_LOCK_EINT */
+#define WM8994_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */
+#define WM8994_MIC2_SHRT_EINT 0x0010 /* MIC2_SHRT_EINT */
+#define WM8994_MIC2_SHRT_EINT_MASK 0x0010 /* MIC2_SHRT_EINT */
+#define WM8994_MIC2_SHRT_EINT_SHIFT 4 /* MIC2_SHRT_EINT */
+#define WM8994_MIC2_SHRT_EINT_WIDTH 1 /* MIC2_SHRT_EINT */
+#define WM8994_MIC2_DET_EINT 0x0008 /* MIC2_DET_EINT */
+#define WM8994_MIC2_DET_EINT_MASK 0x0008 /* MIC2_DET_EINT */
+#define WM8994_MIC2_DET_EINT_SHIFT 3 /* MIC2_DET_EINT */
+#define WM8994_MIC2_DET_EINT_WIDTH 1 /* MIC2_DET_EINT */
+#define WM8994_MIC1_SHRT_EINT 0x0004 /* MIC1_SHRT_EINT */
+#define WM8994_MIC1_SHRT_EINT_MASK 0x0004 /* MIC1_SHRT_EINT */
+#define WM8994_MIC1_SHRT_EINT_SHIFT 2 /* MIC1_SHRT_EINT */
+#define WM8994_MIC1_SHRT_EINT_WIDTH 1 /* MIC1_SHRT_EINT */
+#define WM8994_MIC1_DET_EINT 0x0002 /* MIC1_DET_EINT */
+#define WM8994_MIC1_DET_EINT_MASK 0x0002 /* MIC1_DET_EINT */
+#define WM8994_MIC1_DET_EINT_SHIFT 1 /* MIC1_DET_EINT */
+#define WM8994_MIC1_DET_EINT_WIDTH 1 /* MIC1_DET_EINT */
+#define WM8994_TEMP_SHUT_EINT 0x0001 /* TEMP_SHUT_EINT */
+#define WM8994_TEMP_SHUT_EINT_MASK 0x0001 /* TEMP_SHUT_EINT */
+#define WM8994_TEMP_SHUT_EINT_SHIFT 0 /* TEMP_SHUT_EINT */
+#define WM8994_TEMP_SHUT_EINT_WIDTH 1 /* TEMP_SHUT_EINT */
+
+/*
+ * R1842 (0x732) - Interrupt Raw Status 2
+ */
+#define WM8994_TEMP_WARN_STS 0x8000 /* TEMP_WARN_STS */
+#define WM8994_TEMP_WARN_STS_MASK 0x8000 /* TEMP_WARN_STS */
+#define WM8994_TEMP_WARN_STS_SHIFT 15 /* TEMP_WARN_STS */
+#define WM8994_TEMP_WARN_STS_WIDTH 1 /* TEMP_WARN_STS */
+#define WM8994_DCS_DONE_STS 0x4000 /* DCS_DONE_STS */
+#define WM8994_DCS_DONE_STS_MASK 0x4000 /* DCS_DONE_STS */
+#define WM8994_DCS_DONE_STS_SHIFT 14 /* DCS_DONE_STS */
+#define WM8994_DCS_DONE_STS_WIDTH 1 /* DCS_DONE_STS */
+#define WM8994_WSEQ_DONE_STS 0x2000 /* WSEQ_DONE_STS */
+#define WM8994_WSEQ_DONE_STS_MASK 0x2000 /* WSEQ_DONE_STS */
+#define WM8994_WSEQ_DONE_STS_SHIFT 13 /* WSEQ_DONE_STS */
+#define WM8994_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */
+#define WM8994_FIFOS_ERR_STS 0x1000 /* FIFOS_ERR_STS */
+#define WM8994_FIFOS_ERR_STS_MASK 0x1000 /* FIFOS_ERR_STS */
+#define WM8994_FIFOS_ERR_STS_SHIFT 12 /* FIFOS_ERR_STS */
+#define WM8994_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */
+#define WM8994_AIF2DRC_SIG_DET_STS 0x0800 /* AIF2DRC_SIG_DET_STS */
+#define WM8994_AIF2DRC_SIG_DET_STS_MASK 0x0800 /* AIF2DRC_SIG_DET_STS */
+#define WM8994_AIF2DRC_SIG_DET_STS_SHIFT 11 /* AIF2DRC_SIG_DET_STS */
+#define WM8994_AIF2DRC_SIG_DET_STS_WIDTH 1 /* AIF2DRC_SIG_DET_STS */
+#define WM8994_AIF1DRC2_SIG_DET_STS 0x0400 /* AIF1DRC2_SIG_DET_STS */
+#define WM8994_AIF1DRC2_SIG_DET_STS_MASK 0x0400 /* AIF1DRC2_SIG_DET_STS */
+#define WM8994_AIF1DRC2_SIG_DET_STS_SHIFT 10 /* AIF1DRC2_SIG_DET_STS */
+#define WM8994_AIF1DRC2_SIG_DET_STS_WIDTH 1 /* AIF1DRC2_SIG_DET_STS */
+#define WM8994_AIF1DRC1_SIG_DET_STS 0x0200 /* AIF1DRC1_SIG_DET_STS */
+#define WM8994_AIF1DRC1_SIG_DET_STS_MASK 0x0200 /* AIF1DRC1_SIG_DET_STS */
+#define WM8994_AIF1DRC1_SIG_DET_STS_SHIFT 9 /* AIF1DRC1_SIG_DET_STS */
+#define WM8994_AIF1DRC1_SIG_DET_STS_WIDTH 1 /* AIF1DRC1_SIG_DET_STS */
+#define WM8994_SRC2_LOCK_STS 0x0100 /* SRC2_LOCK_STS */
+#define WM8994_SRC2_LOCK_STS_MASK 0x0100 /* SRC2_LOCK_STS */
+#define WM8994_SRC2_LOCK_STS_SHIFT 8 /* SRC2_LOCK_STS */
+#define WM8994_SRC2_LOCK_STS_WIDTH 1 /* SRC2_LOCK_STS */
+#define WM8994_SRC1_LOCK_STS 0x0080 /* SRC1_LOCK_STS */
+#define WM8994_SRC1_LOCK_STS_MASK 0x0080 /* SRC1_LOCK_STS */
+#define WM8994_SRC1_LOCK_STS_SHIFT 7 /* SRC1_LOCK_STS */
+#define WM8994_SRC1_LOCK_STS_WIDTH 1 /* SRC1_LOCK_STS */
+#define WM8994_FLL2_LOCK_STS 0x0040 /* FLL2_LOCK_STS */
+#define WM8994_FLL2_LOCK_STS_MASK 0x0040 /* FLL2_LOCK_STS */
+#define WM8994_FLL2_LOCK_STS_SHIFT 6 /* FLL2_LOCK_STS */
+#define WM8994_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */
+#define WM8994_FLL1_LOCK_STS 0x0020 /* FLL1_LOCK_STS */
+#define WM8994_FLL1_LOCK_STS_MASK 0x0020 /* FLL1_LOCK_STS */
+#define WM8994_FLL1_LOCK_STS_SHIFT 5 /* FLL1_LOCK_STS */
+#define WM8994_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */
+#define WM8994_MIC2_SHRT_STS 0x0010 /* MIC2_SHRT_STS */
+#define WM8994_MIC2_SHRT_STS_MASK 0x0010 /* MIC2_SHRT_STS */
+#define WM8994_MIC2_SHRT_STS_SHIFT 4 /* MIC2_SHRT_STS */
+#define WM8994_MIC2_SHRT_STS_WIDTH 1 /* MIC2_SHRT_STS */
+#define WM8994_MIC2_DET_STS 0x0008 /* MIC2_DET_STS */
+#define WM8994_MIC2_DET_STS_MASK 0x0008 /* MIC2_DET_STS */
+#define WM8994_MIC2_DET_STS_SHIFT 3 /* MIC2_DET_STS */
+#define WM8994_MIC2_DET_STS_WIDTH 1 /* MIC2_DET_STS */
+#define WM8994_MIC1_SHRT_STS 0x0004 /* MIC1_SHRT_STS */
+#define WM8994_MIC1_SHRT_STS_MASK 0x0004 /* MIC1_SHRT_STS */
+#define WM8994_MIC1_SHRT_STS_SHIFT 2 /* MIC1_SHRT_STS */
+#define WM8994_MIC1_SHRT_STS_WIDTH 1 /* MIC1_SHRT_STS */
+#define WM8994_MIC1_DET_STS 0x0002 /* MIC1_DET_STS */
+#define WM8994_MIC1_DET_STS_MASK 0x0002 /* MIC1_DET_STS */
+#define WM8994_MIC1_DET_STS_SHIFT 1 /* MIC1_DET_STS */
+#define WM8994_MIC1_DET_STS_WIDTH 1 /* MIC1_DET_STS */
+#define WM8994_TEMP_SHUT_STS 0x0001 /* TEMP_SHUT_STS */
+#define WM8994_TEMP_SHUT_STS_MASK 0x0001 /* TEMP_SHUT_STS */
+#define WM8994_TEMP_SHUT_STS_SHIFT 0 /* TEMP_SHUT_STS */
+#define WM8994_TEMP_SHUT_STS_WIDTH 1 /* TEMP_SHUT_STS */
+
+/*
+ * R1848 (0x738) - Interrupt Status 1 Mask
+ */
+#define WM8994_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */
+#define WM8994_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */
+#define WM8994_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */
+#define WM8994_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */
+#define WM8994_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */
+#define WM8994_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */
+#define WM8994_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */
+#define WM8994_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */
+#define WM8994_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */
+#define WM8994_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */
+#define WM8994_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */
+#define WM8994_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */
+#define WM8994_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */
+#define WM8994_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */
+#define WM8994_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */
+#define WM8994_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */
+#define WM8994_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */
+#define WM8994_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */
+#define WM8994_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */
+#define WM8994_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */
+#define WM8994_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */
+#define WM8994_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */
+#define WM8994_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */
+#define WM8994_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */
+#define WM8994_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
+#define WM8994_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
+#define WM8994_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
+#define WM8994_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
+#define WM8994_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
+#define WM8994_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
+#define WM8994_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
+#define WM8994_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
+#define WM8994_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
+#define WM8994_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
+#define WM8994_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
+#define WM8994_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
+#define WM8994_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
+#define WM8994_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
+#define WM8994_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
+#define WM8994_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
+#define WM8994_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
+#define WM8994_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
+#define WM8994_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
+#define WM8994_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
+
+/*
+ * R1849 (0x739) - Interrupt Status 2 Mask
+ */
+#define WM8994_IM_TEMP_WARN_EINT 0x8000 /* IM_TEMP_WARN_EINT */
+#define WM8994_IM_TEMP_WARN_EINT_MASK 0x8000 /* IM_TEMP_WARN_EINT */
+#define WM8994_IM_TEMP_WARN_EINT_SHIFT 15 /* IM_TEMP_WARN_EINT */
+#define WM8994_IM_TEMP_WARN_EINT_WIDTH 1 /* IM_TEMP_WARN_EINT */
+#define WM8994_IM_DCS_DONE_EINT 0x4000 /* IM_DCS_DONE_EINT */
+#define WM8994_IM_DCS_DONE_EINT_MASK 0x4000 /* IM_DCS_DONE_EINT */
+#define WM8994_IM_DCS_DONE_EINT_SHIFT 14 /* IM_DCS_DONE_EINT */
+#define WM8994_IM_DCS_DONE_EINT_WIDTH 1 /* IM_DCS_DONE_EINT */
+#define WM8994_IM_WSEQ_DONE_EINT 0x2000 /* IM_WSEQ_DONE_EINT */
+#define WM8994_IM_WSEQ_DONE_EINT_MASK 0x2000 /* IM_WSEQ_DONE_EINT */
+#define WM8994_IM_WSEQ_DONE_EINT_SHIFT 13 /* IM_WSEQ_DONE_EINT */
+#define WM8994_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */
+#define WM8994_IM_FIFOS_ERR_EINT 0x1000 /* IM_FIFOS_ERR_EINT */
+#define WM8994_IM_FIFOS_ERR_EINT_MASK 0x1000 /* IM_FIFOS_ERR_EINT */
+#define WM8994_IM_FIFOS_ERR_EINT_SHIFT 12 /* IM_FIFOS_ERR_EINT */
+#define WM8994_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */
+#define WM8994_IM_AIF2DRC_SIG_DET_EINT 0x0800 /* IM_AIF2DRC_SIG_DET_EINT */
+#define WM8994_IM_AIF2DRC_SIG_DET_EINT_MASK 0x0800 /* IM_AIF2DRC_SIG_DET_EINT */
+#define WM8994_IM_AIF2DRC_SIG_DET_EINT_SHIFT 11 /* IM_AIF2DRC_SIG_DET_EINT */
+#define WM8994_IM_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* IM_AIF2DRC_SIG_DET_EINT */
+#define WM8994_IM_AIF1DRC2_SIG_DET_EINT 0x0400 /* IM_AIF1DRC2_SIG_DET_EINT */
+#define WM8994_IM_AIF1DRC2_SIG_DET_EINT_MASK 0x0400 /* IM_AIF1DRC2_SIG_DET_EINT */
+#define WM8994_IM_AIF1DRC2_SIG_DET_EINT_SHIFT 10 /* IM_AIF1DRC2_SIG_DET_EINT */
+#define WM8994_IM_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC2_SIG_DET_EINT */
+#define WM8994_IM_AIF1DRC1_SIG_DET_EINT 0x0200 /* IM_AIF1DRC1_SIG_DET_EINT */
+#define WM8994_IM_AIF1DRC1_SIG_DET_EINT_MASK 0x0200 /* IM_AIF1DRC1_SIG_DET_EINT */
+#define WM8994_IM_AIF1DRC1_SIG_DET_EINT_SHIFT 9 /* IM_AIF1DRC1_SIG_DET_EINT */
+#define WM8994_IM_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC1_SIG_DET_EINT */
+#define WM8994_IM_SRC2_LOCK_EINT 0x0100 /* IM_SRC2_LOCK_EINT */
+#define WM8994_IM_SRC2_LOCK_EINT_MASK 0x0100 /* IM_SRC2_LOCK_EINT */
+#define WM8994_IM_SRC2_LOCK_EINT_SHIFT 8 /* IM_SRC2_LOCK_EINT */
+#define WM8994_IM_SRC2_LOCK_EINT_WIDTH 1 /* IM_SRC2_LOCK_EINT */
+#define WM8994_IM_SRC1_LOCK_EINT 0x0080 /* IM_SRC1_LOCK_EINT */
+#define WM8994_IM_SRC1_LOCK_EINT_MASK 0x0080 /* IM_SRC1_LOCK_EINT */
+#define WM8994_IM_SRC1_LOCK_EINT_SHIFT 7 /* IM_SRC1_LOCK_EINT */
+#define WM8994_IM_SRC1_LOCK_EINT_WIDTH 1 /* IM_SRC1_LOCK_EINT */
+#define WM8994_IM_FLL2_LOCK_EINT 0x0040 /* IM_FLL2_LOCK_EINT */
+#define WM8994_IM_FLL2_LOCK_EINT_MASK 0x0040 /* IM_FLL2_LOCK_EINT */
+#define WM8994_IM_FLL2_LOCK_EINT_SHIFT 6 /* IM_FLL2_LOCK_EINT */
+#define WM8994_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */
+#define WM8994_IM_FLL1_LOCK_EINT 0x0020 /* IM_FLL1_LOCK_EINT */
+#define WM8994_IM_FLL1_LOCK_EINT_MASK 0x0020 /* IM_FLL1_LOCK_EINT */
+#define WM8994_IM_FLL1_LOCK_EINT_SHIFT 5 /* IM_FLL1_LOCK_EINT */
+#define WM8994_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */
+#define WM8994_IM_MIC2_SHRT_EINT 0x0010 /* IM_MIC2_SHRT_EINT */
+#define WM8994_IM_MIC2_SHRT_EINT_MASK 0x0010 /* IM_MIC2_SHRT_EINT */
+#define WM8994_IM_MIC2_SHRT_EINT_SHIFT 4 /* IM_MIC2_SHRT_EINT */
+#define WM8994_IM_MIC2_SHRT_EINT_WIDTH 1 /* IM_MIC2_SHRT_EINT */
+#define WM8994_IM_MIC2_DET_EINT 0x0008 /* IM_MIC2_DET_EINT */
+#define WM8994_IM_MIC2_DET_EINT_MASK 0x0008 /* IM_MIC2_DET_EINT */
+#define WM8994_IM_MIC2_DET_EINT_SHIFT 3 /* IM_MIC2_DET_EINT */
+#define WM8994_IM_MIC2_DET_EINT_WIDTH 1 /* IM_MIC2_DET_EINT */
+#define WM8994_IM_MIC1_SHRT_EINT 0x0004 /* IM_MIC1_SHRT_EINT */
+#define WM8994_IM_MIC1_SHRT_EINT_MASK 0x0004 /* IM_MIC1_SHRT_EINT */
+#define WM8994_IM_MIC1_SHRT_EINT_SHIFT 2 /* IM_MIC1_SHRT_EINT */
+#define WM8994_IM_MIC1_SHRT_EINT_WIDTH 1 /* IM_MIC1_SHRT_EINT */
+#define WM8994_IM_MIC1_DET_EINT 0x0002 /* IM_MIC1_DET_EINT */
+#define WM8994_IM_MIC1_DET_EINT_MASK 0x0002 /* IM_MIC1_DET_EINT */
+#define WM8994_IM_MIC1_DET_EINT_SHIFT 1 /* IM_MIC1_DET_EINT */
+#define WM8994_IM_MIC1_DET_EINT_WIDTH 1 /* IM_MIC1_DET_EINT */
+#define WM8994_IM_TEMP_SHUT_EINT 0x0001 /* IM_TEMP_SHUT_EINT */
+#define WM8994_IM_TEMP_SHUT_EINT_MASK 0x0001 /* IM_TEMP_SHUT_EINT */
+#define WM8994_IM_TEMP_SHUT_EINT_SHIFT 0 /* IM_TEMP_SHUT_EINT */
+#define WM8994_IM_TEMP_SHUT_EINT_WIDTH 1 /* IM_TEMP_SHUT_EINT */
+
+/*
+ * R1856 (0x740) - Interrupt Control
+ */
+#define WM8994_IM_IRQ 0x0001 /* IM_IRQ */
+#define WM8994_IM_IRQ_MASK 0x0001 /* IM_IRQ */
+#define WM8994_IM_IRQ_SHIFT 0 /* IM_IRQ */
+#define WM8994_IM_IRQ_WIDTH 1 /* IM_IRQ */
+
+/*
+ * R1864 (0x748) - IRQ Debounce
+ */
+#define WM8994_TEMP_WARN_DB 0x0020 /* TEMP_WARN_DB */
+#define WM8994_TEMP_WARN_DB_MASK 0x0020 /* TEMP_WARN_DB */
+#define WM8994_TEMP_WARN_DB_SHIFT 5 /* TEMP_WARN_DB */
+#define WM8994_TEMP_WARN_DB_WIDTH 1 /* TEMP_WARN_DB */
+#define WM8994_MIC2_SHRT_DB 0x0010 /* MIC2_SHRT_DB */
+#define WM8994_MIC2_SHRT_DB_MASK 0x0010 /* MIC2_SHRT_DB */
+#define WM8994_MIC2_SHRT_DB_SHIFT 4 /* MIC2_SHRT_DB */
+#define WM8994_MIC2_SHRT_DB_WIDTH 1 /* MIC2_SHRT_DB */
+#define WM8994_MIC2_DET_DB 0x0008 /* MIC2_DET_DB */
+#define WM8994_MIC2_DET_DB_MASK 0x0008 /* MIC2_DET_DB */
+#define WM8994_MIC2_DET_DB_SHIFT 3 /* MIC2_DET_DB */
+#define WM8994_MIC2_DET_DB_WIDTH 1 /* MIC2_DET_DB */
+#define WM8994_MIC1_SHRT_DB 0x0004 /* MIC1_SHRT_DB */
+#define WM8994_MIC1_SHRT_DB_MASK 0x0004 /* MIC1_SHRT_DB */
+#define WM8994_MIC1_SHRT_DB_SHIFT 2 /* MIC1_SHRT_DB */
+#define WM8994_MIC1_SHRT_DB_WIDTH 1 /* MIC1_SHRT_DB */
+#define WM8994_MIC1_DET_DB 0x0002 /* MIC1_DET_DB */
+#define WM8994_MIC1_DET_DB_MASK 0x0002 /* MIC1_DET_DB */
+#define WM8994_MIC1_DET_DB_SHIFT 1 /* MIC1_DET_DB */
+#define WM8994_MIC1_DET_DB_WIDTH 1 /* MIC1_DET_DB */
+#define WM8994_TEMP_SHUT_DB 0x0001 /* TEMP_SHUT_DB */
+#define WM8994_TEMP_SHUT_DB_MASK 0x0001 /* TEMP_SHUT_DB */
+#define WM8994_TEMP_SHUT_DB_SHIFT 0 /* TEMP_SHUT_DB */
+#define WM8994_TEMP_SHUT_DB_WIDTH 1 /* TEMP_SHUT_DB */
+
+#endif
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index c1410e3191e3..ea8b4e37a86e 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -206,6 +206,12 @@
.get = snd_soc_dapm_get_enum_double, \
.put = snd_soc_dapm_put_enum_double, \
.private_value = (unsigned long)&xenum }
+#define SOC_DAPM_ENUM_VIRT(xname, xenum) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+ .info = snd_soc_info_enum_double, \
+ .get = snd_soc_dapm_get_enum_virt, \
+ .put = snd_soc_dapm_put_enum_virt, \
+ .private_value = (unsigned long)&xenum }
#define SOC_DAPM_VALUE_ENUM(xname, xenum) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = snd_soc_info_enum_double, \
@@ -260,6 +266,10 @@ int snd_soc_dapm_get_enum_double(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int snd_soc_dapm_put_enum_double(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
+int snd_soc_dapm_get_enum_virt(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+int snd_soc_dapm_put_enum_virt(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
int snd_soc_dapm_get_value_enum_double(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int snd_soc_dapm_put_value_enum_double(struct snd_kcontrol *kcontrol,
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 78e38548c35b..1d0c6bf24363 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -69,8 +69,8 @@ config SND_SOC_ALL_CODECS
config SND_SOC_WM_HUBS
tristate
- default y if SND_SOC_WM8993=y
- default m if SND_SOC_WM8993=m
+ default y if SND_SOC_WM8993=y || SND_SOC_WM8994=y
+ default m if SND_SOC_WM8993=m || SND_SOC_WM8994=m
config SND_SOC_AC97_CODEC
tristate
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index af1958f5b388..f6715122c1d0 100755
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -1,11 +1,11 @@
/*
- * wm8994.c -- WM8994 ALSA SoC audio driver
+ * wm8994.c -- WM8994 ALSA SoC Audio driver
*
* Copyright 2009 Wolfson Microelectronics plc
- * Copyright 2005 Openedhand Ltd.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
@@ -17,34 +17,34 @@
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
-#include <linux/spi/spi.h>
#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
-#include <sound/tlv.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
+#include <sound/tlv.h>
-#include <mach/iomux.h>
-#include <mach/gpio.h>
+#include <linux/mfd/wm8994/core.h>
+#include <linux/mfd/wm8994/registers.h>
+#include <linux/mfd/wm8994/pdata.h>
+#include <linux/mfd/wm8994/gpio.h>
#include "wm8994.h"
-#include <linux/miscdevice.h>
-#include <linux/circ_buf.h>
-#include <mach/spi_fpga.h>
+#include "wm_hubs.h"
-/* If digital BB is used,open this define. */
-//#define PCM_BB
+//#include<asm/string.h>
+#include <linux/vmalloc.h>
-/* Define what kind of digital BB is used. */
-#ifdef PCM_BB
-#define TD688_MODE
-//#define MU301_MODE
-//#define CHONGY_MODE
-//#define THINKWILL_M800_MODE
-#endif //PCM_BB
+#define WM8994_PROC
+#ifdef WM8994_PROC
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+char debug_write_read = 0;
+#endif
#if 1
#define DBG(x...) printk(KERN_INFO x)
@@ -52,2655 +52,3457 @@
#define DBG(x...) do { } while (0)
#endif
-#define wm8994_mic_VCC 0x0010
-#define WM8994_DELAY 50
+#if 0
+#define DBG_CLK(x...) printk(KERN_INFO x)
+#else
+#define DBG_CLK(x...) do { } while (0)
+#endif
-struct i2c_client *wm8994_client;
-//struct wm8994_board wm8994_codec_board_data;
-int reg_send_data(struct i2c_client *client, unsigned short *reg, unsigned short *data, u32 scl_rate);
-int reg_recv_data(struct i2c_client *client, unsigned short *reg, unsigned short *buf, u32 scl_rate);
+#if 0
+#define DBG_INFO(x...) dev_info(x)
+#else
+#define DBG_INFO(x...) do { } while (0)
+#endif
-enum wm8994_codec_mode
-{
- wm8994_AP_to_headset,
- wm8994_AP_to_speakers,
- wm8994_recorder_and_AP_to_headset,
- wm8994_recorder_and_AP_to_speakers,
- wm8994_FM_to_headset,
- wm8994_FM_to_headset_and_record,
- wm8994_FM_to_speakers,
- wm8994_FM_to_speakers_and_record,
- wm8994_handsetMIC_to_baseband_to_headset,
- wm8994_handsetMIC_to_baseband_to_headset_and_record,
- wm8994_mainMIC_to_baseband_to_earpiece,
- wm8994_mainMIC_to_baseband_to_earpiece_and_record,
- wm8994_mainMIC_to_baseband_to_speakers,
- wm8994_mainMIC_to_baseband_with_AP_to_speakers,
- wm8994_mainMIC_to_baseband_to_speakers_and_record,
- wm8994_BT_baseband,
- wm8994_BT_baseband_and_record,
- null
-};
-/* wm8994_current_mode:save current wm8994 mode */
-unsigned char wm8994_current_mode=null;//,wm8994_mic_VCC=0x0000;
-void wm8994_set_volume(unsigned char wm8994_mode,unsigned char volume,unsigned char max_volume);
+static struct snd_soc_codec *wm8994_codec;
+struct snd_soc_codec_device soc_codec_dev_wm8994;
-enum stream_type_wm8994
-{
- VOICE_CALL =0,
- BLUETOOTH_SCO =6,
+struct fll_config {
+ int src;
+ int in;
+ int out;
};
-/* For voice device route set, add by phc */
-enum VoiceDeviceSwitch
-{
- SPEAKER_INCALL,
- SPEAKER_NORMAL,
-
- HEADSET_INCALL,
- HEADSET_NORMAL,
-
- EARPIECE_INCALL,
- EARPIECE_NORMAL,
-
- BLUETOOTH_SCO_INCALL,
- BLUETOOTH_SCO_NORMAL,
-
- BLUETOOTH_A2DP_INCALL,
- BLUETOOTH_A2DP_NORMAL,
-
- MIC_CAPTURE,
+#define WM8994_NUM_DRC 3
+#define WM8994_NUM_EQ 3
- EARPIECE_RINGTONE,
- SPEAKER_RINGTONE,
- HEADSET_RINGTONE,
-
- ALL_OPEN,
- ALL_CLOSED
+static int wm8994_drc_base[] = {
+ WM8994_AIF1_DRC1_1,
+ WM8994_AIF1_DRC2_1,
+ WM8994_AIF2_DRC_1,
};
-
-#define call_maxvol 5
-
-/* call_vol: save all kinds of system volume value. */
-unsigned char call_vol=3;
-int vol;
-unsigned short headset_vol_table[6] ={0x0100,0x011d,0x012d,0x0135,0x013b,0x013f};
-unsigned short speakers_vol_table[6] ={0x0100,0x011d,0x012d,0x0135,0x013b,0x013f};
-unsigned short earpiece_vol_table[6] ={0x0100,0x011d,0x012d,0x0135,0x013b,0x013f};
-unsigned short BT_vol_table[6] ={0x0100,0x011d,0x012d,0x0135,0x013b,0x013f};
-
-/*
- * wm8994 register cache
- * We can't read the WM8994 register space when we
- * are using 2 wire for device control, so we cache them instead.
- */
-static const u16 wm8994_reg[] = {
- 0x0097, 0x0097, 0x0079, 0x0079, /* 0 */
- 0x0000, 0x0008, 0x0000, 0x000a, /* 4 */
- 0x0000, 0x0000, 0x00ff, 0x00ff, /* 8 */
- 0x000f, 0x000f, 0x0000, 0x0000, /* 12 */
- 0x0000, 0x007b, 0x0000, 0x0032, /* 16 */
- 0x0000, 0x00c3, 0x00c3, 0x00c0, /* 20 */
- 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
- 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
- 0x0000, 0x0000, 0x0050, 0x0050, /* 32 */
- 0x0050, 0x0050, 0x0050, 0x0050, /* 36 */
- 0x0079, 0x0079, 0x0079, /* 40 */
+static int wm8994_retune_mobile_base[] = {
+ WM8994_AIF1_DAC1_EQ_GAINS_1,
+ WM8994_AIF1_DAC2_EQ_GAINS_1,
+ WM8994_AIF2_EQ_GAINS_1,
};
+#define WM8994_REG_CACHE_SIZE 0x621
+
/* codec private data */
struct wm8994_priv {
- unsigned int sysclk;
+ struct wm_hubs_data hubs;
struct snd_soc_codec codec;
- struct snd_pcm_hw_constraint_list *sysclk_constraints;
- u16 reg_cache[WM8994_NUM_REG];
+ u16 reg_cache[WM8994_REG_CACHE_SIZE + 1];
+ int sysclk[2];
+ int sysclk_rate[2];
+ int mclk[2];
+ int aifclk[2];
+ struct fll_config fll[2], fll_suspend[2];
+
+ int dac_rates[2];
+ int lrclk_shared[2];
+
+ /* Platform dependant DRC configuration */
+ const char **drc_texts;
+ int drc_cfg[WM8994_NUM_DRC];
+ struct soc_enum drc_enum;
+
+ /* Platform dependant ReTune mobile configuration */
+ int num_retune_mobile_texts;
+ const char **retune_mobile_texts;
+ int retune_mobile_cfg[WM8994_NUM_EQ];
+ struct soc_enum retune_mobile_enum;
+
+ struct wm8994_pdata *pdata;
+};
+
+static struct {
+ unsigned short readable; /* Mask of readable bits */
+ unsigned short writable; /* Mask of writable bits */
+ unsigned short vol; /* Mask of volatile bits */
+} access_masks[] = {
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R0 - Software Reset */
+ { 0x3B37, 0x3B37, 0x0000 }, /* R1 - Power Management (1) */
+ { 0x6BF0, 0x6BF0, 0x0000 }, /* R2 - Power Management (2) */
+ { 0x3FF0, 0x3FF0, 0x0000 }, /* R3 - Power Management (3) */
+ { 0x3F3F, 0x3F3F, 0x0000 }, /* R4 - Power Management (4) */
+ { 0x3F0F, 0x3F0F, 0x0000 }, /* R5 - Power Management (5) */
+ { 0x003F, 0x003F, 0x0000 }, /* R6 - Power Management (6) */
+ { 0x0000, 0x0000, 0x0000 }, /* R7 */
+ { 0x0000, 0x0000, 0x0000 }, /* R8 */
+ { 0x0000, 0x0000, 0x0000 }, /* R9 */
+ { 0x0000, 0x0000, 0x0000 }, /* R10 */
+ { 0x0000, 0x0000, 0x0000 }, /* R11 */
+ { 0x0000, 0x0000, 0x0000 }, /* R12 */
+ { 0x0000, 0x0000, 0x0000 }, /* R13 */
+ { 0x0000, 0x0000, 0x0000 }, /* R14 */
+ { 0x0000, 0x0000, 0x0000 }, /* R15 */
+ { 0x0000, 0x0000, 0x0000 }, /* R16 */
+ { 0x0000, 0x0000, 0x0000 }, /* R17 */
+ { 0x0000, 0x0000, 0x0000 }, /* R18 */
+ { 0x0000, 0x0000, 0x0000 }, /* R19 */
+ { 0x0000, 0x0000, 0x0000 }, /* R20 */
+ { 0x01C0, 0x01C0, 0x0000 }, /* R21 - Input Mixer (1) */
+ { 0x0000, 0x0000, 0x0000 }, /* R22 */
+ { 0x0000, 0x0000, 0x0000 }, /* R23 */
+ { 0x00DF, 0x01DF, 0x0000 }, /* R24 - Left Line Input 1&2 Volume */
+ { 0x00DF, 0x01DF, 0x0000 }, /* R25 - Left Line Input 3&4 Volume */
+ { 0x00DF, 0x01DF, 0x0000 }, /* R26 - Right Line Input 1&2 Volume */
+ { 0x00DF, 0x01DF, 0x0000 }, /* R27 - Right Line Input 3&4 Volume */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R28 - Left Output Volume */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R29 - Right Output Volume */
+ { 0x0077, 0x0077, 0x0000 }, /* R30 - Line Outputs Volume */
+ { 0x0030, 0x0030, 0x0000 }, /* R31 - HPOUT2 Volume */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R32 - Left OPGA Volume */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R33 - Right OPGA Volume */
+ { 0x007F, 0x007F, 0x0000 }, /* R34 - SPKMIXL Attenuation */
+ { 0x017F, 0x017F, 0x0000 }, /* R35 - SPKMIXR Attenuation */
+ { 0x003F, 0x003F, 0x0000 }, /* R36 - SPKOUT Mixers */
+ { 0x003F, 0x003F, 0x0000 }, /* R37 - ClassD */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R38 - Speaker Volume Left */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R39 - Speaker Volume Right */
+ { 0x00FF, 0x00FF, 0x0000 }, /* R40 - Input Mixer (2) */
+ { 0x01B7, 0x01B7, 0x0000 }, /* R41 - Input Mixer (3) */
+ { 0x01B7, 0x01B7, 0x0000 }, /* R42 - Input Mixer (4) */
+ { 0x01C7, 0x01C7, 0x0000 }, /* R43 - Input Mixer (5) */
+ { 0x01C7, 0x01C7, 0x0000 }, /* R44 - Input Mixer (6) */
+ { 0x01FF, 0x01FF, 0x0000 }, /* R45 - Output Mixer (1) */
+ { 0x01FF, 0x01FF, 0x0000 }, /* R46 - Output Mixer (2) */
+ { 0x0FFF, 0x0FFF, 0x0000 }, /* R47 - Output Mixer (3) */
+ { 0x0FFF, 0x0FFF, 0x0000 }, /* R48 - Output Mixer (4) */
+ { 0x0FFF, 0x0FFF, 0x0000 }, /* R49 - Output Mixer (5) */
+ { 0x0FFF, 0x0FFF, 0x0000 }, /* R50 - Output Mixer (6) */
+ { 0x0038, 0x0038, 0x0000 }, /* R51 - HPOUT2 Mixer */
+ { 0x0077, 0x0077, 0x0000 }, /* R52 - Line Mixer (1) */
+ { 0x0077, 0x0077, 0x0000 }, /* R53 - Line Mixer (2) */
+ { 0x03FF, 0x03FF, 0x0000 }, /* R54 - Speaker Mixer */
+ { 0x00C1, 0x00C1, 0x0000 }, /* R55 - Additional Control */
+ { 0x00F0, 0x00F0, 0x0000 }, /* R56 - AntiPOP (1) */
+ { 0x01EF, 0x01EF, 0x0000 }, /* R57 - AntiPOP (2) */
+ { 0x00FF, 0x00FF, 0x0000 }, /* R58 - MICBIAS */
+ { 0x000F, 0x000F, 0x0000 }, /* R59 - LDO 1 */
+ { 0x0007, 0x0007, 0x0000 }, /* R60 - LDO 2 */
+ { 0x0000, 0x0000, 0x0000 }, /* R61 */
+ { 0x0000, 0x0000, 0x0000 }, /* R62 */
+ { 0x0000, 0x0000, 0x0000 }, /* R63 */
+ { 0x0000, 0x0000, 0x0000 }, /* R64 */
+ { 0x0000, 0x0000, 0x0000 }, /* R65 */
+ { 0x0000, 0x0000, 0x0000 }, /* R66 */
+ { 0x0000, 0x0000, 0x0000 }, /* R67 */
+ { 0x0000, 0x0000, 0x0000 }, /* R68 */
+ { 0x0000, 0x0000, 0x0000 }, /* R69 */
+ { 0x0000, 0x0000, 0x0000 }, /* R70 */
+ { 0x0000, 0x0000, 0x0000 }, /* R71 */
+ { 0x0000, 0x0000, 0x0000 }, /* R72 */
+ { 0x0000, 0x0000, 0x0000 }, /* R73 */
+ { 0x0000, 0x0000, 0x0000 }, /* R74 */
+ { 0x0000, 0x0000, 0x0000 }, /* R75 */
+ { 0x8000, 0x8000, 0x0000 }, /* R76 - Charge Pump (1) */
+ { 0x0000, 0x0000, 0x0000 }, /* R77 */
+ { 0x0000, 0x0000, 0x0000 }, /* R78 */
+ { 0x0000, 0x0000, 0x0000 }, /* R79 */
+ { 0x0000, 0x0000, 0x0000 }, /* R80 */
+ { 0x0301, 0x0301, 0x0000 }, /* R81 - Class W (1) */
+ { 0x0000, 0x0000, 0x0000 }, /* R82 */
+ { 0x0000, 0x0000, 0x0000 }, /* R83 */
+ { 0x333F, 0x333F, 0x0000 }, /* R84 - DC Servo (1) */
+ { 0x0FEF, 0x0FEF, 0x0000 }, /* R85 - DC Servo (2) */
+ { 0x0000, 0x0000, 0x0000 }, /* R86 */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R87 - DC Servo (4) */
+ { 0x0333, 0x0000, 0x0000 }, /* R88 - DC Servo Readback */
+ { 0x0000, 0x0000, 0x0000 }, /* R89 */
+ { 0x0000, 0x0000, 0x0000 }, /* R90 */
+ { 0x0000, 0x0000, 0x0000 }, /* R91 */
+ { 0x0000, 0x0000, 0x0000 }, /* R92 */
+ { 0x0000, 0x0000, 0x0000 }, /* R93 */
+ { 0x0000, 0x0000, 0x0000 }, /* R94 */
+ { 0x0000, 0x0000, 0x0000 }, /* R95 */
+ { 0x00EE, 0x00EE, 0x0000 }, /* R96 - Analogue HP (1) */
+ { 0x0000, 0x0000, 0x0000 }, /* R97 */
+ { 0x0000, 0x0000, 0x0000 }, /* R98 */
+ { 0x0000, 0x0000, 0x0000 }, /* R99 */
+ { 0x0000, 0x0000, 0x0000 }, /* R100 */
+ { 0x0000, 0x0000, 0x0000 }, /* R101 */
+ { 0x0000, 0x0000, 0x0000 }, /* R102 */
+ { 0x0000, 0x0000, 0x0000 }, /* R103 */
+ { 0x0000, 0x0000, 0x0000 }, /* R104 */
+ { 0x0000, 0x0000, 0x0000 }, /* R105 */
+ { 0x0000, 0x0000, 0x0000 }, /* R106 */
+ { 0x0000, 0x0000, 0x0000 }, /* R107 */
+ { 0x0000, 0x0000, 0x0000 }, /* R108 */
+ { 0x0000, 0x0000, 0x0000 }, /* R109 */
+ { 0x0000, 0x0000, 0x0000 }, /* R110 */
+ { 0x0000, 0x0000, 0x0000 }, /* R111 */
+ { 0x0000, 0x0000, 0x0000 }, /* R112 */
+ { 0x0000, 0x0000, 0x0000 }, /* R113 */
+ { 0x0000, 0x0000, 0x0000 }, /* R114 */
+ { 0x0000, 0x0000, 0x0000 }, /* R115 */
+ { 0x0000, 0x0000, 0x0000 }, /* R116 */
+ { 0x0000, 0x0000, 0x0000 }, /* R117 */
+ { 0x0000, 0x0000, 0x0000 }, /* R118 */
+ { 0x0000, 0x0000, 0x0000 }, /* R119 */
+ { 0x0000, 0x0000, 0x0000 }, /* R120 */
+ { 0x0000, 0x0000, 0x0000 }, /* R121 */
+ { 0x0000, 0x0000, 0x0000 }, /* R122 */
+ { 0x0000, 0x0000, 0x0000 }, /* R123 */
+ { 0x0000, 0x0000, 0x0000 }, /* R124 */
+ { 0x0000, 0x0000, 0x0000 }, /* R125 */
+ { 0x0000, 0x0000, 0x0000 }, /* R126 */
+ { 0x0000, 0x0000, 0x0000 }, /* R127 */
+ { 0x0000, 0x0000, 0x0000 }, /* R128 */
+ { 0x0000, 0x0000, 0x0000 }, /* R129 */
+ { 0x0000, 0x0000, 0x0000 }, /* R130 */
+ { 0x0000, 0x0000, 0x0000 }, /* R131 */
+ { 0x0000, 0x0000, 0x0000 }, /* R132 */
+ { 0x0000, 0x0000, 0x0000 }, /* R133 */
+ { 0x0000, 0x0000, 0x0000 }, /* R134 */
+ { 0x0000, 0x0000, 0x0000 }, /* R135 */
+ { 0x0000, 0x0000, 0x0000 }, /* R136 */
+ { 0x0000, 0x0000, 0x0000 }, /* R137 */
+ { 0x0000, 0x0000, 0x0000 }, /* R138 */
+ { 0x0000, 0x0000, 0x0000 }, /* R139 */
+ { 0x0000, 0x0000, 0x0000 }, /* R140 */
+ { 0x0000, 0x0000, 0x0000 }, /* R141 */
+ { 0x0000, 0x0000, 0x0000 }, /* R142 */
+ { 0x0000, 0x0000, 0x0000 }, /* R143 */
+ { 0x0000, 0x0000, 0x0000 }, /* R144 */
+ { 0x0000, 0x0000, 0x0000 }, /* R145 */
+ { 0x0000, 0x0000, 0x0000 }, /* R146 */
+ { 0x0000, 0x0000, 0x0000 }, /* R147 */
+ { 0x0000, 0x0000, 0x0000 }, /* R148 */
+ { 0x0000, 0x0000, 0x0000 }, /* R149 */
+ { 0x0000, 0x0000, 0x0000 }, /* R150 */
+ { 0x0000, 0x0000, 0x0000 }, /* R151 */
+ { 0x0000, 0x0000, 0x0000 }, /* R152 */
+ { 0x0000, 0x0000, 0x0000 }, /* R153 */
+ { 0x0000, 0x0000, 0x0000 }, /* R154 */
+ { 0x0000, 0x0000, 0x0000 }, /* R155 */
+ { 0x0000, 0x0000, 0x0000 }, /* R156 */
+ { 0x0000, 0x0000, 0x0000 }, /* R157 */
+ { 0x0000, 0x0000, 0x0000 }, /* R158 */
+ { 0x0000, 0x0000, 0x0000 }, /* R159 */
+ { 0x0000, 0x0000, 0x0000 }, /* R160 */
+ { 0x0000, 0x0000, 0x0000 }, /* R161 */
+ { 0x0000, 0x0000, 0x0000 }, /* R162 */
+ { 0x0000, 0x0000, 0x0000 }, /* R163 */
+ { 0x0000, 0x0000, 0x0000 }, /* R164 */
+ { 0x0000, 0x0000, 0x0000 }, /* R165 */
+ { 0x0000, 0x0000, 0x0000 }, /* R166 */
+ { 0x0000, 0x0000, 0x0000 }, /* R167 */
+ { 0x0000, 0x0000, 0x0000 }, /* R168 */
+ { 0x0000, 0x0000, 0x0000 }, /* R169 */
+ { 0x0000, 0x0000, 0x0000 }, /* R170 */
+ { 0x0000, 0x0000, 0x0000 }, /* R171 */
+ { 0x0000, 0x0000, 0x0000 }, /* R172 */
+ { 0x0000, 0x0000, 0x0000 }, /* R173 */
+ { 0x0000, 0x0000, 0x0000 }, /* R174 */
+ { 0x0000, 0x0000, 0x0000 }, /* R175 */
+ { 0x0000, 0x0000, 0x0000 }, /* R176 */
+ { 0x0000, 0x0000, 0x0000 }, /* R177 */
+ { 0x0000, 0x0000, 0x0000 }, /* R178 */
+ { 0x0000, 0x0000, 0x0000 }, /* R179 */
+ { 0x0000, 0x0000, 0x0000 }, /* R180 */
+ { 0x0000, 0x0000, 0x0000 }, /* R181 */
+ { 0x0000, 0x0000, 0x0000 }, /* R182 */
+ { 0x0000, 0x0000, 0x0000 }, /* R183 */
+ { 0x0000, 0x0000, 0x0000 }, /* R184 */
+ { 0x0000, 0x0000, 0x0000 }, /* R185 */
+ { 0x0000, 0x0000, 0x0000 }, /* R186 */
+ { 0x0000, 0x0000, 0x0000 }, /* R187 */
+ { 0x0000, 0x0000, 0x0000 }, /* R188 */
+ { 0x0000, 0x0000, 0x0000 }, /* R189 */
+ { 0x0000, 0x0000, 0x0000 }, /* R190 */
+ { 0x0000, 0x0000, 0x0000 }, /* R191 */
+ { 0x0000, 0x0000, 0x0000 }, /* R192 */
+ { 0x0000, 0x0000, 0x0000 }, /* R193 */
+ { 0x0000, 0x0000, 0x0000 }, /* R194 */
+ { 0x0000, 0x0000, 0x0000 }, /* R195 */
+ { 0x0000, 0x0000, 0x0000 }, /* R196 */
+ { 0x0000, 0x0000, 0x0000 }, /* R197 */
+ { 0x0000, 0x0000, 0x0000 }, /* R198 */
+ { 0x0000, 0x0000, 0x0000 }, /* R199 */
+ { 0x0000, 0x0000, 0x0000 }, /* R200 */
+ { 0x0000, 0x0000, 0x0000 }, /* R201 */
+ { 0x0000, 0x0000, 0x0000 }, /* R202 */
+ { 0x0000, 0x0000, 0x0000 }, /* R203 */
+ { 0x0000, 0x0000, 0x0000 }, /* R204 */
+ { 0x0000, 0x0000, 0x0000 }, /* R205 */
+ { 0x0000, 0x0000, 0x0000 }, /* R206 */
+ { 0x0000, 0x0000, 0x0000 }, /* R207 */
+ { 0x0000, 0x0000, 0x0000 }, /* R208 */
+ { 0x0000, 0x0000, 0x0000 }, /* R209 */
+ { 0x0000, 0x0000, 0x0000 }, /* R210 */
+ { 0x0000, 0x0000, 0x0000 }, /* R211 */
+ { 0x0000, 0x0000, 0x0000 }, /* R212 */
+ { 0x0000, 0x0000, 0x0000 }, /* R213 */
+ { 0x0000, 0x0000, 0x0000 }, /* R214 */
+ { 0x0000, 0x0000, 0x0000 }, /* R215 */
+ { 0x0000, 0x0000, 0x0000 }, /* R216 */
+ { 0x0000, 0x0000, 0x0000 }, /* R217 */
+ { 0x0000, 0x0000, 0x0000 }, /* R218 */
+ { 0x0000, 0x0000, 0x0000 }, /* R219 */
+ { 0x0000, 0x0000, 0x0000 }, /* R220 */
+ { 0x0000, 0x0000, 0x0000 }, /* R221 */
+ { 0x0000, 0x0000, 0x0000 }, /* R222 */
+ { 0x0000, 0x0000, 0x0000 }, /* R223 */
+ { 0x0000, 0x0000, 0x0000 }, /* R224 */
+ { 0x0000, 0x0000, 0x0000 }, /* R225 */
+ { 0x0000, 0x0000, 0x0000 }, /* R226 */
+ { 0x0000, 0x0000, 0x0000 }, /* R227 */
+ { 0x0000, 0x0000, 0x0000 }, /* R228 */
+ { 0x0000, 0x0000, 0x0000 }, /* R229 */
+ { 0x0000, 0x0000, 0x0000 }, /* R230 */
+ { 0x0000, 0x0000, 0x0000 }, /* R231 */
+ { 0x0000, 0x0000, 0x0000 }, /* R232 */
+ { 0x0000, 0x0000, 0x0000 }, /* R233 */
+ { 0x0000, 0x0000, 0x0000 }, /* R234 */
+ { 0x0000, 0x0000, 0x0000 }, /* R235 */
+ { 0x0000, 0x0000, 0x0000 }, /* R236 */
+ { 0x0000, 0x0000, 0x0000 }, /* R237 */
+ { 0x0000, 0x0000, 0x0000 }, /* R238 */
+ { 0x0000, 0x0000, 0x0000 }, /* R239 */
+ { 0x0000, 0x0000, 0x0000 }, /* R240 */
+ { 0x0000, 0x0000, 0x0000 }, /* R241 */
+ { 0x0000, 0x0000, 0x0000 }, /* R242 */
+ { 0x0000, 0x0000, 0x0000 }, /* R243 */
+ { 0x0000, 0x0000, 0x0000 }, /* R244 */
+ { 0x0000, 0x0000, 0x0000 }, /* R245 */
+ { 0x0000, 0x0000, 0x0000 }, /* R246 */
+ { 0x0000, 0x0000, 0x0000 }, /* R247 */
+ { 0x0000, 0x0000, 0x0000 }, /* R248 */
+ { 0x0000, 0x0000, 0x0000 }, /* R249 */
+ { 0x0000, 0x0000, 0x0000 }, /* R250 */
+ { 0x0000, 0x0000, 0x0000 }, /* R251 */
+ { 0x0000, 0x0000, 0x0000 }, /* R252 */
+ { 0x0000, 0x0000, 0x0000 }, /* R253 */
+ { 0x0000, 0x0000, 0x0000 }, /* R254 */
+ { 0x0000, 0x0000, 0x0000 }, /* R255 */
+ { 0x000F, 0x0000, 0x0000 }, /* R256 - Chip Revision */
+ { 0x0074, 0x0074, 0x0000 }, /* R257 - Control Interface */
+ { 0x0000, 0x0000, 0x0000 }, /* R258 */
+ { 0x0000, 0x0000, 0x0000 }, /* R259 */
+ { 0x0000, 0x0000, 0x0000 }, /* R260 */
+ { 0x0000, 0x0000, 0x0000 }, /* R261 */
+ { 0x0000, 0x0000, 0x0000 }, /* R262 */
+ { 0x0000, 0x0000, 0x0000 }, /* R263 */
+ { 0x0000, 0x0000, 0x0000 }, /* R264 */
+ { 0x0000, 0x0000, 0x0000 }, /* R265 */
+ { 0x0000, 0x0000, 0x0000 }, /* R266 */
+ { 0x0000, 0x0000, 0x0000 }, /* R267 */
+ { 0x0000, 0x0000, 0x0000 }, /* R268 */
+ { 0x0000, 0x0000, 0x0000 }, /* R269 */
+ { 0x0000, 0x0000, 0x0000 }, /* R270 */
+ { 0x0000, 0x0000, 0x0000 }, /* R271 */
+ { 0x807F, 0x837F, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */
+ { 0x017F, 0x0000, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
+ { 0x0000, 0x0000, 0x0000 }, /* R274 */
+ { 0x0000, 0x0000, 0x0000 }, /* R275 */
+ { 0x0000, 0x0000, 0x0000 }, /* R276 */
+ { 0x0000, 0x0000, 0x0000 }, /* R277 */
+ { 0x0000, 0x0000, 0x0000 }, /* R278 */
+ { 0x0000, 0x0000, 0x0000 }, /* R279 */
+ { 0x0000, 0x0000, 0x0000 }, /* R280 */
+ { 0x0000, 0x0000, 0x0000 }, /* R281 */
+ { 0x0000, 0x0000, 0x0000 }, /* R282 */
+ { 0x0000, 0x0000, 0x0000 }, /* R283 */
+ { 0x0000, 0x0000, 0x0000 }, /* R284 */
+ { 0x0000, 0x0000, 0x0000 }, /* R285 */
+ { 0x0000, 0x0000, 0x0000 }, /* R286 */
+ { 0x0000, 0x0000, 0x0000 }, /* R287 */
+ { 0x0000, 0x0000, 0x0000 }, /* R288 */
+ { 0x0000, 0x0000, 0x0000 }, /* R289 */
+ { 0x0000, 0x0000, 0x0000 }, /* R290 */
+ { 0x0000, 0x0000, 0x0000 }, /* R291 */
+ { 0x0000, 0x0000, 0x0000 }, /* R292 */
+ { 0x0000, 0x0000, 0x0000 }, /* R293 */
+ { 0x0000, 0x0000, 0x0000 }, /* R294 */
+ { 0x0000, 0x0000, 0x0000 }, /* R295 */
+ { 0x0000, 0x0000, 0x0000 }, /* R296 */
+ { 0x0000, 0x0000, 0x0000 }, /* R297 */
+ { 0x0000, 0x0000, 0x0000 }, /* R298 */
+ { 0x0000, 0x0000, 0x0000 }, /* R299 */
+ { 0x0000, 0x0000, 0x0000 }, /* R300 */
+ { 0x0000, 0x0000, 0x0000 }, /* R301 */
+ { 0x0000, 0x0000, 0x0000 }, /* R302 */
+ { 0x0000, 0x0000, 0x0000 }, /* R303 */
+ { 0x0000, 0x0000, 0x0000 }, /* R304 */
+ { 0x0000, 0x0000, 0x0000 }, /* R305 */
+ { 0x0000, 0x0000, 0x0000 }, /* R306 */
+ { 0x0000, 0x0000, 0x0000 }, /* R307 */
+ { 0x0000, 0x0000, 0x0000 }, /* R308 */
+ { 0x0000, 0x0000, 0x0000 }, /* R309 */
+ { 0x0000, 0x0000, 0x0000 }, /* R310 */
+ { 0x0000, 0x0000, 0x0000 }, /* R311 */
+ { 0x0000, 0x0000, 0x0000 }, /* R312 */
+ { 0x0000, 0x0000, 0x0000 }, /* R313 */
+ { 0x0000, 0x0000, 0x0000 }, /* R314 */
+ { 0x0000, 0x0000, 0x0000 }, /* R315 */
+ { 0x0000, 0x0000, 0x0000 }, /* R316 */
+ { 0x0000, 0x0000, 0x0000 }, /* R317 */
+ { 0x0000, 0x0000, 0x0000 }, /* R318 */
+ { 0x0000, 0x0000, 0x0000 }, /* R319 */
+ { 0x0000, 0x0000, 0x0000 }, /* R320 */
+ { 0x0000, 0x0000, 0x0000 }, /* R321 */
+ { 0x0000, 0x0000, 0x0000 }, /* R322 */
+ { 0x0000, 0x0000, 0x0000 }, /* R323 */
+ { 0x0000, 0x0000, 0x0000 }, /* R324 */
+ { 0x0000, 0x0000, 0x0000 }, /* R325 */
+ { 0x0000, 0x0000, 0x0000 }, /* R326 */
+ { 0x0000, 0x0000, 0x0000 }, /* R327 */
+ { 0x0000, 0x0000, 0x0000 }, /* R328 */
+ { 0x0000, 0x0000, 0x0000 }, /* R329 */
+ { 0x0000, 0x0000, 0x0000 }, /* R330 */
+ { 0x0000, 0x0000, 0x0000 }, /* R331 */
+ { 0x0000, 0x0000, 0x0000 }, /* R332 */
+ { 0x0000, 0x0000, 0x0000 }, /* R333 */
+ { 0x0000, 0x0000, 0x0000 }, /* R334 */
+ { 0x0000, 0x0000, 0x0000 }, /* R335 */
+ { 0x0000, 0x0000, 0x0000 }, /* R336 */
+ { 0x0000, 0x0000, 0x0000 }, /* R337 */
+ { 0x0000, 0x0000, 0x0000 }, /* R338 */
+ { 0x0000, 0x0000, 0x0000 }, /* R339 */
+ { 0x0000, 0x0000, 0x0000 }, /* R340 */
+ { 0x0000, 0x0000, 0x0000 }, /* R341 */
+ { 0x0000, 0x0000, 0x0000 }, /* R342 */
+ { 0x0000, 0x0000, 0x0000 }, /* R343 */
+ { 0x0000, 0x0000, 0x0000 }, /* R344 */
+ { 0x0000, 0x0000, 0x0000 }, /* R345 */
+ { 0x0000, 0x0000, 0x0000 }, /* R346 */
+ { 0x0000, 0x0000, 0x0000 }, /* R347 */
+ { 0x0000, 0x0000, 0x0000 }, /* R348 */
+ { 0x0000, 0x0000, 0x0000 }, /* R349 */
+ { 0x0000, 0x0000, 0x0000 }, /* R350 */
+ { 0x0000, 0x0000, 0x0000 }, /* R351 */
+ { 0x0000, 0x0000, 0x0000 }, /* R352 */
+ { 0x0000, 0x0000, 0x0000 }, /* R353 */
+ { 0x0000, 0x0000, 0x0000 }, /* R354 */
+ { 0x0000, 0x0000, 0x0000 }, /* R355 */
+ { 0x0000, 0x0000, 0x0000 }, /* R356 */
+ { 0x0000, 0x0000, 0x0000 }, /* R357 */
+ { 0x0000, 0x0000, 0x0000 }, /* R358 */
+ { 0x0000, 0x0000, 0x0000 }, /* R359 */
+ { 0x0000, 0x0000, 0x0000 }, /* R360 */
+ { 0x0000, 0x0000, 0x0000 }, /* R361 */
+ { 0x0000, 0x0000, 0x0000 }, /* R362 */
+ { 0x0000, 0x0000, 0x0000 }, /* R363 */
+ { 0x0000, 0x0000, 0x0000 }, /* R364 */
+ { 0x0000, 0x0000, 0x0000 }, /* R365 */
+ { 0x0000, 0x0000, 0x0000 }, /* R366 */
+ { 0x0000, 0x0000, 0x0000 }, /* R367 */
+ { 0x0000, 0x0000, 0x0000 }, /* R368 */
+ { 0x0000, 0x0000, 0x0000 }, /* R369 */
+ { 0x0000, 0x0000, 0x0000 }, /* R370 */
+ { 0x0000, 0x0000, 0x0000 }, /* R371 */
+ { 0x0000, 0x0000, 0x0000 }, /* R372 */
+ { 0x0000, 0x0000, 0x0000 }, /* R373 */
+ { 0x0000, 0x0000, 0x0000 }, /* R374 */
+ { 0x0000, 0x0000, 0x0000 }, /* R375 */
+ { 0x0000, 0x0000, 0x0000 }, /* R376 */
+ { 0x0000, 0x0000, 0x0000 }, /* R377 */
+ { 0x0000, 0x0000, 0x0000 }, /* R378 */
+ { 0x0000, 0x0000, 0x0000 }, /* R379 */
+ { 0x0000, 0x0000, 0x0000 }, /* R380 */
+ { 0x0000, 0x0000, 0x0000 }, /* R381 */
+ { 0x0000, 0x0000, 0x0000 }, /* R382 */
+ { 0x0000, 0x0000, 0x0000 }, /* R383 */
+ { 0x0000, 0x0000, 0x0000 }, /* R384 */
+ { 0x0000, 0x0000, 0x0000 }, /* R385 */
+ { 0x0000, 0x0000, 0x0000 }, /* R386 */
+ { 0x0000, 0x0000, 0x0000 }, /* R387 */
+ { 0x0000, 0x0000, 0x0000 }, /* R388 */
+ { 0x0000, 0x0000, 0x0000 }, /* R389 */
+ { 0x0000, 0x0000, 0x0000 }, /* R390 */
+ { 0x0000, 0x0000, 0x0000 }, /* R391 */
+ { 0x0000, 0x0000, 0x0000 }, /* R392 */
+ { 0x0000, 0x0000, 0x0000 }, /* R393 */
+ { 0x0000, 0x0000, 0x0000 }, /* R394 */
+ { 0x0000, 0x0000, 0x0000 }, /* R395 */
+ { 0x0000, 0x0000, 0x0000 }, /* R396 */
+ { 0x0000, 0x0000, 0x0000 }, /* R397 */
+ { 0x0000, 0x0000, 0x0000 }, /* R398 */
+ { 0x0000, 0x0000, 0x0000 }, /* R399 */
+ { 0x0000, 0x0000, 0x0000 }, /* R400 */
+ { 0x0000, 0x0000, 0x0000 }, /* R401 */
+ { 0x0000, 0x0000, 0x0000 }, /* R402 */
+ { 0x0000, 0x0000, 0x0000 }, /* R403 */
+ { 0x0000, 0x0000, 0x0000 }, /* R404 */
+ { 0x0000, 0x0000, 0x0000 }, /* R405 */
+ { 0x0000, 0x0000, 0x0000 }, /* R406 */
+ { 0x0000, 0x0000, 0x0000 }, /* R407 */
+ { 0x0000, 0x0000, 0x0000 }, /* R408 */
+ { 0x0000, 0x0000, 0x0000 }, /* R409 */
+ { 0x0000, 0x0000, 0x0000 }, /* R410 */
+ { 0x0000, 0x0000, 0x0000 }, /* R411 */
+ { 0x0000, 0x0000, 0x0000 }, /* R412 */
+ { 0x0000, 0x0000, 0x0000 }, /* R413 */
+ { 0x0000, 0x0000, 0x0000 }, /* R414 */
+ { 0x0000, 0x0000, 0x0000 }, /* R415 */
+ { 0x0000, 0x0000, 0x0000 }, /* R416 */
+ { 0x0000, 0x0000, 0x0000 }, /* R417 */
+ { 0x0000, 0x0000, 0x0000 }, /* R418 */
+ { 0x0000, 0x0000, 0x0000 }, /* R419 */
+ { 0x0000, 0x0000, 0x0000 }, /* R420 */
+ { 0x0000, 0x0000, 0x0000 }, /* R421 */
+ { 0x0000, 0x0000, 0x0000 }, /* R422 */
+ { 0x0000, 0x0000, 0x0000 }, /* R423 */
+ { 0x0000, 0x0000, 0x0000 }, /* R424 */
+ { 0x0000, 0x0000, 0x0000 }, /* R425 */
+ { 0x0000, 0x0000, 0x0000 }, /* R426 */
+ { 0x0000, 0x0000, 0x0000 }, /* R427 */
+ { 0x0000, 0x0000, 0x0000 }, /* R428 */
+ { 0x0000, 0x0000, 0x0000 }, /* R429 */
+ { 0x0000, 0x0000, 0x0000 }, /* R430 */
+ { 0x0000, 0x0000, 0x0000 }, /* R431 */
+ { 0x0000, 0x0000, 0x0000 }, /* R432 */
+ { 0x0000, 0x0000, 0x0000 }, /* R433 */
+ { 0x0000, 0x0000, 0x0000 }, /* R434 */
+ { 0x0000, 0x0000, 0x0000 }, /* R435 */
+ { 0x0000, 0x0000, 0x0000 }, /* R436 */
+ { 0x0000, 0x0000, 0x0000 }, /* R437 */
+ { 0x0000, 0x0000, 0x0000 }, /* R438 */
+ { 0x0000, 0x0000, 0x0000 }, /* R439 */
+ { 0x0000, 0x0000, 0x0000 }, /* R440 */
+ { 0x0000, 0x0000, 0x0000 }, /* R441 */
+ { 0x0000, 0x0000, 0x0000 }, /* R442 */
+ { 0x0000, 0x0000, 0x0000 }, /* R443 */
+ { 0x0000, 0x0000, 0x0000 }, /* R444 */
+ { 0x0000, 0x0000, 0x0000 }, /* R445 */
+ { 0x0000, 0x0000, 0x0000 }, /* R446 */
+ { 0x0000, 0x0000, 0x0000 }, /* R447 */
+ { 0x0000, 0x0000, 0x0000 }, /* R448 */
+ { 0x0000, 0x0000, 0x0000 }, /* R449 */
+ { 0x0000, 0x0000, 0x0000 }, /* R450 */
+ { 0x0000, 0x0000, 0x0000 }, /* R451 */
+ { 0x0000, 0x0000, 0x0000 }, /* R452 */
+ { 0x0000, 0x0000, 0x0000 }, /* R453 */
+ { 0x0000, 0x0000, 0x0000 }, /* R454 */
+ { 0x0000, 0x0000, 0x0000 }, /* R455 */
+ { 0x0000, 0x0000, 0x0000 }, /* R456 */
+ { 0x0000, 0x0000, 0x0000 }, /* R457 */
+ { 0x0000, 0x0000, 0x0000 }, /* R458 */
+ { 0x0000, 0x0000, 0x0000 }, /* R459 */
+ { 0x0000, 0x0000, 0x0000 }, /* R460 */
+ { 0x0000, 0x0000, 0x0000 }, /* R461 */
+ { 0x0000, 0x0000, 0x0000 }, /* R462 */
+ { 0x0000, 0x0000, 0x0000 }, /* R463 */
+ { 0x0000, 0x0000, 0x0000 }, /* R464 */
+ { 0x0000, 0x0000, 0x0000 }, /* R465 */
+ { 0x0000, 0x0000, 0x0000 }, /* R466 */
+ { 0x0000, 0x0000, 0x0000 }, /* R467 */
+ { 0x0000, 0x0000, 0x0000 }, /* R468 */
+ { 0x0000, 0x0000, 0x0000 }, /* R469 */
+ { 0x0000, 0x0000, 0x0000 }, /* R470 */
+ { 0x0000, 0x0000, 0x0000 }, /* R471 */
+ { 0x0000, 0x0000, 0x0000 }, /* R472 */
+ { 0x0000, 0x0000, 0x0000 }, /* R473 */
+ { 0x0000, 0x0000, 0x0000 }, /* R474 */
+ { 0x0000, 0x0000, 0x0000 }, /* R475 */
+ { 0x0000, 0x0000, 0x0000 }, /* R476 */
+ { 0x0000, 0x0000, 0x0000 }, /* R477 */
+ { 0x0000, 0x0000, 0x0000 }, /* R478 */
+ { 0x0000, 0x0000, 0x0000 }, /* R479 */
+ { 0x0000, 0x0000, 0x0000 }, /* R480 */
+ { 0x0000, 0x0000, 0x0000 }, /* R481 */
+ { 0x0000, 0x0000, 0x0000 }, /* R482 */
+ { 0x0000, 0x0000, 0x0000 }, /* R483 */
+ { 0x0000, 0x0000, 0x0000 }, /* R484 */
+ { 0x0000, 0x0000, 0x0000 }, /* R485 */
+ { 0x0000, 0x0000, 0x0000 }, /* R486 */
+ { 0x0000, 0x0000, 0x0000 }, /* R487 */
+ { 0x0000, 0x0000, 0x0000 }, /* R488 */
+ { 0x0000, 0x0000, 0x0000 }, /* R489 */
+ { 0x0000, 0x0000, 0x0000 }, /* R490 */
+ { 0x0000, 0x0000, 0x0000 }, /* R491 */
+ { 0x0000, 0x0000, 0x0000 }, /* R492 */
+ { 0x0000, 0x0000, 0x0000 }, /* R493 */
+ { 0x0000, 0x0000, 0x0000 }, /* R494 */
+ { 0x0000, 0x0000, 0x0000 }, /* R495 */
+ { 0x0000, 0x0000, 0x0000 }, /* R496 */
+ { 0x0000, 0x0000, 0x0000 }, /* R497 */
+ { 0x0000, 0x0000, 0x0000 }, /* R498 */
+ { 0x0000, 0x0000, 0x0000 }, /* R499 */
+ { 0x0000, 0x0000, 0x0000 }, /* R500 */
+ { 0x0000, 0x0000, 0x0000 }, /* R501 */
+ { 0x0000, 0x0000, 0x0000 }, /* R502 */
+ { 0x0000, 0x0000, 0x0000 }, /* R503 */
+ { 0x0000, 0x0000, 0x0000 }, /* R504 */
+ { 0x0000, 0x0000, 0x0000 }, /* R505 */
+ { 0x0000, 0x0000, 0x0000 }, /* R506 */
+ { 0x0000, 0x0000, 0x0000 }, /* R507 */
+ { 0x0000, 0x0000, 0x0000 }, /* R508 */
+ { 0x0000, 0x0000, 0x0000 }, /* R509 */
+ { 0x0000, 0x0000, 0x0000 }, /* R510 */
+ { 0x0000, 0x0000, 0x0000 }, /* R511 */
+ { 0x001F, 0x001F, 0x0000 }, /* R512 - AIF1 Clocking (1) */
+ { 0x003F, 0x003F, 0x0000 }, /* R513 - AIF1 Clocking (2) */
+ { 0x0000, 0x0000, 0x0000 }, /* R514 */
+ { 0x0000, 0x0000, 0x0000 }, /* R515 */
+ { 0x001F, 0x001F, 0x0000 }, /* R516 - AIF2 Clocking (1) */
+ { 0x003F, 0x003F, 0x0000 }, /* R517 - AIF2 Clocking (2) */
+ { 0x0000, 0x0000, 0x0000 }, /* R518 */
+ { 0x0000, 0x0000, 0x0000 }, /* R519 */
+ { 0x001F, 0x001F, 0x0000 }, /* R520 - Clocking (1) */
+ { 0x0777, 0x0777, 0x0000 }, /* R521 - Clocking (2) */
+ { 0x0000, 0x0000, 0x0000 }, /* R522 */
+ { 0x0000, 0x0000, 0x0000 }, /* R523 */
+ { 0x0000, 0x0000, 0x0000 }, /* R524 */
+ { 0x0000, 0x0000, 0x0000 }, /* R525 */
+ { 0x0000, 0x0000, 0x0000 }, /* R526 */
+ { 0x0000, 0x0000, 0x0000 }, /* R527 */
+ { 0x00FF, 0x00FF, 0x0000 }, /* R528 - AIF1 Rate */
+ { 0x00FF, 0x00FF, 0x0000 }, /* R529 - AIF2 Rate */
+ { 0x000F, 0x0000, 0x0000 }, /* R530 - Rate Status */
+ { 0x0000, 0x0000, 0x0000 }, /* R531 */
+ { 0x0000, 0x0000, 0x0000 }, /* R532 */
+ { 0x0000, 0x0000, 0x0000 }, /* R533 */
+ { 0x0000, 0x0000, 0x0000 }, /* R534 */
+ { 0x0000, 0x0000, 0x0000 }, /* R535 */
+ { 0x0000, 0x0000, 0x0000 }, /* R536 */
+ { 0x0000, 0x0000, 0x0000 }, /* R537 */
+ { 0x0000, 0x0000, 0x0000 }, /* R538 */
+ { 0x0000, 0x0000, 0x0000 }, /* R539 */
+ { 0x0000, 0x0000, 0x0000 }, /* R540 */
+ { 0x0000, 0x0000, 0x0000 }, /* R541 */
+ { 0x0000, 0x0000, 0x0000 }, /* R542 */
+ { 0x0000, 0x0000, 0x0000 }, /* R543 */
+ { 0x0007, 0x0007, 0x0000 }, /* R544 - FLL1 Control (1) */
+ { 0x3F77, 0x3F77, 0x0000 }, /* R545 - FLL1 Control (2) */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R546 - FLL1 Control (3) */
+ { 0x7FEF, 0x7FEF, 0x0000 }, /* R547 - FLL1 Control (4) */
+ { 0x1FDB, 0x1FDB, 0x0000 }, /* R548 - FLL1 Control (5) */
+ { 0x0000, 0x0000, 0x0000 }, /* R549 */
+ { 0x0000, 0x0000, 0x0000 }, /* R550 */
+ { 0x0000, 0x0000, 0x0000 }, /* R551 */
+ { 0x0000, 0x0000, 0x0000 }, /* R552 */
+ { 0x0000, 0x0000, 0x0000 }, /* R553 */
+ { 0x0000, 0x0000, 0x0000 }, /* R554 */
+ { 0x0000, 0x0000, 0x0000 }, /* R555 */
+ { 0x0000, 0x0000, 0x0000 }, /* R556 */
+ { 0x0000, 0x0000, 0x0000 }, /* R557 */
+ { 0x0000, 0x0000, 0x0000 }, /* R558 */
+ { 0x0000, 0x0000, 0x0000 }, /* R559 */
+ { 0x0000, 0x0000, 0x0000 }, /* R560 */
+ { 0x0000, 0x0000, 0x0000 }, /* R561 */
+ { 0x0000, 0x0000, 0x0000 }, /* R562 */
+ { 0x0000, 0x0000, 0x0000 }, /* R563 */
+ { 0x0000, 0x0000, 0x0000 }, /* R564 */
+ { 0x0000, 0x0000, 0x0000 }, /* R565 */
+ { 0x0000, 0x0000, 0x0000 }, /* R566 */
+ { 0x0000, 0x0000, 0x0000 }, /* R567 */
+ { 0x0000, 0x0000, 0x0000 }, /* R568 */
+ { 0x0000, 0x0000, 0x0000 }, /* R569 */
+ { 0x0000, 0x0000, 0x0000 }, /* R570 */
+ { 0x0000, 0x0000, 0x0000 }, /* R571 */
+ { 0x0000, 0x0000, 0x0000 }, /* R572 */
+ { 0x0000, 0x0000, 0x0000 }, /* R573 */
+ { 0x0000, 0x0000, 0x0000 }, /* R574 */
+ { 0x0000, 0x0000, 0x0000 }, /* R575 */
+ { 0x0007, 0x0007, 0x0000 }, /* R576 - FLL2 Control (1) */
+ { 0x3F77, 0x3F77, 0x0000 }, /* R577 - FLL2 Control (2) */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R578 - FLL2 Control (3) */
+ { 0x7FEF, 0x7FEF, 0x0000 }, /* R579 - FLL2 Control (4) */
+ { 0x1FDB, 0x1FDB, 0x0000 }, /* R580 - FLL2 Control (5) */
+ { 0x0000, 0x0000, 0x0000 }, /* R581 */
+ { 0x0000, 0x0000, 0x0000 }, /* R582 */
+ { 0x0000, 0x0000, 0x0000 }, /* R583 */
+ { 0x0000, 0x0000, 0x0000 }, /* R584 */
+ { 0x0000, 0x0000, 0x0000 }, /* R585 */
+ { 0x0000, 0x0000, 0x0000 }, /* R586 */
+ { 0x0000, 0x0000, 0x0000 }, /* R587 */
+ { 0x0000, 0x0000, 0x0000 }, /* R588 */
+ { 0x0000, 0x0000, 0x0000 }, /* R589 */
+ { 0x0000, 0x0000, 0x0000 }, /* R590 */
+ { 0x0000, 0x0000, 0x0000 }, /* R591 */
+ { 0x0000, 0x0000, 0x0000 }, /* R592 */
+ { 0x0000, 0x0000, 0x0000 }, /* R593 */
+ { 0x0000, 0x0000, 0x0000 }, /* R594 */
+ { 0x0000, 0x0000, 0x0000 }, /* R595 */
+ { 0x0000, 0x0000, 0x0000 }, /* R596 */
+ { 0x0000, 0x0000, 0x0000 }, /* R597 */
+ { 0x0000, 0x0000, 0x0000 }, /* R598 */
+ { 0x0000, 0x0000, 0x0000 }, /* R599 */
+ { 0x0000, 0x0000, 0x0000 }, /* R600 */
+ { 0x0000, 0x0000, 0x0000 }, /* R601 */
+ { 0x0000, 0x0000, 0x0000 }, /* R602 */
+ { 0x0000, 0x0000, 0x0000 }, /* R603 */
+ { 0x0000, 0x0000, 0x0000 }, /* R604 */
+ { 0x0000, 0x0000, 0x0000 }, /* R605 */
+ { 0x0000, 0x0000, 0x0000 }, /* R606 */
+ { 0x0000, 0x0000, 0x0000 }, /* R607 */
+ { 0x0000, 0x0000, 0x0000 }, /* R608 */
+ { 0x0000, 0x0000, 0x0000 }, /* R609 */
+ { 0x0000, 0x0000, 0x0000 }, /* R610 */
+ { 0x0000, 0x0000, 0x0000 }, /* R611 */
+ { 0x0000, 0x0000, 0x0000 }, /* R612 */
+ { 0x0000, 0x0000, 0x0000 }, /* R613 */
+ { 0x0000, 0x0000, 0x0000 }, /* R614 */
+ { 0x0000, 0x0000, 0x0000 }, /* R615 */
+ { 0x0000, 0x0000, 0x0000 }, /* R616 */
+ { 0x0000, 0x0000, 0x0000 }, /* R617 */
+ { 0x0000, 0x0000, 0x0000 }, /* R618 */
+ { 0x0000, 0x0000, 0x0000 }, /* R619 */
+ { 0x0000, 0x0000, 0x0000 }, /* R620 */
+ { 0x0000, 0x0000, 0x0000 }, /* R621 */
+ { 0x0000, 0x0000, 0x0000 }, /* R622 */
+ { 0x0000, 0x0000, 0x0000 }, /* R623 */
+ { 0x0000, 0x0000, 0x0000 }, /* R624 */
+ { 0x0000, 0x0000, 0x0000 }, /* R625 */
+ { 0x0000, 0x0000, 0x0000 }, /* R626 */
+ { 0x0000, 0x0000, 0x0000 }, /* R627 */
+ { 0x0000, 0x0000, 0x0000 }, /* R628 */
+ { 0x0000, 0x0000, 0x0000 }, /* R629 */
+ { 0x0000, 0x0000, 0x0000 }, /* R630 */
+ { 0x0000, 0x0000, 0x0000 }, /* R631 */
+ { 0x0000, 0x0000, 0x0000 }, /* R632 */
+ { 0x0000, 0x0000, 0x0000 }, /* R633 */
+ { 0x0000, 0x0000, 0x0000 }, /* R634 */
+ { 0x0000, 0x0000, 0x0000 }, /* R635 */
+ { 0x0000, 0x0000, 0x0000 }, /* R636 */
+ { 0x0000, 0x0000, 0x0000 }, /* R637 */
+ { 0x0000, 0x0000, 0x0000 }, /* R638 */
+ { 0x0000, 0x0000, 0x0000 }, /* R639 */
+ { 0x0000, 0x0000, 0x0000 }, /* R640 */
+ { 0x0000, 0x0000, 0x0000 }, /* R641 */
+ { 0x0000, 0x0000, 0x0000 }, /* R642 */
+ { 0x0000, 0x0000, 0x0000 }, /* R643 */
+ { 0x0000, 0x0000, 0x0000 }, /* R644 */
+ { 0x0000, 0x0000, 0x0000 }, /* R645 */
+ { 0x0000, 0x0000, 0x0000 }, /* R646 */
+ { 0x0000, 0x0000, 0x0000 }, /* R647 */
+ { 0x0000, 0x0000, 0x0000 }, /* R648 */
+ { 0x0000, 0x0000, 0x0000 }, /* R649 */
+ { 0x0000, 0x0000, 0x0000 }, /* R650 */
+ { 0x0000, 0x0000, 0x0000 }, /* R651 */
+ { 0x0000, 0x0000, 0x0000 }, /* R652 */
+ { 0x0000, 0x0000, 0x0000 }, /* R653 */
+ { 0x0000, 0x0000, 0x0000 }, /* R654 */
+ { 0x0000, 0x0000, 0x0000 }, /* R655 */
+ { 0x0000, 0x0000, 0x0000 }, /* R656 */
+ { 0x0000, 0x0000, 0x0000 }, /* R657 */
+ { 0x0000, 0x0000, 0x0000 }, /* R658 */
+ { 0x0000, 0x0000, 0x0000 }, /* R659 */
+ { 0x0000, 0x0000, 0x0000 }, /* R660 */
+ { 0x0000, 0x0000, 0x0000 }, /* R661 */
+ { 0x0000, 0x0000, 0x0000 }, /* R662 */
+ { 0x0000, 0x0000, 0x0000 }, /* R663 */
+ { 0x0000, 0x0000, 0x0000 }, /* R664 */
+ { 0x0000, 0x0000, 0x0000 }, /* R665 */
+ { 0x0000, 0x0000, 0x0000 }, /* R666 */
+ { 0x0000, 0x0000, 0x0000 }, /* R667 */
+ { 0x0000, 0x0000, 0x0000 }, /* R668 */
+ { 0x0000, 0x0000, 0x0000 }, /* R669 */
+ { 0x0000, 0x0000, 0x0000 }, /* R670 */
+ { 0x0000, 0x0000, 0x0000 }, /* R671 */
+ { 0x0000, 0x0000, 0x0000 }, /* R672 */
+ { 0x0000, 0x0000, 0x0000 }, /* R673 */
+ { 0x0000, 0x0000, 0x0000 }, /* R674 */
+ { 0x0000, 0x0000, 0x0000 }, /* R675 */
+ { 0x0000, 0x0000, 0x0000 }, /* R676 */
+ { 0x0000, 0x0000, 0x0000 }, /* R677 */
+ { 0x0000, 0x0000, 0x0000 }, /* R678 */
+ { 0x0000, 0x0000, 0x0000 }, /* R679 */
+ { 0x0000, 0x0000, 0x0000 }, /* R680 */
+ { 0x0000, 0x0000, 0x0000 }, /* R681 */
+ { 0x0000, 0x0000, 0x0000 }, /* R682 */
+ { 0x0000, 0x0000, 0x0000 }, /* R683 */
+ { 0x0000, 0x0000, 0x0000 }, /* R684 */
+ { 0x0000, 0x0000, 0x0000 }, /* R685 */
+ { 0x0000, 0x0000, 0x0000 }, /* R686 */
+ { 0x0000, 0x0000, 0x0000 }, /* R687 */
+ { 0x0000, 0x0000, 0x0000 }, /* R688 */
+ { 0x0000, 0x0000, 0x0000 }, /* R689 */
+ { 0x0000, 0x0000, 0x0000 }, /* R690 */
+ { 0x0000, 0x0000, 0x0000 }, /* R691 */
+ { 0x0000, 0x0000, 0x0000 }, /* R692 */
+ { 0x0000, 0x0000, 0x0000 }, /* R693 */
+ { 0x0000, 0x0000, 0x0000 }, /* R694 */
+ { 0x0000, 0x0000, 0x0000 }, /* R695 */
+ { 0x0000, 0x0000, 0x0000 }, /* R696 */
+ { 0x0000, 0x0000, 0x0000 }, /* R697 */
+ { 0x0000, 0x0000, 0x0000 }, /* R698 */
+ { 0x0000, 0x0000, 0x0000 }, /* R699 */
+ { 0x0000, 0x0000, 0x0000 }, /* R700 */
+ { 0x0000, 0x0000, 0x0000 }, /* R701 */
+ { 0x0000, 0x0000, 0x0000 }, /* R702 */
+ { 0x0000, 0x0000, 0x0000 }, /* R703 */
+ { 0x0000, 0x0000, 0x0000 }, /* R704 */
+ { 0x0000, 0x0000, 0x0000 }, /* R705 */
+ { 0x0000, 0x0000, 0x0000 }, /* R706 */
+ { 0x0000, 0x0000, 0x0000 }, /* R707 */
+ { 0x0000, 0x0000, 0x0000 }, /* R708 */
+ { 0x0000, 0x0000, 0x0000 }, /* R709 */
+ { 0x0000, 0x0000, 0x0000 }, /* R710 */
+ { 0x0000, 0x0000, 0x0000 }, /* R711 */
+ { 0x0000, 0x0000, 0x0000 }, /* R712 */
+ { 0x0000, 0x0000, 0x0000 }, /* R713 */
+ { 0x0000, 0x0000, 0x0000 }, /* R714 */
+ { 0x0000, 0x0000, 0x0000 }, /* R715 */
+ { 0x0000, 0x0000, 0x0000 }, /* R716 */
+ { 0x0000, 0x0000, 0x0000 }, /* R717 */
+ { 0x0000, 0x0000, 0x0000 }, /* R718 */
+ { 0x0000, 0x0000, 0x0000 }, /* R719 */
+ { 0x0000, 0x0000, 0x0000 }, /* R720 */
+ { 0x0000, 0x0000, 0x0000 }, /* R721 */
+ { 0x0000, 0x0000, 0x0000 }, /* R722 */
+ { 0x0000, 0x0000, 0x0000 }, /* R723 */
+ { 0x0000, 0x0000, 0x0000 }, /* R724 */
+ { 0x0000, 0x0000, 0x0000 }, /* R725 */
+ { 0x0000, 0x0000, 0x0000 }, /* R726 */
+ { 0x0000, 0x0000, 0x0000 }, /* R727 */
+ { 0x0000, 0x0000, 0x0000 }, /* R728 */
+ { 0x0000, 0x0000, 0x0000 }, /* R729 */
+ { 0x0000, 0x0000, 0x0000 }, /* R730 */
+ { 0x0000, 0x0000, 0x0000 }, /* R731 */
+ { 0x0000, 0x0000, 0x0000 }, /* R732 */
+ { 0x0000, 0x0000, 0x0000 }, /* R733 */
+ { 0x0000, 0x0000, 0x0000 }, /* R734 */
+ { 0x0000, 0x0000, 0x0000 }, /* R735 */
+ { 0x0000, 0x0000, 0x0000 }, /* R736 */
+ { 0x0000, 0x0000, 0x0000 }, /* R737 */
+ { 0x0000, 0x0000, 0x0000 }, /* R738 */
+ { 0x0000, 0x0000, 0x0000 }, /* R739 */
+ { 0x0000, 0x0000, 0x0000 }, /* R740 */
+ { 0x0000, 0x0000, 0x0000 }, /* R741 */
+ { 0x0000, 0x0000, 0x0000 }, /* R742 */
+ { 0x0000, 0x0000, 0x0000 }, /* R743 */
+ { 0x0000, 0x0000, 0x0000 }, /* R744 */
+ { 0x0000, 0x0000, 0x0000 }, /* R745 */
+ { 0x0000, 0x0000, 0x0000 }, /* R746 */
+ { 0x0000, 0x0000, 0x0000 }, /* R747 */
+ { 0x0000, 0x0000, 0x0000 }, /* R748 */
+ { 0x0000, 0x0000, 0x0000 }, /* R749 */
+ { 0x0000, 0x0000, 0x0000 }, /* R750 */
+ { 0x0000, 0x0000, 0x0000 }, /* R751 */
+ { 0x0000, 0x0000, 0x0000 }, /* R752 */
+ { 0x0000, 0x0000, 0x0000 }, /* R753 */
+ { 0x0000, 0x0000, 0x0000 }, /* R754 */
+ { 0x0000, 0x0000, 0x0000 }, /* R755 */
+ { 0x0000, 0x0000, 0x0000 }, /* R756 */
+ { 0x0000, 0x0000, 0x0000 }, /* R757 */
+ { 0x0000, 0x0000, 0x0000 }, /* R758 */
+ { 0x0000, 0x0000, 0x0000 }, /* R759 */
+ { 0x0000, 0x0000, 0x0000 }, /* R760 */
+ { 0x0000, 0x0000, 0x0000 }, /* R761 */
+ { 0x0000, 0x0000, 0x0000 }, /* R762 */
+ { 0x0000, 0x0000, 0x0000 }, /* R763 */
+ { 0x0000, 0x0000, 0x0000 }, /* R764 */
+ { 0x0000, 0x0000, 0x0000 }, /* R765 */
+ { 0x0000, 0x0000, 0x0000 }, /* R766 */
+ { 0x0000, 0x0000, 0x0000 }, /* R767 */
+ { 0xE1F8, 0xE1F8, 0x0000 }, /* R768 - AIF1 Control (1) */
+ { 0xCD1F, 0xCD1F, 0x0000 }, /* R769 - AIF1 Control (2) */
+ { 0xF000, 0xF000, 0x0000 }, /* R770 - AIF1 Master/Slave */
+ { 0x01F0, 0x01F0, 0x0000 }, /* R771 - AIF1 BCLK */
+ { 0x0FFF, 0x0FFF, 0x0000 }, /* R772 - AIF1ADC LRCLK */
+ { 0x0FFF, 0x0FFF, 0x0000 }, /* R773 - AIF1DAC LRCLK */
+ { 0x0003, 0x0003, 0x0000 }, /* R774 - AIF1DAC Data */
+ { 0x0003, 0x0003, 0x0000 }, /* R775 - AIF1ADC Data */
+ { 0x0000, 0x0000, 0x0000 }, /* R776 */
+ { 0x0000, 0x0000, 0x0000 }, /* R777 */
+ { 0x0000, 0x0000, 0x0000 }, /* R778 */
+ { 0x0000, 0x0000, 0x0000 }, /* R779 */
+ { 0x0000, 0x0000, 0x0000 }, /* R780 */
+ { 0x0000, 0x0000, 0x0000 }, /* R781 */
+ { 0x0000, 0x0000, 0x0000 }, /* R782 */
+ { 0x0000, 0x0000, 0x0000 }, /* R783 */
+ { 0xF1F8, 0xF1F8, 0x0000 }, /* R784 - AIF2 Control (1) */
+ { 0xFD1F, 0xFD1F, 0x0000 }, /* R785 - AIF2 Control (2) */
+ { 0xF000, 0xF000, 0x0000 }, /* R786 - AIF2 Master/Slave */
+ { 0x01F0, 0x01F0, 0x0000 }, /* R787 - AIF2 BCLK */
+ { 0x0FFF, 0x0FFF, 0x0000 }, /* R788 - AIF2ADC LRCLK */
+ { 0x0FFF, 0x0FFF, 0x0000 }, /* R789 - AIF2DAC LRCLK */
+ { 0x0003, 0x0003, 0x0000 }, /* R790 - AIF2DAC Data */
+ { 0x0003, 0x0003, 0x0000 }, /* R791 - AIF2ADC Data */
+ { 0x0000, 0x0000, 0x0000 }, /* R792 */
+ { 0x0000, 0x0000, 0x0000 }, /* R793 */
+ { 0x0000, 0x0000, 0x0000 }, /* R794 */
+ { 0x0000, 0x0000, 0x0000 }, /* R795 */
+ { 0x0000, 0x0000, 0x0000 }, /* R796 */
+ { 0x0000, 0x0000, 0x0000 }, /* R797 */
+ { 0x0000, 0x0000, 0x0000 }, /* R798 */
+ { 0x0000, 0x0000, 0x0000 }, /* R799 */
+ { 0x0000, 0x0000, 0x0000 }, /* R800 */
+ { 0x0000, 0x0000, 0x0000 }, /* R801 */
+ { 0x0000, 0x0000, 0x0000 }, /* R802 */
+ { 0x0000, 0x0000, 0x0000 }, /* R803 */
+ { 0x0000, 0x0000, 0x0000 }, /* R804 */
+ { 0x0000, 0x0000, 0x0000 }, /* R805 */
+ { 0x0000, 0x0000, 0x0000 }, /* R806 */
+ { 0x0000, 0x0000, 0x0000 }, /* R807 */
+ { 0x0000, 0x0000, 0x0000 }, /* R808 */
+ { 0x0000, 0x0000, 0x0000 }, /* R809 */
+ { 0x0000, 0x0000, 0x0000 }, /* R810 */
+ { 0x0000, 0x0000, 0x0000 }, /* R811 */
+ { 0x0000, 0x0000, 0x0000 }, /* R812 */
+ { 0x0000, 0x0000, 0x0000 }, /* R813 */
+ { 0x0000, 0x0000, 0x0000 }, /* R814 */
+ { 0x0000, 0x0000, 0x0000 }, /* R815 */
+ { 0x0000, 0x0000, 0x0000 }, /* R816 */
+ { 0x0000, 0x0000, 0x0000 }, /* R817 */
+ { 0x0000, 0x0000, 0x0000 }, /* R818 */
+ { 0x0000, 0x0000, 0x0000 }, /* R819 */
+ { 0x0000, 0x0000, 0x0000 }, /* R820 */
+ { 0x0000, 0x0000, 0x0000 }, /* R821 */
+ { 0x0000, 0x0000, 0x0000 }, /* R822 */
+ { 0x0000, 0x0000, 0x0000 }, /* R823 */
+ { 0x0000, 0x0000, 0x0000 }, /* R824 */
+ { 0x0000, 0x0000, 0x0000 }, /* R825 */
+ { 0x0000, 0x0000, 0x0000 }, /* R826 */
+ { 0x0000, 0x0000, 0x0000 }, /* R827 */
+ { 0x0000, 0x0000, 0x0000 }, /* R828 */
+ { 0x0000, 0x0000, 0x0000 }, /* R829 */
+ { 0x0000, 0x0000, 0x0000 }, /* R830 */
+ { 0x0000, 0x0000, 0x0000 }, /* R831 */
+ { 0x0000, 0x0000, 0x0000 }, /* R832 */
+ { 0x0000, 0x0000, 0x0000 }, /* R833 */
+ { 0x0000, 0x0000, 0x0000 }, /* R834 */
+ { 0x0000, 0x0000, 0x0000 }, /* R835 */
+ { 0x0000, 0x0000, 0x0000 }, /* R836 */
+ { 0x0000, 0x0000, 0x0000 }, /* R837 */
+ { 0x0000, 0x0000, 0x0000 }, /* R838 */
+ { 0x0000, 0x0000, 0x0000 }, /* R839 */
+ { 0x0000, 0x0000, 0x0000 }, /* R840 */
+ { 0x0000, 0x0000, 0x0000 }, /* R841 */
+ { 0x0000, 0x0000, 0x0000 }, /* R842 */
+ { 0x0000, 0x0000, 0x0000 }, /* R843 */
+ { 0x0000, 0x0000, 0x0000 }, /* R844 */
+ { 0x0000, 0x0000, 0x0000 }, /* R845 */
+ { 0x0000, 0x0000, 0x0000 }, /* R846 */
+ { 0x0000, 0x0000, 0x0000 }, /* R847 */
+ { 0x0000, 0x0000, 0x0000 }, /* R848 */
+ { 0x0000, 0x0000, 0x0000 }, /* R849 */
+ { 0x0000, 0x0000, 0x0000 }, /* R850 */
+ { 0x0000, 0x0000, 0x0000 }, /* R851 */
+ { 0x0000, 0x0000, 0x0000 }, /* R852 */
+ { 0x0000, 0x0000, 0x0000 }, /* R853 */
+ { 0x0000, 0x0000, 0x0000 }, /* R854 */
+ { 0x0000, 0x0000, 0x0000 }, /* R855 */
+ { 0x0000, 0x0000, 0x0000 }, /* R856 */
+ { 0x0000, 0x0000, 0x0000 }, /* R857 */
+ { 0x0000, 0x0000, 0x0000 }, /* R858 */
+ { 0x0000, 0x0000, 0x0000 }, /* R859 */
+ { 0x0000, 0x0000, 0x0000 }, /* R860 */
+ { 0x0000, 0x0000, 0x0000 }, /* R861 */
+ { 0x0000, 0x0000, 0x0000 }, /* R862 */
+ { 0x0000, 0x0000, 0x0000 }, /* R863 */
+ { 0x0000, 0x0000, 0x0000 }, /* R864 */
+ { 0x0000, 0x0000, 0x0000 }, /* R865 */
+ { 0x0000, 0x0000, 0x0000 }, /* R866 */
+ { 0x0000, 0x0000, 0x0000 }, /* R867 */
+ { 0x0000, 0x0000, 0x0000 }, /* R868 */
+ { 0x0000, 0x0000, 0x0000 }, /* R869 */
+ { 0x0000, 0x0000, 0x0000 }, /* R870 */
+ { 0x0000, 0x0000, 0x0000 }, /* R871 */
+ { 0x0000, 0x0000, 0x0000 }, /* R872 */
+ { 0x0000, 0x0000, 0x0000 }, /* R873 */
+ { 0x0000, 0x0000, 0x0000 }, /* R874 */
+ { 0x0000, 0x0000, 0x0000 }, /* R875 */
+ { 0x0000, 0x0000, 0x0000 }, /* R876 */
+ { 0x0000, 0x0000, 0x0000 }, /* R877 */
+ { 0x0000, 0x0000, 0x0000 }, /* R878 */
+ { 0x0000, 0x0000, 0x0000 }, /* R879 */
+ { 0x0000, 0x0000, 0x0000 }, /* R880 */
+ { 0x0000, 0x0000, 0x0000 }, /* R881 */
+ { 0x0000, 0x0000, 0x0000 }, /* R882 */
+ { 0x0000, 0x0000, 0x0000 }, /* R883 */
+ { 0x0000, 0x0000, 0x0000 }, /* R884 */
+ { 0x0000, 0x0000, 0x0000 }, /* R885 */
+ { 0x0000, 0x0000, 0x0000 }, /* R886 */
+ { 0x0000, 0x0000, 0x0000 }, /* R887 */
+ { 0x0000, 0x0000, 0x0000 }, /* R888 */
+ { 0x0000, 0x0000, 0x0000 }, /* R889 */
+ { 0x0000, 0x0000, 0x0000 }, /* R890 */
+ { 0x0000, 0x0000, 0x0000 }, /* R891 */
+ { 0x0000, 0x0000, 0x0000 }, /* R892 */
+ { 0x0000, 0x0000, 0x0000 }, /* R893 */
+ { 0x0000, 0x0000, 0x0000 }, /* R894 */
+ { 0x0000, 0x0000, 0x0000 }, /* R895 */
+ { 0x0000, 0x0000, 0x0000 }, /* R896 */
+ { 0x0000, 0x0000, 0x0000 }, /* R897 */
+ { 0x0000, 0x0000, 0x0000 }, /* R898 */
+ { 0x0000, 0x0000, 0x0000 }, /* R899 */
+ { 0x0000, 0x0000, 0x0000 }, /* R900 */
+ { 0x0000, 0x0000, 0x0000 }, /* R901 */
+ { 0x0000, 0x0000, 0x0000 }, /* R902 */
+ { 0x0000, 0x0000, 0x0000 }, /* R903 */
+ { 0x0000, 0x0000, 0x0000 }, /* R904 */
+ { 0x0000, 0x0000, 0x0000 }, /* R905 */
+ { 0x0000, 0x0000, 0x0000 }, /* R906 */
+ { 0x0000, 0x0000, 0x0000 }, /* R907 */
+ { 0x0000, 0x0000, 0x0000 }, /* R908 */
+ { 0x0000, 0x0000, 0x0000 }, /* R909 */
+ { 0x0000, 0x0000, 0x0000 }, /* R910 */
+ { 0x0000, 0x0000, 0x0000 }, /* R911 */
+ { 0x0000, 0x0000, 0x0000 }, /* R912 */
+ { 0x0000, 0x0000, 0x0000 }, /* R913 */
+ { 0x0000, 0x0000, 0x0000 }, /* R914 */
+ { 0x0000, 0x0000, 0x0000 }, /* R915 */
+ { 0x0000, 0x0000, 0x0000 }, /* R916 */
+ { 0x0000, 0x0000, 0x0000 }, /* R917 */
+ { 0x0000, 0x0000, 0x0000 }, /* R918 */
+ { 0x0000, 0x0000, 0x0000 }, /* R919 */
+ { 0x0000, 0x0000, 0x0000 }, /* R920 */
+ { 0x0000, 0x0000, 0x0000 }, /* R921 */
+ { 0x0000, 0x0000, 0x0000 }, /* R922 */
+ { 0x0000, 0x0000, 0x0000 }, /* R923 */
+ { 0x0000, 0x0000, 0x0000 }, /* R924 */
+ { 0x0000, 0x0000, 0x0000 }, /* R925 */
+ { 0x0000, 0x0000, 0x0000 }, /* R926 */
+ { 0x0000, 0x0000, 0x0000 }, /* R927 */
+ { 0x0000, 0x0000, 0x0000 }, /* R928 */
+ { 0x0000, 0x0000, 0x0000 }, /* R929 */
+ { 0x0000, 0x0000, 0x0000 }, /* R930 */
+ { 0x0000, 0x0000, 0x0000 }, /* R931 */
+ { 0x0000, 0x0000, 0x0000 }, /* R932 */
+ { 0x0000, 0x0000, 0x0000 }, /* R933 */
+ { 0x0000, 0x0000, 0x0000 }, /* R934 */
+ { 0x0000, 0x0000, 0x0000 }, /* R935 */
+ { 0x0000, 0x0000, 0x0000 }, /* R936 */
+ { 0x0000, 0x0000, 0x0000 }, /* R937 */
+ { 0x0000, 0x0000, 0x0000 }, /* R938 */
+ { 0x0000, 0x0000, 0x0000 }, /* R939 */
+ { 0x0000, 0x0000, 0x0000 }, /* R940 */
+ { 0x0000, 0x0000, 0x0000 }, /* R941 */
+ { 0x0000, 0x0000, 0x0000 }, /* R942 */
+ { 0x0000, 0x0000, 0x0000 }, /* R943 */
+ { 0x0000, 0x0000, 0x0000 }, /* R944 */
+ { 0x0000, 0x0000, 0x0000 }, /* R945 */
+ { 0x0000, 0x0000, 0x0000 }, /* R946 */
+ { 0x0000, 0x0000, 0x0000 }, /* R947 */
+ { 0x0000, 0x0000, 0x0000 }, /* R948 */
+ { 0x0000, 0x0000, 0x0000 }, /* R949 */
+ { 0x0000, 0x0000, 0x0000 }, /* R950 */
+ { 0x0000, 0x0000, 0x0000 }, /* R951 */
+ { 0x0000, 0x0000, 0x0000 }, /* R952 */
+ { 0x0000, 0x0000, 0x0000 }, /* R953 */
+ { 0x0000, 0x0000, 0x0000 }, /* R954 */
+ { 0x0000, 0x0000, 0x0000 }, /* R955 */
+ { 0x0000, 0x0000, 0x0000 }, /* R956 */
+ { 0x0000, 0x0000, 0x0000 }, /* R957 */
+ { 0x0000, 0x0000, 0x0000 }, /* R958 */
+ { 0x0000, 0x0000, 0x0000 }, /* R959 */
+ { 0x0000, 0x0000, 0x0000 }, /* R960 */
+ { 0x0000, 0x0000, 0x0000 }, /* R961 */
+ { 0x0000, 0x0000, 0x0000 }, /* R962 */
+ { 0x0000, 0x0000, 0x0000 }, /* R963 */
+ { 0x0000, 0x0000, 0x0000 }, /* R964 */
+ { 0x0000, 0x0000, 0x0000 }, /* R965 */
+ { 0x0000, 0x0000, 0x0000 }, /* R966 */
+ { 0x0000, 0x0000, 0x0000 }, /* R967 */
+ { 0x0000, 0x0000, 0x0000 }, /* R968 */
+ { 0x0000, 0x0000, 0x0000 }, /* R969 */
+ { 0x0000, 0x0000, 0x0000 }, /* R970 */
+ { 0x0000, 0x0000, 0x0000 }, /* R971 */
+ { 0x0000, 0x0000, 0x0000 }, /* R972 */
+ { 0x0000, 0x0000, 0x0000 }, /* R973 */
+ { 0x0000, 0x0000, 0x0000 }, /* R974 */
+ { 0x0000, 0x0000, 0x0000 }, /* R975 */
+ { 0x0000, 0x0000, 0x0000 }, /* R976 */
+ { 0x0000, 0x0000, 0x0000 }, /* R977 */
+ { 0x0000, 0x0000, 0x0000 }, /* R978 */
+ { 0x0000, 0x0000, 0x0000 }, /* R979 */
+ { 0x0000, 0x0000, 0x0000 }, /* R980 */
+ { 0x0000, 0x0000, 0x0000 }, /* R981 */
+ { 0x0000, 0x0000, 0x0000 }, /* R982 */
+ { 0x0000, 0x0000, 0x0000 }, /* R983 */
+ { 0x0000, 0x0000, 0x0000 }, /* R984 */
+ { 0x0000, 0x0000, 0x0000 }, /* R985 */
+ { 0x0000, 0x0000, 0x0000 }, /* R986 */
+ { 0x0000, 0x0000, 0x0000 }, /* R987 */
+ { 0x0000, 0x0000, 0x0000 }, /* R988 */
+ { 0x0000, 0x0000, 0x0000 }, /* R989 */
+ { 0x0000, 0x0000, 0x0000 }, /* R990 */
+ { 0x0000, 0x0000, 0x0000 }, /* R991 */
+ { 0x0000, 0x0000, 0x0000 }, /* R992 */
+ { 0x0000, 0x0000, 0x0000 }, /* R993 */
+ { 0x0000, 0x0000, 0x0000 }, /* R994 */
+ { 0x0000, 0x0000, 0x0000 }, /* R995 */
+ { 0x0000, 0x0000, 0x0000 }, /* R996 */
+ { 0x0000, 0x0000, 0x0000 }, /* R997 */
+ { 0x0000, 0x0000, 0x0000 }, /* R998 */
+ { 0x0000, 0x0000, 0x0000 }, /* R999 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1000 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1001 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1002 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1003 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1004 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1005 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1006 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1007 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1008 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1009 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1010 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1011 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1012 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1013 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1014 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1015 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1016 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1017 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1018 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1019 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1020 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1021 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1022 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1023 */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R1024 - AIF1 ADC1 Left Volume */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R1025 - AIF1 ADC1 Right Volume */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R1026 - AIF1 DAC1 Left Volume */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R1027 - AIF1 DAC1 Right Volume */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R1028 - AIF1 ADC2 Left Volume */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R1029 - AIF1 ADC2 Right Volume */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R1030 - AIF1 DAC2 Left Volume */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R1031 - AIF1 DAC2 Right Volume */
+ { 0x0000, 0x0000, 0x0000 }, /* R1032 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1033 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1034 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1035 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1036 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1037 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1038 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1039 */
+ { 0xF800, 0xF800, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */
+ { 0x7800, 0x7800, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */
+ { 0x0000, 0x0000, 0x0000 }, /* R1042 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1043 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1044 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1045 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1046 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1047 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1048 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1049 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1050 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1051 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1052 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1053 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1054 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1055 */
+ { 0x02B6, 0x02B6, 0x0000 }, /* R1056 - AIF1 DAC1 Filters (1) */
+ { 0x3F00, 0x3F00, 0x0000 }, /* R1057 - AIF1 DAC1 Filters (2) */
+ { 0x02B6, 0x02B6, 0x0000 }, /* R1058 - AIF1 DAC2 Filters (1) */
+ { 0x3F00, 0x3F00, 0x0000 }, /* R1059 - AIF1 DAC2 Filters (2) */
+ { 0x0000, 0x0000, 0x0000 }, /* R1060 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1061 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1062 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1063 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1064 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1065 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1066 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1067 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1068 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1069 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1070 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1071 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1072 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1073 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1074 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1075 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1076 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1077 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1078 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1079 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1080 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1081 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1082 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1083 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1084 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1085 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1086 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1087 */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1088 - AIF1 DRC1 (1) */
+ { 0x1FFF, 0x1FFF, 0x0000 }, /* R1089 - AIF1 DRC1 (2) */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */
+ { 0x07FF, 0x07FF, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */
+ { 0x03FF, 0x03FF, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */
+ { 0x0000, 0x0000, 0x0000 }, /* R1093 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1094 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1095 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1096 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1097 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1098 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1099 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1100 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1101 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1102 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1103 */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1104 - AIF1 DRC2 (1) */
+ { 0x1FFF, 0x1FFF, 0x0000 }, /* R1105 - AIF1 DRC2 (2) */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */
+ { 0x07FF, 0x07FF, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */
+ { 0x03FF, 0x03FF, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */
+ { 0x0000, 0x0000, 0x0000 }, /* R1109 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1110 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1111 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1112 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1113 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1114 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1115 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1116 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1117 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1118 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1119 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1120 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1121 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1122 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1123 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1124 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1125 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1126 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1127 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1128 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1129 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1130 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1131 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1132 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1133 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1134 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1135 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1136 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1137 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1138 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1139 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1140 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1141 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1142 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1143 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1144 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1145 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1146 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1147 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1148 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1149 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1150 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1151 */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
+ { 0xFFC0, 0xFFC0, 0x0000 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
+ { 0x0000, 0x0000, 0x0000 }, /* R1172 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1173 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1174 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1175 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1176 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1177 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1178 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1179 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1180 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1181 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1182 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1183 */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
+ { 0xFFC0, 0xFFC0, 0x0000 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
+ { 0x0000, 0x0000, 0x0000 }, /* R1204 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1205 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1206 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1207 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1208 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1209 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1210 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1211 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1212 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1213 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1214 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1215 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1216 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1217 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1218 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1219 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1220 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1221 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1222 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1223 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1224 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1225 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1226 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1227 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1228 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1229 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1230 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1231 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1232 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1233 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1234 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1235 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1236 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1237 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1238 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1239 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1240 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1241 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1242 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1243 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1244 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1245 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1246 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1247 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1248 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1249 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1250 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1251 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1252 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1253 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1254 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1255 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1256 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1257 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1258 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1259 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1260 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1261 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1262 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1263 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1264 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1265 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1266 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1267 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1268 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1269 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1270 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1271 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1272 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1273 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1274 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1275 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1276 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1277 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1278 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1279 */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R1280 - AIF2 ADC Left Volume */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R1281 - AIF2 ADC Right Volume */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R1282 - AIF2 DAC Left Volume */
+ { 0x00FF, 0x01FF, 0x0000 }, /* R1283 - AIF2 DAC Right Volume */
+ { 0x0000, 0x0000, 0x0000 }, /* R1284 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1285 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1286 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1287 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1288 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1289 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1290 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1291 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1292 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1293 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1294 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1295 */
+ { 0xF800, 0xF800, 0x0000 }, /* R1296 - AIF2 ADC Filters */
+ { 0x0000, 0x0000, 0x0000 }, /* R1297 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1298 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1299 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1300 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1301 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1302 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1303 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1304 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1305 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1306 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1307 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1308 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1309 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1310 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1311 */
+ { 0x02B6, 0x02B6, 0x0000 }, /* R1312 - AIF2 DAC Filters (1) */
+ { 0x3F00, 0x3F00, 0x0000 }, /* R1313 - AIF2 DAC Filters (2) */
+ { 0x0000, 0x0000, 0x0000 }, /* R1314 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1315 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1316 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1317 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1318 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1319 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1320 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1321 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1322 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1323 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1324 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1325 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1326 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1327 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1328 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1329 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1330 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1331 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1332 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1333 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1334 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1335 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1336 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1337 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1338 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1339 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1340 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1341 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1342 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1343 */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1344 - AIF2 DRC (1) */
+ { 0x1FFF, 0x1FFF, 0x0000 }, /* R1345 - AIF2 DRC (2) */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1346 - AIF2 DRC (3) */
+ { 0x07FF, 0x07FF, 0x0000 }, /* R1347 - AIF2 DRC (4) */
+ { 0x03FF, 0x03FF, 0x0000 }, /* R1348 - AIF2 DRC (5) */
+ { 0x0000, 0x0000, 0x0000 }, /* R1349 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1350 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1351 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1352 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1353 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1354 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1355 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1356 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1357 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1358 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1359 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1360 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1361 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1362 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1363 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1364 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1365 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1366 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1367 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1368 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1369 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1370 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1371 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1372 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1373 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1374 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1375 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1376 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1377 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1378 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1379 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1380 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1381 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1382 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1383 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1384 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1385 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1386 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1387 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1388 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1389 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1390 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1391 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1392 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1393 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1394 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1395 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1396 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1397 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1398 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1399 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1400 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1401 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1402 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1403 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1404 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1405 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1406 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1407 */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1408 - AIF2 EQ Gains (1) */
+ { 0xFFC0, 0xFFC0, 0x0000 }, /* R1409 - AIF2 EQ Gains (2) */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1410 - AIF2 EQ Band 1 A */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1411 - AIF2 EQ Band 1 B */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1412 - AIF2 EQ Band 1 PG */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1413 - AIF2 EQ Band 2 A */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1414 - AIF2 EQ Band 2 B */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1415 - AIF2 EQ Band 2 C */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1416 - AIF2 EQ Band 2 PG */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1417 - AIF2 EQ Band 3 A */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1418 - AIF2 EQ Band 3 B */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1419 - AIF2 EQ Band 3 C */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1420 - AIF2 EQ Band 3 PG */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1421 - AIF2 EQ Band 4 A */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1422 - AIF2 EQ Band 4 B */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1423 - AIF2 EQ Band 4 C */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1424 - AIF2 EQ Band 4 PG */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1425 - AIF2 EQ Band 5 A */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1426 - AIF2 EQ Band 5 B */
+ { 0xFFFF, 0xFFFF, 0x0000 }, /* R1427 - AIF2 EQ Band 5 PG */
+ { 0x0000, 0x0000, 0x0000 }, /* R1428 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1429 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1430 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1431 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1432 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1433 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1434 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1435 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1436 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1437 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1438 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1439 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1440 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1441 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1442 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1443 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1444 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1445 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1446 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1447 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1448 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1449 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1450 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1451 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1452 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1453 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1454 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1455 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1456 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1457 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1458 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1459 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1460 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1461 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1462 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1463 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1464 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1465 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1466 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1467 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1468 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1469 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1470 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1471 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1472 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1473 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1474 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1475 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1476 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1477 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1478 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1479 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1480 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1481 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1482 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1483 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1484 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1485 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1486 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1487 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1488 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1489 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1490 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1491 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1492 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1493 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1494 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1495 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1496 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1497 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1498 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1499 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1500 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1501 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1502 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1503 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1504 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1505 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1506 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1507 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1508 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1509 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1510 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1511 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1512 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1513 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1514 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1515 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1516 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1517 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1518 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1519 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1520 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1521 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1522 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1523 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1524 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1525 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1526 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1527 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1528 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1529 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1530 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1531 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1532 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1533 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1534 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1535 */
+ { 0x01EF, 0x01EF, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */
+ { 0x0037, 0x0037, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */
+ { 0x0037, 0x0037, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */
+ { 0x01EF, 0x01EF, 0x0000 }, /* R1539 - DAC2 Mixer Volumes */
+ { 0x0037, 0x0037, 0x0000 }, /* R1540 - DAC2 Left Mixer Routing */
+ { 0x0037, 0x0037, 0x0000 }, /* R1541 - DAC2 Right Mixer Routing */
+ { 0x0003, 0x0003, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
+ { 0x0003, 0x0003, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
+ { 0x0003, 0x0003, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
+ { 0x0003, 0x0003, 0x0000 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
+ { 0x0000, 0x0000, 0x0000 }, /* R1546 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1547 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1548 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1549 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1550 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1551 */
+ { 0x02FF, 0x03FF, 0x0000 }, /* R1552 - DAC1 Left Volume */
+ { 0x02FF, 0x03FF, 0x0000 }, /* R1553 - DAC1 Right Volume */
+ { 0x02FF, 0x03FF, 0x0000 }, /* R1554 - DAC2 Left Volume */
+ { 0x02FF, 0x03FF, 0x0000 }, /* R1555 - DAC2 Right Volume */
+ { 0x0003, 0x0003, 0x0000 }, /* R1556 - DAC Softmute */
+ { 0x0000, 0x0000, 0x0000 }, /* R1557 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1558 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1559 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1560 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1561 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1562 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1563 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1564 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1565 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1566 */
+ { 0x0000, 0x0000, 0x0000 }, /* R1567 */
+ { 0x0003, 0x0003, 0x0000 }, /* R1568 - Oversampling */
+ { 0x03C3, 0x03C3, 0x0000 }, /* R1569 - Sidetone */
};
-static int wm8994_read(unsigned short reg,unsigned short *value)
+static int wm8994_readable(unsigned int reg)
{
- unsigned short regs=((reg>>8)&0x00FF)|((reg<<8)&0xFF00),values;
+ if (reg >= ARRAY_SIZE(access_masks))
+ return 0;
+ return access_masks[reg].readable != 0;
+}
- if (reg_recv_data(wm8994_client,®s,&values,400000) > 0)
- {
- *value=((values>>8)& 0x00FF)|((values<<8)&0xFF00);
+static int wm8994_volatile(unsigned int reg)
+{
+ if (reg >= WM8994_REG_CACHE_SIZE)
+ return 1;
+
+ switch (reg) {
+ case WM8994_SOFTWARE_RESET:
+ case WM8994_CHIP_REVISION:
+ case WM8994_DC_SERVO_1:
+ case WM8994_DC_SERVO_READBACK:
+ case WM8994_RATE_STATUS:
+ case WM8994_LDO_1:
+ case WM8994_LDO_2:
+ return 1;
+ default:
return 0;
}
-
- printk("%s---line->%d:Codec read error! reg = 0x%x , value = 0x%x\n",__FUNCTION__,__LINE__,reg,*value);
-
- return -EIO;
}
-
-static int wm8994_write(unsigned short reg,unsigned short value)
+static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
+ unsigned int value)
{
- unsigned short regs=((reg>>8)&0x00FF)|((reg<<8)&0xFF00),values=((value>>8)&0x00FF)|((value<<8)&0xFF00);
-
- if (reg_send_data(wm8994_client,®s,&values,400000) > 0)
- return 0;
+ struct wm8994_priv *wm8994 = codec->private_data;
+#ifdef WM8994_PROC
+ if(debug_write_read != 0)
+ DBG("%s:0x%04x = 0x%04x",__FUNCTION__,reg,value);
+#endif
+ BUG_ON(reg > WM8994_MAX_REGISTER);
- printk("%s---line->%d:Codec write error! reg = 0x%x , value = 0x%x\n",__FUNCTION__,__LINE__,reg,value);
+ if (!wm8994_volatile(reg))
+ wm8994->reg_cache[reg] = value;
- return -EIO;
+ return wm8994_reg_write(codec->control_data, reg, value);
}
-#define wm8994_reset() wm8994_write(WM8994_RESET, 0)
-void AP_to_headset(void)
+static unsigned int wm8994_read(struct snd_soc_codec *codec,
+ unsigned int reg)
{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_AP_to_headset)return;
- wm8994_current_mode=wm8994_AP_to_headset;
- wm8994_reset();
- msleep(WM8994_DELAY);
-
- wm8994_write(0x01, 0x0003);
- msleep(WM8994_DELAY);
-
- wm8994_write(0x200, 0x0001);
- wm8994_write(0x220, 0x0000);
- wm8994_write(0x221, 0x0700);
- wm8994_write(0x222, 0x3126);
- wm8994_write(0x223, 0x0100);
-
- wm8994_write(0x210, 0x0083); // SR=48KHz
- wm8994_write(0x220, 0x0004);
- msleep(WM8994_DELAY);
- wm8994_write(0x220, 0x0005);
- wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1) 0x0011
- wm8994_write(0x300, 0x4010); // i2s 16 bits
-
- wm8994_write(0x04, 0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1/ q
- wm8994_write(0x05, 0x0303);
- wm8994_write(0x2D, 0x0100);
- wm8994_write(0x2E, 0x0100);
-
- wm8994_write(0x4C, 0x9F25);
- msleep(5);
- wm8994_write(0x01, 0x0303);
- msleep(50);
- wm8994_write(0x60, 0x0022);
- wm8994_write(0x60, 0x00FF);
-
- wm8994_write(0x208, 0x000A);
- wm8994_write(0x420, 0x0000);
- wm8994_write(0x601, 0x0001);
- wm8994_write(0x602, 0x0001);
-
- wm8994_write(0x610, 0x01A0); //DAC1 Left Volume bit0~7
- wm8994_write(0x611, 0x01A0); //DAC1 Right Volume bit0~7
- wm8994_write(0x03, 0x3030);
- wm8994_write(0x22, 0x0000);
- wm8994_write(0x23, 0x0100);
- wm8994_write(0x36, 0x0003);
- wm8994_write(0x1C, 0x017F); //HPOUT1L Volume
- wm8994_write(0x1D, 0x017F); //HPOUT1R Volume
-
-#ifdef CONFIG_SND_CODEC_SOC_MASTER
- wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
- wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
- wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
- wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
-#endif
-}
+ u16 *reg_cache = codec->reg_cache;
+ int read_val;
+ BUG_ON(reg > WM8994_MAX_REGISTER);
-void AP_to_speakers(void)
-{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_AP_to_speakers)return;
- wm8994_current_mode=wm8994_AP_to_speakers;
- wm8994_reset();
- msleep(WM8994_DELAY);
-
- wm8994_write(0x01, 0x0003);
- msleep(WM8994_DELAY);
-
- wm8994_write(0x200, 0x0001);
- wm8994_write(0x220, 0x0000);
- wm8994_write(0x221, 0x0700);
- wm8994_write(0x222, 0x3126);
- wm8994_write(0x223, 0x0100);
-
- wm8994_write(0x210, 0x0083); // SR=48KHz
- wm8994_write(0x220, 0x0004);
- msleep(WM8994_DELAY);
- wm8994_write(0x220, 0x0005);
- wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1) 0x0011
- wm8994_write(0x300, 0xC010); // i2s 16 bits
-
- wm8994_write(0x01, 0x3003);
- wm8994_write(0x04, 0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
- wm8994_write(0x05, 0x0303);
- wm8994_write(0x2D, 0x0100);
- wm8994_write(0x2E, 0x0100);
- wm8994_write(0x4C, 0x9F25);
- wm8994_write(0x60, 0x00EE);
- wm8994_write(0x208, 0x000A);
- wm8994_write(0x420, 0x0000);
-
- wm8994_write(0x601, 0x0001);
- wm8994_write(0x602, 0x0001);
-
- wm8994_write(0x610, 0x01c0); //DAC1 Left Volume bit0~7
- wm8994_write(0x611, 0x01c0); //DAC1 Right Volume bit0~7
- wm8994_write(0x03, 0x0330);
- wm8994_write(0x22, 0x0000);
- wm8994_write(0x23, 0x0100);
- wm8994_write(0x36, 0x0003);
- wm8994_write(0x26, 0x017F); //Speaker Left Output Volume
- wm8994_write(0x27, 0x017F); //Speaker Right Output Volume
-
-#ifdef CONFIG_SND_CODEC_SOC_MASTER
- wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
- wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
- wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
- wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
-#endif
+ if (wm8994_volatile(reg))
+ {
+ read_val = wm8994_reg_read(codec->control_data, reg);
+ #ifdef WM8994_PROC
+ if(debug_write_read != 0)
+ DBG("%s:0x%04x = 0x%04x",__FUNCTION__,reg,read_val);
+ #endif
+ return read_val;
+ }
+ else
+ {
+ #ifdef WM8994_PROC
+ if(debug_write_read != 0)
+ DBG("%s:0x%04x = 0x%04x",__FUNCTION__,reg,reg_cache[reg]);
+ #endif
+ return reg_cache[reg];
+ }
}
-void recorder_and_AP_to_headset(void)
+static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_recorder_and_AP_to_headset)return;
- wm8994_current_mode=wm8994_recorder_and_AP_to_headset;
- wm8994_reset();
- msleep(WM8994_DELAY);
-
- wm8994_write(0x01, 0x0003);
- msleep(WM8994_DELAY);
-
-//MCLK=12MHz
-//48KHz, BCLK=48KHz*64=3.072MHz, Fout=12.288MHz
-
- wm8994_write(0x200, 0x0001); // AIF1CLK_ENA=1
- wm8994_write(0x220, 0x0000);
- wm8994_write(0x221, 0x0700);
- wm8994_write(0x222, 0x3126);
- wm8994_write(0x223, 0x0100);
- wm8994_write(0x210, 0x0083); // SR=48KHz
- wm8994_write(0x220, 0x0004);
- msleep(WM8994_DELAY);
- wm8994_write(0x220, 0x0005); // FLL1_FRACN_ENA=1, FLL1_ENA=1
- wm8994_write(0x200, 0x0011); // AIF1CLK_SRC=10, AIF1CLK_ENA=1
-
- vol=CONFIG_WM8994_RECORDER_VOL;
- if(vol>60)vol=60;
- if(vol<-16)vol=-16;
- if(vol<30){
- wm8994_write(0x1A, 320+(vol+16)*10/15); //mic vol
- }else{
- wm8994_write(0x2A, 0x0030);
- wm8994_write(0x1A, 320+(vol-14)*10/15); //mic vol
- }
- vol=CONFIG_WM8994_HEADSET_NORMAL_VOL;
- if(vol>6)vol=6;
- if(vol<-57)vol=-57;
- wm8994_write(0x1C, 320+vol+57); //-57dB~6dB
- wm8994_write(0x1D, 320+vol+57); //-57dB~6dB
-
- wm8994_write(0x28, 0x0003); // IN1RP_TO_IN1R=1, IN1RN_TO_IN1R=1
- wm8994_write(0x200, 0x0011); // AIF1CLK_ENA=1
- wm8994_write(0x208, 0x000A); // DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
- wm8994_write(0x300, 0xC050); // AIF1ADCL_SRC=1, AIF1ADCR_SRC=1, AIF1_WL=10, AIF1_FMT=10
- wm8994_write(0x606, 0x0002); // ADC1L_TO_AIF1ADC1L=1
- wm8994_write(0x607, 0x0002); // ADC1R_TO_AIF1ADC1R=1
- wm8994_write(0x620, 0x0000);
- wm8994_write(0x700, 0xA101);
-
- wm8994_write(0x402, 0x01FF); // AIF1ADC1L_VOL [7:0]
- wm8994_write(0x403, 0x01FF); // AIF1ADC1R_VOL [7:0]
- wm8994_write(0x2D, 0x0100); // DAC1L_TO_HPOUT1L=1
- wm8994_write(0x2E, 0x0100); // DAC1R_TO_HPOUT1R=1
-
- wm8994_write(0x4C, 0x9F25);
- mdelay(5);
- wm8994_write(0x01, 0x0313);
- mdelay(50);
- wm8994_write(0x60, 0x0022);
- wm8994_write(0x60, 0x00EE);
-
- wm8994_write(0x601, 0x0001); // AIF1DAC1L_TO_DAC1L=1
- wm8994_write(0x602, 0x0001); // AIF1DAC1R_TO_DAC1R=1
- wm8994_write(0x610, 0x01A0); // DAC1_VU=1, DAC1L_VOL=1100_0000
- wm8994_write(0x611, 0x01A0); // DAC1_VU=1, DAC1R_VOL=1100_0000
- wm8994_write(0x02, 0x6110); // TSHUT_ENA=1, TSHUT_OPDIS=1, MIXINR_ENA=1,IN1R_ENA=1
- wm8994_write(0x03, 0x3030);
- wm8994_write(0x04, 0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
- wm8994_write(0x05, 0x0303); // AIF1DAC1L_ENA=1, AIF1DAC1R_ENA=1, DAC1L_ENA=1, DAC1R_ENA=1
- wm8994_write(0x420, 0x0000);
- wm8994_write(0x700, 0xA101);
-#ifdef CONFIG_SND_CODEC_SOC_MASTER
- wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
- wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
- wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
- wm8994_write(0x302, 0x3000); // AIF1_MSTR=1
- msleep(50);
- wm8994_write(0x302, 0x7000); // AIF1_MSTR=1
- msleep(50);
-#endif
-}
+ struct wm8994_priv *wm8994 = codec->private_data;
+ int rate;
+ int reg1 = 0;
+ int offset;
-void recorder_and_AP_to_speakers(void)
-{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_recorder_and_AP_to_speakers)return;
- wm8994_current_mode=wm8994_recorder_and_AP_to_speakers;
- wm8994_reset();
- msleep(WM8994_DELAY);
-
- wm8994_write(0x01, 0x0003);
- msleep(WM8994_DELAY);
-
-//MCLK=12MHz
-//48KHz, BCLK=48KHz*64=3.072MHz, Fout=12.288MHz
-
- wm8994_write(0x200, 0x0001); // AIF1CLK_ENA=1
- wm8994_write(0x220, 0x0000);
- wm8994_write(0x221, 0x0700);
- wm8994_write(0x222, 0x3126);
- wm8994_write(0x223, 0x0100);
- wm8994_write(0x210, 0x0083); // SR=48KHz
-
- wm8994_write(0x220, 0x0004);
- msleep(WM8994_DELAY);
- wm8994_write(0x220, 0x0005); // FLL1_FRACN_ENA=1, FLL1_ENA=1
- wm8994_write(0x200, 0x0011); // AIF1CLK_SRC=10, AIF1CLK_ENA=1
-
- wm8994_write(0x02, 0x6110); // TSHUT_ENA=1, TSHUT_OPDIS=1, MIXINR_ENA=1,IN1R_ENA=1
- wm8994_write(0x04, 0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
- wm8994_write(0x28, 0x0003); // IN1RP_TO_IN1R=1, IN1RN_TO_IN1R=1
- vol=CONFIG_WM8994_RECORDER_VOL;
- if(vol>60)vol=60;
- if(vol<-16)vol=-16;
- if(vol<30){
- wm8994_write(0x1A, 320+(vol+16)*10/15); //mic vol
- }else{
- wm8994_write(0x2A, 0x0030);
- wm8994_write(0x1A, 320+(vol-14)*10/15); //mic vol
+ if (aif)
+ offset = 4;
+ else
+ offset = 0;
+
+ switch (wm8994->sysclk[aif]) {
+ case WM8994_SYSCLK_MCLK1:
+ rate = wm8994->mclk[0];
+ break;
+
+ case WM8994_SYSCLK_MCLK2:
+ reg1 |= 0x8;
+ rate = wm8994->mclk[1];
+ break;
+
+ case WM8994_SYSCLK_FLL1:
+ reg1 |= 0x10;
+ rate = wm8994->fll[0].out;
+ break;
+
+ case WM8994_SYSCLK_FLL2:
+ reg1 |= 0x18;
+ rate = wm8994->fll[1].out;
+ break;
+
+ default:
+ return -EINVAL;
}
- vol=CONFIG_WM8994_SPEAKER_NORMAL_VOL;
- if(vol>18)vol=18;
- if(vol<-57)vol=-57;
- if(vol<=6){
- wm8994_write(0x26, 320+vol+57); //-57dB~6dB
- wm8994_write(0x27, 320+vol+57); //-57dB~6dB
- }else{
- wm8994_write(0x25, 0x003F); //0~12dB
- wm8994_write(0x26, 320+vol+39); //-57dB~6dB
- wm8994_write(0x27, 320+vol+39); //-57dB~6dB
+ if (rate >= 13500000) {
+ rate /= 2;
+ reg1 |= WM8994_AIF1CLK_DIV;
+
+ DBG_INFO(codec->dev, "Dividing AIF%d clock to %dHz\n",
+ aif + 1, rate);
}
+ wm8994->aifclk[aif] = rate;
- wm8994_write(0x200, 0x0011); // AIF1CLK_ENA=1
- wm8994_write(0x208, 0x000A); // DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
- wm8994_write(0x300, 0xC050); // AIF1ADCL_SRC=1, AIF1ADCR_SRC=1, AIF1_WL=10, AIF1_FMT=10
- wm8994_write(0x606, 0x0002); // ADC1L_TO_AIF1ADC1L=1
- wm8994_write(0x607, 0x0002); // ADC1R_TO_AIF1ADC1R=1
- wm8994_write(0x620, 0x0000);
-
- wm8994_write(0x402, 0x01FF); // AIF1ADC1L_VOL [7:0]
- wm8994_write(0x403, 0x01FF); // AIF1ADC1R_VOL [7:0]
-
- wm8994_write(0x700, 0xA101);
-
- wm8994_write(0x01, 0x3013);
- wm8994_write(0x03, 0x0330); // SPKRVOL_ENA=1, SPKLVOL_ENA=1, MIXOUTL_ENA=1, MIXOUTR_ENA=1
- wm8994_write(0x05, 0x0303); // AIF1DAC1L_ENA=1, AIF1DAC1R_ENA=1, DAC1L_ENA=1, DAC1R_ENA=1
- wm8994_write(0x22, 0x0000);
- wm8994_write(0x23, 0x0100); // SPKOUT_CLASSAB=1
-
- wm8994_write(0x2D, 0x0001); // DAC1L_TO_MIXOUTL=1
- wm8994_write(0x2E, 0x0001); // DAC1R_TO_MIXOUTR=1
- wm8994_write(0x4C, 0x9F25);
- wm8994_write(0x60, 0x00EE);
- wm8994_write(0x36, 0x000C); // MIXOUTL_TO_SPKMIXL=1, MIXOUTR_TO_SPKMIXR=1
- wm8994_write(0x601, 0x0001); // AIF1DAC1L_TO_DAC1L=1
- wm8994_write(0x602, 0x0001); // AIF1DAC1R_TO_DAC1R=1
- wm8994_write(0x610, 0x01C0); // DAC1_VU=1, DAC1L_VOL=1100_0000
- wm8994_write(0x611, 0x01C0); // DAC1_VU=1, DAC1R_VOL=1100_0000
- wm8994_write(0x420, 0x0000);
-#ifdef CONFIG_SND_CODEC_SOC_MASTER
- wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
- wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
- wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
- wm8994_write(0x302, 0x3000); // AIF1_MSTR=1
- msleep(50);
- wm8994_write(0x302, 0x7000); // AIF1_MSTR=1
- msleep(50);
-#endif
-}
+ snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
+ WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
+ reg1);
-void FM_to_headset(void)
-{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_FM_to_headset)return;
- wm8994_current_mode=wm8994_FM_to_headset;
- wm8994_reset();
- msleep(WM8994_DELAY);
-
- wm8994_write(0x01, 0x0323);
- wm8994_write(0x02, 0x03A0);
- wm8994_write(0x03, 0x0030);
- wm8994_write(0x19, 0x010B); //LEFT LINE INPUT 3&4 VOLUME
- wm8994_write(0x1B, 0x010B); //RIGHT LINE INPUT 3&4 VOLUME
-
- wm8994_write(0x28, 0x0044);
- wm8994_write(0x29, 0x0100);
- wm8994_write(0x2A, 0x0100);
- wm8994_write(0x2D, 0x0040);
- wm8994_write(0x2E, 0x0040);
- wm8994_write(0x4C, 0x9F25);
- wm8994_write(0x60, 0x00EE);
- wm8994_write(0x220, 0x0003);
- wm8994_write(0x221, 0x0700);
- wm8994_write(0x224, 0x0CC0);
- wm8994_write(0x200, 0x0011);
- wm8994_write(0x1C, 0x01F9); //LEFT OUTPUT VOLUME
- wm8994_write(0x1D, 0x01F9); //RIGHT OUTPUT VOLUME
+ return 0;
}
-void FM_to_headset_and_record(void)
+static int configure_clock(struct snd_soc_codec *codec)
{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
+ struct wm8994_priv *wm8994 = codec->private_data;
+ int old, new;
- if(wm8994_current_mode==wm8994_FM_to_headset_and_record)return;
- wm8994_current_mode=wm8994_FM_to_headset_and_record;
- wm8994_reset();
- msleep(WM8994_DELAY);
+ /* Bring up the AIF clocks first */
+ configure_aif_clock(codec, 0);//AIF1
+ configure_aif_clock(codec, 1);//AIF2
- wm8994_write(0x01, 0x0003);
- msleep(WM8994_DELAY);
- wm8994_write(0x221, 0x1900); //8~13BIT div
+ /* Then switch CLK_SYS over to the higher of them; a change
+ * can only happen as a result of a clocking change which can
+ * only be made outside of DAPM so we can safely redo the
+ * clocking.
+ */
-#ifdef CONFIG_SND_CODEC_SOC_MASTER
- wm8994_write(0x302, 0x4000); // master = 0x4000 // slave= 0x0000
- wm8994_write(0x303, 0x0040); // master 0x0050 lrck 7.94kHz bclk 510KHz
-#endif
-
- wm8994_write(0x220, 0x0004);
- msleep(WM8994_DELAY);
- wm8994_write(0x220, 0x0005);
-
- wm8994_write(0x01, 0x0323);
- wm8994_write(0x02, 0x03A0);
- wm8994_write(0x03, 0x0030);
- wm8994_write(0x19, 0x010B); //LEFT LINE INPUT 3&4 VOLUME
- wm8994_write(0x1B, 0x010B); //RIGHT LINE INPUT 3&4 VOLUME
-
- wm8994_write(0x28, 0x0044);
- wm8994_write(0x29, 0x0100);
- wm8994_write(0x2A, 0x0100);
- wm8994_write(0x2D, 0x0040);
- wm8994_write(0x2E, 0x0040);
- wm8994_write(0x4C, 0x9F25);
- wm8994_write(0x60, 0x00EE);
- wm8994_write(0x200, 0x0011);
- wm8994_write(0x1C, 0x01F9); //LEFT OUTPUT VOLUME
- wm8994_write(0x1D, 0x01F9); //RIGHT OUTPUT VOLUME
- wm8994_write(0x04, 0x0303);
- wm8994_write(0x208, 0x000A);
- wm8994_write(0x300, 0x4050);
- wm8994_write(0x606, 0x0002);
- wm8994_write(0x607, 0x0002);
- wm8994_write(0x620, 0x0000);
-}
+ /* If they're equal it doesn't matter which is used */
+ if (wm8994->aifclk[0] == wm8994->aifclk[1])
+ return 0;
-void FM_to_speakers(void)
-{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_FM_to_speakers)return;
- wm8994_current_mode=wm8994_FM_to_speakers;
- wm8994_reset();
- msleep(WM8994_DELAY);
-
- wm8994_write(0x01, 0x3023);
- wm8994_write(0x02, 0x03A0);
- wm8994_write(0x03, 0x0330);
- wm8994_write(0x19, 0x010B); //LEFT LINE INPUT 3&4 VOLUME
- wm8994_write(0x1B, 0x010B); //RIGHT LINE INPUT 3&4 VOLUME
-
- wm8994_write(0x22, 0x0000);
- wm8994_write(0x23, 0x0000);
- wm8994_write(0x36, 0x000C);
-
- wm8994_write(0x28, 0x0044);
- wm8994_write(0x29, 0x0100);
- wm8994_write(0x2A, 0x0100);
- wm8994_write(0x2D, 0x0040);
- wm8994_write(0x2E, 0x0040);
-
- wm8994_write(0x220, 0x0003);
- wm8994_write(0x221, 0x0700);
- wm8994_write(0x224, 0x0CC0);
-
- wm8994_write(0x200, 0x0011);
- wm8994_write(0x20, 0x01F9);
- wm8994_write(0x21, 0x01F9);
-}
+ if (wm8994->aifclk[0] < wm8994->aifclk[1])
+ new = WM8994_SYSCLK_SRC;
+ else
+ new = 0;
-void FM_to_speakers_and_record(void)
-{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
+ old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
- if(wm8994_current_mode==wm8994_FM_to_speakers_and_record)return;
- wm8994_current_mode=wm8994_FM_to_speakers_and_record;
- wm8994_reset();
- msleep(WM8994_DELAY);
+ /* If there's no change then we're done. */
+ if (old == new)
+ return 0;
- wm8994_write(0x01, 0x0003);
- msleep(WM8994_DELAY);
+ snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
-#ifdef CONFIG_SND_CODEC_SOC_MASTER
- wm8994_write(0x302, 0x4000); // master = 0x4000 // slave= 0x0000
- wm8994_write(0x303, 0x0090); //
-#endif
-
- wm8994_write(0x220, 0x0006);
- msleep(WM8994_DELAY);
-
- wm8994_write(0x01, 0x3023);
- wm8994_write(0x02, 0x03A0);
- wm8994_write(0x03, 0x0330);
- wm8994_write(0x19, 0x010B); //LEFT LINE INPUT 3&4 VOLUME
- wm8994_write(0x1B, 0x010B); //RIGHT LINE INPUT 3&4 VOLUME
-
- wm8994_write(0x22, 0x0000);
- wm8994_write(0x23, 0x0000);
- wm8994_write(0x36, 0x000C);
-
- wm8994_write(0x28, 0x0044);
- wm8994_write(0x29, 0x0100);
- wm8994_write(0x2A, 0x0100);
- wm8994_write(0x2D, 0x0040);
- wm8994_write(0x2E, 0x0040);
-
- wm8994_write(0x220, 0x0003);
- wm8994_write(0x221, 0x0700);
- wm8994_write(0x224, 0x0CC0);
-
- wm8994_write(0x200, 0x0011);
- wm8994_write(0x20, 0x01F9);
- wm8994_write(0x21, 0x01F9);
- wm8994_write(0x04, 0x0303);
- wm8994_write(0x208, 0x000A);
- wm8994_write(0x300, 0x4050);
- wm8994_write(0x606, 0x0002);
- wm8994_write(0x607, 0x0002);
- wm8994_write(0x620, 0x0000);
+ snd_soc_dapm_sync(codec);
+
+ return 0;
}
-#ifndef PCM_BB
-void handsetMIC_to_baseband_to_headset(void)
+
+static int check_clk_sys(struct snd_soc_dapm_widget *source,
+ struct snd_soc_dapm_widget *sink)
{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset)return;
- wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset;
- wm8994_reset();
- msleep(WM8994_DELAY);
-
- wm8994_write(0x01, 0x0003);
- msleep(50);
-
- wm8994_write(0x200, 0x0001);
- wm8994_write(0x220, 0x0000);
- wm8994_write(0x221, 0x0700);
- wm8994_write(0x222, 0x3126);
- wm8994_write(0x223, 0x0100);
-
- wm8994_write(0x210, 0x0083); // SR=48KHz
- wm8994_write(0x220, 0x0004);
- msleep(WM8994_DELAY);
- wm8994_write(0x220, 0x0005);
- wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1) 0x0011
- wm8994_write(0x300, 0xC010); // i2s 16 bits
-
- vol=CONFIG_WM8994_HEADSET_INCALL_MIC_VOL;
- if(vol>30)vol=30;
- if(vol<-22)vol=-22;
- if(vol<-16){
- wm8994_write(0x1E, 0x0016); //mic vol
- wm8994_write(0x18, 320+(vol+22)*10/15); //mic vol
- }else{
- wm8994_write(0x1E, 0x0006); //mic vol
- wm8994_write(0x18, 320+(vol+16)*10/15); //mic vol
- }
+ int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
+ const char *clk;
- wm8994_write(0x22, 0x0000);
- wm8994_write(0x23, 0x0100);
- wm8994_write(0x28, 0x0030); //IN1LN_TO_IN1L IN1LP_TO_IN1L
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
-
- wm8994_write(0x34, 0x0002); //IN1L_TO_LINEOUT1P
- wm8994_write(0x36, 0x0003);
-
- wm8994_write(0x4C, 0x9F25);
- msleep(5);
- wm8994_write(0x01, 0x0323);
- msleep(50);
- wm8994_write(0x60, 0x0022);
- wm8994_write(0x60, 0x00EE);
-
- wm8994_write(0x02, 0x6040);
- wm8994_write(0x03, 0x3030);
- wm8994_write(0x04, 0x0300); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1
- wm8994_write(0x05, 0x0303);
-#ifdef CONFIG_SND_BB_NORMAL_INPUT
- wm8994_write(0x2D, 0x0003); //bit 1 IN2LP_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L 0x0102
- wm8994_write(0x2E, 0x0003); //bit 1 IN2RP_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R 0x0102
-#endif
-#ifdef CONFIG_SND_BB_DIFFERENTIAL_INPUT
- vol=CONFIG_WM8994_HEADSET_INCALL_VOL;
- if(vol>6)vol=6;
- if(vol<-12)vol=-12;
- wm8994_write(0x2B, (vol+12)/3+1); //-12~6dB
- wm8994_write(0x02, 0x6240);
- wm8994_write(0x2D, 0x0041); //bit 1 MIXINL_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L 0x0102
- wm8994_write(0x2E, 0x0081); //bit 1 MIXINL_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R 0x0102
-#endif
- wm8994_write(0x208, 0x000A);
- wm8994_write(0x224, 0x0CC0);
- wm8994_write(0x420, 0x0000);
- wm8994_write(0x601, 0x0001);
- wm8994_write(0x602, 0x0001);
-
- wm8994_write(0x610, 0x01A0); //DAC1 Left Volume bit0~7
- wm8994_write(0x611, 0x01A0); //DAC1 Right Volume bit0~7
- wm8994_write(0x700, 0xA101);
-#ifdef CONFIG_SND_CODEC_SOC_MASTER
- wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
- wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
- wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
- wm8994_write(0x302, 0x3000); // AIF1_MSTR=1
- msleep(50);
- wm8994_write(0x302, 0x7000); // AIF1_MSTR=1
- msleep(50);
-#endif
+ /* Check what we're currently using for CLK_SYS */
+ if (reg & WM8994_SYSCLK_SRC)
+ clk = "AIF2CLK";
+ else
+ clk = "AIF1CLK";
+
+ return strcmp(source->name, clk) == 0;
}
-void handsetMIC_to_baseband_to_headset_and_record(void)
+static const char *sidetone_hpf_text[] = {
+ "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
+};
+
+static const struct soc_enum sidetone_hpf =
+ SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
+
+static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
+static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
+static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
+static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
+static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
+
+//--------------------------------------------------------------------------------
+//WM8994_DRC_SWITCH
+//--------------------------------------------------------------------------------
+#define WM8994_DRC_SWITCH(xname, reg, shift) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+ .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
+ .put = wm8994_put_drc_sw, \
+ .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
+
+static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset_and_record)return;
- wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset_and_record;
- wm8994_reset();
- msleep(WM8994_DELAY);
-
- wm8994_write(0x01, 0x0303|wm8994_mic_VCC);
- wm8994_write(0x02, 0x62C0);
- wm8994_write(0x03, 0x3030);
- wm8994_write(0x04, 0x0303);
- wm8994_write(0x18, 0x014B); //volume
- wm8994_write(0x19, 0x014B); //volume
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
- wm8994_write(0x1E, 0x0006);
- wm8994_write(0x28, 0x00B0); //IN2LP_TO_IN2L
- wm8994_write(0x29, 0x0120);
- wm8994_write(0x2D, 0x0002); //bit 1 IN2LP_TO_MIXOUTL
- wm8994_write(0x2E, 0x0002); //bit 1 IN2RP_TO_MIXOUTR
- wm8994_write(0x34, 0x0002);
- wm8994_write(0x4C, 0x9F25);
- wm8994_write(0x60, 0x00EE);
- wm8994_write(0x200, 0x0001);
- wm8994_write(0x208, 0x000A);
- wm8994_write(0x300, 0x0050);
-
-#ifdef CONFIG_SND_CODEC_SOC_MASTER
- wm8994_write(0x302, 0x4000); // master = 0x4000 // slave= 0x0000
- wm8994_write(0x303, 0x0090); // master lrck 16k
-#endif
+ struct soc_mixer_control *mc =
+ (struct soc_mixer_control *)kcontrol->private_value;
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int mask, ret;
+
+ /* Can't enable both ADC and DAC paths simultaneously */
+ if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
+ mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
+ WM8994_AIF1ADC1R_DRC_ENA_MASK;
+ else
+ mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
+
+ ret = snd_soc_read(codec, mc->reg);
+ if (ret < 0)
+ return ret;
+ if (ret & mask)
+ return -EINVAL;
- wm8994_write(0x606, 0x0002);
- wm8994_write(0x607, 0x0002);
- wm8994_write(0x620, 0x0000);
+ return snd_soc_put_volsw(kcontrol, ucontrol);
}
-void mainMIC_to_baseband_to_earpiece(void)
+static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece)return;
- wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece;
- wm8994_reset();
- msleep(WM8994_DELAY);
-
- wm8994_write(0x01, 0x0003);
- msleep(WM8994_DELAY);
-
- wm8994_write(0x200, 0x0001);
- wm8994_write(0x220, 0x0000);
- wm8994_write(0x221, 0x0700);
- wm8994_write(0x222, 0x3126);
- wm8994_write(0x223, 0x0100);
-
- wm8994_write(0x210, 0x0083); // SR=48KHz
- wm8994_write(0x220, 0x0004);
- msleep(WM8994_DELAY);
- wm8994_write(0x220, 0x0005);
- wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1) 0x0011
- wm8994_write(0x300, 0x4010); // i2s 16 bits
-
- wm8994_write(0x01, 0x0833); //HPOUT2_ENA=1, VMID_SEL=01, BIAS_ENA=1
- wm8994_write(0x02, 0x6250); //bit4 IN1R_ENV bit6 IN1L_ENV
- wm8994_write(0x03, 0x30F0);
- wm8994_write(0x04, 0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
- wm8994_write(0x05, 0x0303);
- wm8994_write(0x1F, 0x0000);
-#if defined(CONFIG_SND_INSIDE_EARPIECE)||defined(CONFIG_SND_OUTSIDE_EARPIECE)
- vol=CONFIG_WM8994_EARPIECE_INCALL_VOL;
- if(vol>30)vol=30;
- if(vol<-27)vol=-27;
- if(vol>9){
- wm8994_write(0x2E, 0x0081); //30dB
- wm8994_write(0x33, 0x0018); //30dB
- wm8994_write(0x31, (((30-vol)/3)<<3)+(30-vol)/3); //-21dB
- }else if(vol>3){
- wm8994_write(0x2E, 0x0081); //30dB
- wm8994_write(0x33, 0x0018); //30dB
- wm8994_write(0x31, (((24-vol)/3)<<3)+(24-vol)/3); //-21dB
- wm8994_write(0x1F, 0x0010);
- }else if(vol>=0){
- }else if(vol>-21){
- wm8994_write(0x31, (((-vol)/3)<<3)+(-vol)/3); //-21dB
- }else{
- wm8994_write(0x1F, 0x0010);
- wm8994_write(0x31, (((-vol-6)/3)<<3)+(-vol-6)/3); //-21dB
- }
-#ifdef CONFIG_SND_INSIDE_EARPIECE
- wm8994_write(0x28, 0x0003); //IN1RP_TO_IN1R IN1RN_TO_IN1R
- wm8994_write(0x34, 0x0004); //IN1R_TO_LINEOUT1P
- vol=CONFIG_WM8994_SPEAKER_INCALL_MIC_VOL;
- if(vol>30)vol=30;
- if(vol<-22)vol=-22;
- if(vol<-16){
- wm8994_write(0x1E, 0x0016);
- wm8994_write(0x1A, 320+(vol+22)*10/15);
- }else{
- wm8994_write(0x1E, 0x0006);
- wm8994_write(0x1A, 320+(vol+16)*10/15);
- }
-#endif
-#ifdef CONFIG_SND_OUTSIDE_EARPIECE
- wm8994_write(0x28, 0x0030); //IN1LP_TO_IN1L IN1LN_TO_IN1L
- wm8994_write(0x34, 0x0002); //IN1L_TO_LINEOUT1P
- vol=CONFIG_WM8994_HEADSET_INCALL_MIC_VOL;
- if(vol>30)vol=30;
- if(vol<-22)vol=-22;
- if(vol<-16){
- wm8994_write(0x1E, 0x0016); //mic vol
- wm8994_write(0x18, 320+(vol+22)*10/15); //mic vol
- }else{
- wm8994_write(0x1E, 0x0006); //mic vol
- wm8994_write(0x18, 320+(vol+16)*10/15); //mic vol
- }
-#endif
-#endif
-#ifdef CONFIG_SND_BB_NORMAL_INPUT
- wm8994_write(0x2D, 0x0003); //bit 1 IN2LP_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L 0x0102
- wm8994_write(0x2E, 0x0003); //bit 1 IN2RP_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R 0x0102
-#endif
-#ifdef CONFIG_SND_BB_DIFFERENTIAL_INPUT
- wm8994_write(0x2B, 0x0005); //VRX_MIXINL_VOL
- wm8994_write(0x2D, 0x0041); //bit 1 MIXINL_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L 0x0102
- wm8994_write(0x2E, 0x0081); //bit 1 MIXINL_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R 0x0102
-#endif
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
- wm8994_write(0x33, 0x0010);
-
- wm8994_write(0x208, 0x000A); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
- wm8994_write(0x601, 0x0001); //AIF1DAC1L_TO_DAC1L=1
- wm8994_write(0x602, 0x0001); //AIF1DAC1R_TO_DAC1R=1
- wm8994_write(0x610, 0x01C0); //DAC1_VU=1, DAC1L_VOL=1100_0000
- wm8994_write(0x611, 0x01C0); //DAC1_VU=1, DAC1R_VOL=1100_0000
-
- wm8994_write(0x420, 0x0000);
- wm8994_write(0x700, 0xA101);
-#ifdef CONFIG_SND_CODEC_SOC_MASTER
- wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
- wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
- wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
- wm8994_write(0x302, 0x3000); // AIF1_MSTR=1
- msleep(50);
- wm8994_write(0x302, 0x7000); // AIF1_MSTR=1
- msleep(50);
-#endif
+ struct wm8994_priv *wm8994 = codec->private_data;
+ struct wm8994_pdata *pdata = wm8994->pdata;
+ int base = wm8994_drc_base[drc];
+ int cfg = wm8994->drc_cfg[drc];
+ int save, i;
+
+ /* Save any enables; the configuration should clear them. */
+ save = snd_soc_read(codec, base);
+ save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
+ WM8994_AIF1ADC1R_DRC_ENA;
+
+ for (i = 0; i < WM8994_DRC_REGS; i++)
+ snd_soc_update_bits(codec, base + i, 0xffff,
+ pdata->drc_cfgs[cfg].regs[i]);
+
+ snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
+ WM8994_AIF1ADC1L_DRC_ENA |
+ WM8994_AIF1ADC1R_DRC_ENA, save);
}
-void mainMIC_to_baseband_to_earpiece_I2S(void)
+/* Icky as hell but saves code duplication */
+static int wm8994_get_drc(const char *name)
{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece)return;
- wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece;
- wm8994_reset();
- msleep(WM8994_DELAY);
-
- wm8994_write(0x01, 0x0003);
- msleep(WM8994_DELAY);
-
- wm8994_write(0x200, 0x0001);
- wm8994_write(0x220, 0x0000);
- wm8994_write(0x221, 0x0700);
- wm8994_write(0x222, 0x3126);
- wm8994_write(0x223, 0x0100);
-
- wm8994_write(0x210, 0x0083); // SR=48KHz
- wm8994_write(0x220, 0x0004);
- msleep(WM8994_DELAY);
- wm8994_write(0x220, 0x0005);
- wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1)
-
- wm8994_write(0x02, 0x6240);
- wm8994_write(0x04, 0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
- wm8994_write(0x18, 0x015B); //IN1_VU=1, IN1L_MUTE=0, IN1L_ZC=1, IN1L_VOL=0_1011
- wm8994_write(0x1E, 0x0006);
- wm8994_write(0x1F, 0x0000);
- wm8994_write(0x28, 0x0030);
- wm8994_write(0x29, 0x0020); //IN1L_TO_MIXINL=1, IN1L_MIXINL_VOL=0, MIXOUTL_MIXINL_VOL=000
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
-
- wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1)
-
- wm8994_write(0x208, 0x000A); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
- wm8994_write(0x300, 0x0050); //AIF1ADCL_SRC=1, AIF1ADCR_SRC=1
- wm8994_write(0x606, 0x0002); //ADC1L_TO_AIF1ADC1L=1
- wm8994_write(0x607, 0x0002); //ADC1R_TO_AIF1ADC1R=1
-
- wm8994_write(0x620, 0x0000);
- wm8994_write(0x700, 0xA101);
-
- wm8994_write(0x01, 0x0833); //HPOUT2_ENA=1, VMID_SEL=01, BIAS_ENA=1
- wm8994_write(0x03, 0x30F0);
- wm8994_write(0x05, 0x0303);
- wm8994_write(0x2D, 0x0021); //DAC1L_TO_MIXOUTL=1
- wm8994_write(0x2E, 0x0001); //DAC1R_TO_MIXOUTR=1
-
- wm8994_write(0x4C, 0x9F25);
- wm8994_write(0x60, 0x00EE);
-
- wm8994_write(0x33, 0x0010);
- wm8994_write(0x34, 0x0002);
-
- wm8994_write(0x601, 0x0001); //AIF1DAC1L_TO_DAC1L=1
- wm8994_write(0x602, 0x0001); //AIF1DAC1R_TO_DAC1R=1
- wm8994_write(0x610, 0x01FF); //DAC1_VU=1, DAC1L_VOL=1100_0000
- wm8994_write(0x611, 0x01FF); //DAC1_VU=1, DAC1R_VOL=1100_0000
-
- wm8994_write(0x420, 0x0000);
- wm8994_write(0x700, 0xA101);
-#ifdef CONFIG_SND_CODEC_SOC_MASTER
- wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
- wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
- wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
- wm8994_write(0x302, 0x3000); // AIF1_MSTR=1
- msleep(50);
- wm8994_write(0x302, 0x7000); // AIF1_MSTR=1
- msleep(50);
-#endif
+ if (strcmp(name, "AIF1DRC1 Mode") == 0)
+ return 0;
+ if (strcmp(name, "AIF1DRC2 Mode") == 0)
+ return 1;
+ if (strcmp(name, "AIF2DRC Mode") == 0)
+ return 2;
+ return -EINVAL;
}
-void mainMIC_to_baseband_to_earpiece_and_record(void)
+static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece_and_record)return;
- wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece_and_record;
- wm8994_reset();
- msleep(WM8994_DELAY);
-
- wm8994_write(0x01 ,0x0803|wm8994_mic_VCC);
- wm8994_write(0x02 ,0x6310);
- wm8994_write(0x03 ,0x30A0);
- wm8994_write(0x04 ,0x0303);
- wm8994_write(0x1A ,0x014F);
- wm8994_write(0x1E ,0x0006);
- wm8994_write(0x1F ,0x0000);
- wm8994_write(0x28 ,0x0003); //MAINMIC_TO_IN1R //
- wm8994_write(0x2A ,0x0020); //IN1R_TO_MIXINR //
- wm8994_write(0x2B ,0x0005); //VRX_MIXINL_VOL bit 0~2
- wm8994_write(0x2C ,0x0005); //VRX_MIXINR_VOL
- wm8994_write(0x2D ,0x0040); //MIXINL_TO_MIXOUTL
- wm8994_write(0x33 ,0x0010); //MIXOUTLVOL_TO_HPOUT2
- wm8994_write(0x34 ,0x0004); //IN1R_TO_LINEOUT1 //
- wm8994_write(0x200 ,0x0001);
- wm8994_write(0x208 ,0x000A);
- wm8994_write(0x300 ,0xC050);
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
-
-#ifdef CONFIG_SND_CODEC_SOC_MASTER
- wm8994_write(0x302, 0x4000); // master = 0x4000 // slave= 0x0000
- wm8994_write(0x303, 0x0090); // master lrck 16k
-#endif
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct wm8994_priv *wm8994 = codec->private_data;
+ struct wm8994_pdata *pdata = wm8994->pdata;
+ int drc = wm8994_get_drc(kcontrol->id.name);
+ int value = ucontrol->value.integer.value[0];
- wm8994_write(0x606 ,0x0002);
- wm8994_write(0x607 ,0x0002);
- wm8994_write(0x620 ,0x0000);
-}
+ if (drc < 0)
+ return drc;
-void mainMIC_to_baseband_to_speakers(void)
-{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers)return;
- wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers;
- wm8994_reset();
- msleep(WM8994_DELAY);
-
- wm8994_write(0x01, 0x0003);
- msleep(WM8994_DELAY);
-
- wm8994_write(0x200, 0x0001);
- wm8994_write(0x220, 0x0000);
- wm8994_write(0x221, 0x0700);
- wm8994_write(0x222, 0x3126);
- wm8994_write(0x223, 0x0100);
-
- wm8994_write(0x210, 0x0083); // SR=48KHz
- msleep(WM8994_DELAY);
- wm8994_write(0x220, 0x0005);
- wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1) 0x0011
- wm8994_write(0x300, 0xC010); // i2s 16 bits
-
- wm8994_write(0x01, 0x3013);
- wm8994_write(0x02, 0x6210);
- wm8994_write(0x03, 0x33F0);
- wm8994_write(0x04, 0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
- wm8994_write(0x05, 0x0303);
- wm8994_write(0x22, 0x0000);
- wm8994_write(0x23, 0x0100);
- vol=CONFIG_WM8994_SPEAKER_INCALL_MIC_VOL;
- if(vol>30)vol=30;
- if(vol<-22)vol=-22;
- if(vol<-16){
- wm8994_write(0x1E, 0x0016);
- wm8994_write(0x1A, 320+(vol+22)*10/15);
- }else{
- wm8994_write(0x1E, 0x0006);
- wm8994_write(0x1A, 320+(vol+16)*10/15);
- }
- vol=CONFIG_WM8994_SPEAKER_INCALL_VOL;
- if(vol>12)vol=12;
- if(vol<-21)vol=-21;
- if(vol<0){
- wm8994_write(0x31, (((-vol)/3)<<3)+(-vol)/3);
- }else{
- wm8994_write(0x25, ((vol*10/15)<<3)+vol*10/15);
- }
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
- wm8994_write(0x28, 0x0003); //IN1RP_TO_IN1R IN1RN_TO_IN1R
-#ifdef CONFIG_SND_BB_NORMAL_INPUT
- wm8994_write(0x2D, 0x0003); //bit 1 IN2LP_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L 0x0102
- wm8994_write(0x2E, 0x0003); //bit 1 IN2RP_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R 0x0102
-#endif
-#ifdef CONFIG_SND_BB_DIFFERENTIAL_INPUT
- wm8994_write(0x2B, 0x0005); //VRX_MIXINL_VOL
- wm8994_write(0x2D, 0x0041); //bit 1 MIXINL_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L 0x0102
- wm8994_write(0x2E, 0x0081); //bit 1 MIXINL_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R 0x0102
-#endif
- wm8994_write(0x4C, 0x9F25);
- wm8994_write(0x60, 0x00EE);
- wm8994_write(0x34, 0x0004);
- wm8994_write(0x36, 0x000C); //MIXOUTL_TO_SPKMIXL MIXOUTR_TO_SPKMIXR
+ if (value >= pdata->num_drc_cfgs)
+ return -EINVAL;
- wm8994_write(0x208, 0x000A);
- wm8994_write(0x420, 0x0000);
-
- wm8994_write(0x601, 0x0001);
- wm8994_write(0x602, 0x0001);
-
- wm8994_write(0x610, 0x01c0); //DAC1 Left Volume bit0~7
- wm8994_write(0x611, 0x01c0); //DAC1 Right Volume bit0~7
- wm8994_write(0x700, 0xA101);
-#ifdef CONFIG_SND_CODEC_SOC_MASTER
- wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
- wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
- wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
- wm8994_write(0x302, 0x3000); // AIF1_MSTR=1
- msleep(50);
- wm8994_write(0x302, 0x7000); // AIF1_MSTR=1
- msleep(50);
-#endif
-}
+ wm8994->drc_cfg[drc] = value;
-void mainMIC_to_baseband_to_speakers_and_record(void)
-{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers_and_record)return;
- wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers_and_record;
- wm8994_reset();
- msleep(WM8994_DELAY);
-
- wm8994_write(0x01, 0x3003|wm8994_mic_VCC);
- wm8994_write(0x02, 0x6330);
- wm8994_write(0x03, 0x3330);
- wm8994_write(0x04, 0x0303);
- wm8994_write(0x1A, 0x014B);
- wm8994_write(0x1B, 0x014B);
- wm8994_write(0x1E, 0x0006);
- wm8994_write(0x22, 0x0000);
- wm8994_write(0x23, 0x0100);
- wm8994_write(0x28, 0x0007);
- wm8994_write(0x2A, 0x0120);
- wm8994_write(0x2D, 0x0002); //bit 1 IN2LP_TO_MIXOUTL
- wm8994_write(0x2E, 0x0002); //bit 1 IN2RP_TO_MIXOUTR
- wm8994_write(0x34, 0x0004);
- wm8994_write(0x36, 0x000C);
- wm8994_write(0x200, 0x0001);
- wm8994_write(0x208, 0x000A);
- wm8994_write(0x300, 0xC050);
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
-
-#ifdef CONFIG_SND_CODEC_SOC_MASTER
- wm8994_write(0x302, 0x4000); // master = 0x4000 // slave= 0x0000
- wm8994_write(0x303, 0x0090); // master lrck 16k
-#endif
+ wm8994_set_drc(codec, drc);
- wm8994_write(0x606, 0x0002);
- wm8994_write(0x607, 0x0002);
- wm8994_write(0x620, 0x0000);
+ return 0;
}
-void BT_baseband(void)
+static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_BT_baseband)return;
- wm8994_current_mode=wm8994_BT_baseband;
- wm8994_reset();
- msleep(WM8994_DELAY);
-
- wm8994_write(0x01, 0x0003);
- wm8994_write(0x02, 0x63A0);
- wm8994_write(0x03, 0x30A0);
- wm8994_write(0x04, 0x3303);
- wm8994_write(0x05, 0x3002);
- wm8994_write(0x06, 0x000A);
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
- wm8994_write(0x1E, 0x0006);
- wm8994_write(0x29, 0x0100);
- wm8994_write(0x2A, 0x0100);
- vol=CONFIG_WM8994_BT_INCALL_MIC_VOL;
- if(vol>6)vol=6;
- if(vol<-57)vol=-57;
- wm8994_write(0x20, 320+vol+57);
-
- vol=CONFIG_WM8994_BT_INCALL_VOL;
- if(vol>30)vol=30;
- if(vol<0)vol=0;
- if(vol==30){
- wm8994_write(0x29, 0x0130);
- wm8994_write(0x2A, 0x0130);
- }
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct wm8994_priv *wm8994 = codec->private_data;
+ int drc = wm8994_get_drc(kcontrol->id.name);
-#ifdef CONFIG_SND_BB_NORMAL_INPUT
- wm8994_write(0x28, 0x00C0);
-#endif
-#ifdef CONFIG_SND_BB_DIFFERENTIAL_INPUT
- wm8994_write(0x28, 0x00CC);
-#endif
- wm8994_write(0x2D, 0x0001);
- wm8994_write(0x34, 0x0001);
- wm8994_write(0x200, 0x0001);
-
- //roger_chen@20100524
- //8KHz, BCLK=8KHz*128=1024KHz, Fout=2.048MHz
- wm8994_write(0x204, 0x0001); // SMbus_16inx_16dat Write 0x34 * AIF2 Clocking (1)(204H): 0011 AIF2CLK_SRC=00, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
- wm8994_write(0x208, 0x000F);
- wm8994_write(0x220, 0x0000); // SMbus_16inx_16dat Write 0x34 * FLL1 Control (1)(220H): 0005 FLL1_FRACN_ENA=0, FLL1_OSC_ENA=0, FLL1_ENA=0
- wm8994_write(0x221, 0x2F00); // SMbus_16inx_16dat Write 0x34 * FLL1 Control (2)(221H): 0700 FLL1_OUTDIV=2Fh, FLL1_CTRL_RATE=000, FLL1_FRATIO=000
- wm8994_write(0x222, 0x3126); // SMbus_16inx_16dat Write 0x34 * FLL1 Control (3)(222H): 8FD5 FLL1_K=3126h
- wm8994_write(0x223, 0x0100); // SMbus_16inx_16dat Write 0x34 * FLL1 Control (4)(223H): 00E0 FLL1_N=8h, FLL1_GAIN=0000
- wm8994_write(0x310, 0xC118); //DSP/PCM; 16bits; ADC L channel = R channel;MODE A
-
- wm8994_write(0x210, 0x0003); // SMbus_16inx_16dat Write 0x34 * SR=8KHz
- wm8994_write(0x220, 0x0004); // SMbus_16inx_16dat Write 0x34 * FLL1 Control (1)(220H): 0005 FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=0
- msleep(50);
- wm8994_write(0x220, 0x0005); // SMbus_16inx_16dat Write 0x34 * FLL1 Control (1)(220H): 0005 FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=1
- wm8994_write(0x200, 0x0011);
- wm8994_write(0x204, 0x0011); // SMbus_16inx_16dat Write 0x34 * AIF2 Clocking (1)(204H): 0011 AIF2CLK_SRC=10, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
-
- wm8994_write(0x440, 0x0018);
- wm8994_write(0x450, 0x0018);
- wm8994_write(0x480, 0x0000);
- wm8994_write(0x481, 0x0000);
- wm8994_write(0x4A0, 0x0000);
- wm8994_write(0x4A1, 0x0000);
- wm8994_write(0x520, 0x0000);
- wm8994_write(0x540, 0x0018);
- wm8994_write(0x580, 0x0000);
- wm8994_write(0x581, 0x0000);
- wm8994_write(0x601, 0x0004);
- wm8994_write(0x603, 0x000C);
- wm8994_write(0x604, 0x0010);
- wm8994_write(0x605, 0x0010);
- wm8994_write(0x610, 0x01C0);
- wm8994_write(0x612, 0x01C0);
- wm8994_write(0x613, 0x01C0);
- wm8994_write(0x620, 0x0000);
-
- //roger_chen@20100519
- //enable AIF2 BCLK,LRCK
- //Rev.B and Rev.D is different
- wm8994_write(0x702, 0x2100);
- wm8994_write(0x703, 0x2100);
-
- wm8994_write(0x704, 0xA100);
- wm8994_write(0x707, 0xA100);
- wm8994_write(0x708, 0x2100);
- wm8994_write(0x709, 0x2100);
- wm8994_write(0x70A, 0x2100);
-#ifdef CONFIG_SND_CODEC_SOC_MASTER
- wm8994_write(0x700, 0xA101);
- wm8994_write(0x705, 0xA101);
- wm8994_write(0x303, 0x0090);
- wm8994_write(0x313, 0x0020); // SMbus_16inx_16dat Write 0x34 * AIF2 BCLK DIV--------AIF1CLK/2
- wm8994_write(0x314, 0x0080); // SMbus_16inx_16dat Write 0x34 * AIF2 ADCLRCK DIV-----BCLK/128
- wm8994_write(0x315, 0x0080); // SMbus_16inx_16dat Write 0x34 * AIF2 DACLRCK DIV-----BCLK/128
- msleep(30);
- wm8994_write(0x302, 0x3000);
- msleep(30);
- wm8994_write(0x302, 0x7000);
- msleep(30);
- wm8994_write(0x312, 0x3000); // SMbus_16inx_16dat Write 0x34 * AIF2 Master/Slave(312H): 7000 AIF2_TRI=0, AIF2_MSTR=1, AIF2_CLK_FRC=0, AIF2_LRCLK_FRC=0
- msleep(30);
- wm8994_write(0x312, 0x7000); // SMbus_16inx_16dat Write 0x34 * AIF2 Master/Slave(312H): 7000 AIF2_TRI=0, AIF2_MSTR=1, AIF2_CLK_FRC=0, AIF2_LRCLK_FRC=0
- msleep(50);
-#endif
+ ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
+
+ return 0;
}
-void BT_baseband_and_record(void)
+static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_BT_baseband_and_record)return;
- wm8994_current_mode=wm8994_BT_baseband_and_record;
- wm8994_reset();
- msleep(WM8994_DELAY);
-
- wm8994_write(0x01, 0x0003);
- wm8994_write(0x02, 0x63A0);
- wm8994_write(0x03, 0x30A0);
- wm8994_write(0x04, 0x3303);
- wm8994_write(0x05, 0x3002);
- wm8994_write(0x06, 0x000A);
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
- wm8994_write(0x1E, 0x0006);
- wm8994_write(0x28, 0x00CC);
- wm8994_write(0x29, 0x0100);
- wm8994_write(0x2A, 0x0100);
- wm8994_write(0x2D, 0x0001);
- wm8994_write(0x34, 0x0001);
- wm8994_write(0x200, 0x0001);
-
- //roger_chen@20100524
- //8KHz, BCLK=8KHz*128=1024KHz, Fout=2.048MHz
- wm8994_write(0x204, 0x0001); // SMbus_16inx_16dat Write 0x34 * AIF2 Clocking (1)(204H): 0011 AIF2CLK_SRC=00, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
- wm8994_write(0x208, 0x000F);
- wm8994_write(0x220, 0x0000); // SMbus_16inx_16dat Write 0x34 * FLL1 Control (1)(220H): 0005 FLL1_FRACN_ENA=0, FLL1_OSC_ENA=0, FLL1_ENA=0
- wm8994_write(0x221, 0x2F00); // SMbus_16inx_16dat Write 0x34 * FLL1 Control (2)(221H): 0700 FLL1_OUTDIV=2Fh, FLL1_CTRL_RATE=000, FLL1_FRATIO=000
- wm8994_write(0x222, 0x3126); // SMbus_16inx_16dat Write 0x34 * FLL1 Control (3)(222H): 8FD5 FLL1_K=3126h
- wm8994_write(0x223, 0x0100); // SMbus_16inx_16dat Write 0x34 * FLL1 Control (4)(223H): 00E0 FLL1_N=8h, FLL1_GAIN=0000
- wm8994_write(0x302, 0x4000);
- wm8994_write(0x303, 0x0090);
- wm8994_write(0x310, 0xC118); //DSP/PCM; 16bits; ADC L channel = R channel;MODE A
- wm8994_write(0x312, 0x4000); // SMbus_16inx_16dat Write 0x34 * AIF2 Master/Slave(312H): 7000 AIF2_TRI=0, AIF2_MSTR=1, AIF2_CLK_FRC=0, AIF2_LRCLK_FRC=0
- wm8994_write(0x313, 0x0020); // SMbus_16inx_16dat Write 0x34 * AIF2 BCLK DIV--------AIF1CLK/2
- wm8994_write(0x314, 0x0080); // SMbus_16inx_16dat Write 0x34 * AIF2 ADCLRCK DIV-----BCLK/128
- wm8994_write(0x315, 0x0080); // SMbus_16inx_16dat Write 0x34 * AIF2 DACLRCK DIV-----BCLK/128
- wm8994_write(0x210, 0x0003); // SMbus_16inx_16dat Write 0x34 * SR=8KHz
- wm8994_write(0x220, 0x0004); // SMbus_16inx_16dat Write 0x34 * FLL1 Control (1)(220H): 0005 FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=0
- msleep(WM8994_DELAY);
- wm8994_write(0x220, 0x0005); // SMbus_16inx_16dat Write 0x34 * FLL1 Control (1)(220H): 0005 FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=1
- wm8994_write(0x204, 0x0011); // SMbus_16inx_16dat Write 0x34 * AIF2 Clocking (1)(204H): 0011 AIF2CLK_SRC=10, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
-
- wm8994_write(0x440, 0x0018);
- wm8994_write(0x450, 0x0018);
- wm8994_write(0x480, 0x0000);
- wm8994_write(0x481, 0x0000);
- wm8994_write(0x4A0, 0x0000);
- wm8994_write(0x4A1, 0x0000);
- wm8994_write(0x520, 0x0000);
- wm8994_write(0x540, 0x0018);
- wm8994_write(0x580, 0x0000);
- wm8994_write(0x581, 0x0000);
- wm8994_write(0x601, 0x0004);
- wm8994_write(0x603, 0x000C);
- wm8994_write(0x604, 0x0010);
- wm8994_write(0x605, 0x0010);
- wm8994_write(0x606, 0x0003);
- wm8994_write(0x607, 0x0003);
- wm8994_write(0x610, 0x01C0);
- wm8994_write(0x612, 0x01C0);
- wm8994_write(0x613, 0x01C0);
- wm8994_write(0x620, 0x0000);
-
- //roger_chen@20100519
- //enable AIF2 BCLK,LRCK
- //Rev.B and Rev.D is different
- wm8994_write(0x702, 0xA100);
- wm8994_write(0x703, 0xA100);
-
- wm8994_write(0x704, 0xA100);
- wm8994_write(0x707, 0xA100);
- wm8994_write(0x708, 0x2100);
- wm8994_write(0x709, 0x2100);
- wm8994_write(0x70A, 0x2100);
-}
+ struct wm8994_priv *wm8994 = codec->private_data;
+ struct wm8994_pdata *pdata = wm8994->pdata;
+ int base = wm8994_retune_mobile_base[block];
+ int iface, best, best_val, save, i, cfg;
+
+ if (!pdata || !wm8994->num_retune_mobile_texts)
+ return;
+
+ switch (block) {
+ case 0:
+ case 1:
+ iface = 0;
+ break;
+ case 2:
+ iface = 1;
+ break;
+ default:
+ return;
+ }
-#else //PCM_BB
+ /* Find the version of the currently selected configuration
+ * with the nearest sample rate. */
+ cfg = wm8994->retune_mobile_cfg[block];
+ best = 0;
+ best_val = INT_MAX;
+ for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
+ if (strcmp(pdata->retune_mobile_cfgs[i].name,
+ wm8994->retune_mobile_texts[cfg]) == 0 &&
+ abs(pdata->retune_mobile_cfgs[i].rate
+ - wm8994->dac_rates[iface]) < best_val) {
+ best = i;
+ best_val = abs(pdata->retune_mobile_cfgs[i].rate
+ - wm8994->dac_rates[iface]);
+ }
+ }
-/******************PCM BB BEGIN*****************/
+ dev_info(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
+ block,
+ pdata->retune_mobile_cfgs[best].name,
+ pdata->retune_mobile_cfgs[best].rate,
+ wm8994->dac_rates[iface]);
-void handsetMIC_to_baseband_to_headset(void) //pcmbaseband
-{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
+ /* The EQ will be disabled while reconfiguring it, remember the
+ * current configuration.
+ */
+ save = snd_soc_read(codec, base);
+ save &= WM8994_AIF1DAC1_EQ_ENA;
- if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset)return;
- wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset;
- wm8994_reset();
- msleep(50);
-
- wm8994_write(0x01, 0x0003|wm8994_mic_VCC);
- msleep(50);
- wm8994_write(0x221, 0x0700);
- wm8994_write(0x222, 0x3127);
- wm8994_write(0x223, 0x0100);
- wm8994_write(0x220, 0x0004);
- msleep(50);
- wm8994_write(0x220, 0x0005);
-
- wm8994_write(0x01, 0x0303|wm8994_mic_VCC); ///0x0303); // sysclk = fll (bit4 =1) 0x0011
- wm8994_write(0x02, 0x0240);
- wm8994_write(0x03, 0x0030);
- wm8994_write(0x04, 0x3003);
- wm8994_write(0x05, 0x3003); // i2s 16 bits
- wm8994_write(0x18, 0x010B);
- wm8994_write(0x28, 0x0030);
- wm8994_write(0x29, 0x0020);
- wm8994_write(0x2D, 0x0100); //0x0100);DAC1L_TO_HPOUT1L ;;;bit 8
- wm8994_write(0x2E, 0x0100); //0x0100);DAC1R_TO_HPOUT1R ;;;bit 8
- wm8994_write(0x4C, 0x9F25);
- wm8994_write(0x60, 0x00EE);
- wm8994_write(0x200, 0x0001);
- wm8994_write(0x204, 0x0001);
- wm8994_write(0x208, 0x0007);
- wm8994_write(0x520, 0x0000);
- wm8994_write(0x601, 0x0004); //AIF2DACL_TO_DAC1L
- wm8994_write(0x602, 0x0004); //AIF2DACR_TO_DAC1R
-
- wm8994_write(0x610, 0x01C0); //DAC1 Left Volume bit0~7
- wm8994_write(0x611, 0x01C0); //DAC1 Right Volume bit0~7
- wm8994_write(0x612, 0x01C0); //DAC2 Left Volume bit0~7
- wm8994_write(0x613, 0x01C0); //DAC2 Right Volume bit0~7
-
- wm8994_write(0x702, 0xC100);
- wm8994_write(0x703, 0xC100);
- wm8994_write(0x704, 0xC100);
- wm8994_write(0x706, 0x4100);
- wm8994_write(0x204, 0x0011);
- wm8994_write(0x211, 0x0009);
- #ifdef TD688_MODE
- wm8994_write(0x310, 0x4108); ///0x4118); ///interface dsp mode 16bit
- #endif
- #ifdef CHONGY_MODE
- wm8994_write(0x310, 0x4118); ///0x4118); ///interface dsp mode 16bit
- #endif
- #ifdef MU301_MODE
- wm8994_write(0x310, 0x4118); ///0x4118); ///interface dsp mode 16bit
- wm8994_write(0x241, 0x2f04);
- wm8994_write(0x242, 0x0000);
- wm8994_write(0x243, 0x0300);
- wm8994_write(0x240, 0x0004);
- msleep(40);
- wm8994_write(0x240, 0x0005);
- wm8994_write(0x204, 0x0019);
- wm8994_write(0x211, 0x0003);
- wm8994_write(0x244, 0x0c83);
- wm8994_write(0x620, 0x0000);
- #endif
- #ifdef THINKWILL_M800_MODE
- wm8994_write(0x310, 0x4118); ///0x4118); ///interface dsp mode 16bit
- #endif
- wm8994_write(0x313, 0x00F0);
- wm8994_write(0x314, 0x0020);
- wm8994_write(0x315, 0x0020);
- wm8994_write(0x603, 0x018c); ///0x000C); //Rev.D ADCL SideTone
- wm8994_write(0x604, 0x0010); //XX
- wm8994_write(0x605, 0x0010); //XX
- wm8994_write(0x621, 0x0000); //0x0001); ///0x0000);
- wm8994_write(0x317, 0x0003);
- wm8994_write(0x312, 0x0000); /// as slave ///0x4000); //AIF2 SET AS MASTER
-
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
-}
+ for (i = 0; i < WM8994_EQ_REGS; i++)
+ snd_soc_update_bits(codec, base + i, 0xffff,
+ pdata->retune_mobile_cfgs[best].regs[i]);
-void handsetMIC_to_baseband_to_headset_and_record(void) //pcmbaseband
-{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset_and_record)return;
- wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset_and_record;
- wm8994_reset();
- msleep(50);
-
- wm8994_write(0x01, 0x0003|wm8994_mic_VCC);
- msleep(50);
- wm8994_write(0x221, 0x0700); //MCLK=12MHz
- wm8994_write(0x222, 0x3127);
- wm8994_write(0x223, 0x0100);
- wm8994_write(0x220, 0x0004);
- msleep(50);
- wm8994_write(0x220, 0x0005);
-
- wm8994_write(0x01, 0x0303|wm8994_mic_VCC);
- wm8994_write(0x02, 0x0240);
- wm8994_write(0x03, 0x0030);
- wm8994_write(0x04, 0x3003);
- wm8994_write(0x05, 0x3003);
- wm8994_write(0x18, 0x010B); // 0x011F=+30dB for MIC
- wm8994_write(0x28, 0x0030);
- wm8994_write(0x29, 0x0020);
- wm8994_write(0x2D, 0x0100);
- wm8994_write(0x2E, 0x0100);
- wm8994_write(0x4C, 0x9F25);
- wm8994_write(0x60, 0x00EE);
- wm8994_write(0x200, 0x0001);
- wm8994_write(0x204, 0x0001);
- wm8994_write(0x208, 0x0007);
- wm8994_write(0x520, 0x0000);
- wm8994_write(0x601, 0x0004);
- wm8994_write(0x602, 0x0004);
-
- wm8994_write(0x610, 0x01C0); //DAC1 Left Volume bit0~7
- wm8994_write(0x611, 0x01C0); //DAC1 Right Volume bit0~7
- wm8994_write(0x612, 0x01C0); //DAC2 Left Volume bit0~7
- wm8994_write(0x613, 0x01C0); //DAC2 Right Volume bit0~7
-
- wm8994_write(0x700, 0x8141); //SYNC issue, AIF1 ADCLRC1 from LRCK1
- wm8994_write(0x702, 0xC100);
- wm8994_write(0x703, 0xC100);
- wm8994_write(0x704, 0xC100);
- wm8994_write(0x706, 0x4100);
- wm8994_write(0x204, 0x0011); //AIF2 MCLK=FLL1
- wm8994_write(0x211, 0x0009); //LRCK=8KHz, Rate=MCLK/1536
- wm8994_write(0x310, 0x4118); //DSP/PCM 16bits
- wm8994_write(0x313, 0x00F0);
- wm8994_write(0x314, 0x0020);
- wm8994_write(0x315, 0x0020);
-
- wm8994_write(0x603, 0x018c); ///0x000C); //Rev.D ADCL SideTone
- wm8994_write(0x604, 0x0010);
- wm8994_write(0x605, 0x0010);
- wm8994_write(0x621, 0x0000);
- //wm8994_write(0x317, 0x0003);
- //wm8994_write(0x312, 0x4000); //AIF2 SET AS MASTER
-////AIF1
- wm8994_write(0x04, 0x3303);
- wm8994_write(0x200, 0x0001);
- wm8994_write(0x208, 0x000F);
- wm8994_write(0x210, 0x0009); //LRCK=8KHz, Rate=MCLK/1536
- wm8994_write(0x300, 0x0118); //DSP/PCM 16bits, R ADC = L ADC
- wm8994_write(0x606, 0x0003);
- wm8994_write(0x607, 0x0003);
-
-////AIF1 Master Clock(SR=8KHz)
- wm8994_write(0x200, 0x0011);
- wm8994_write(0x302, 0x4000);
- wm8994_write(0x303, 0x00F0);
- wm8994_write(0x304, 0x0020);
- wm8994_write(0x305, 0x0020);
-
-////AIF1 DAC1 HP
- wm8994_write(0x05, 0x3303);
- wm8994_write(0x420, 0x0000);
- wm8994_write(0x601, 0x0001);
- wm8994_write(0x602, 0x0001);
- wm8994_write(0x700, 0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
-
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
+ snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
}
-void mainMIC_to_baseband_to_earpiece(void) //pcmbaseband
+/* Icky as hell but saves code duplication */
+static int wm8994_get_retune_mobile_block(const char *name)
{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece)return;
- wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece;
- wm8994_reset();
- msleep(50);
-
- wm8994_write(0x01, 0x0003|wm8994_mic_VCC);
- msleep(50);
- wm8994_write(0x221, 0x0700); //MCLK=12MHz
- wm8994_write(0x222, 0x3127);
- wm8994_write(0x223, 0x0100);
- wm8994_write(0x220, 0x0004);
- msleep(50);
- wm8994_write(0x220, 0x0005);
-
- wm8994_write(0x01, 0x0803|wm8994_mic_VCC); ///0x0813);
- wm8994_write(0x02, 0x0240); ///0x0110);
- wm8994_write(0x03, 0x00F0);
- wm8994_write(0x04, 0x3003);
- wm8994_write(0x05, 0x3003);
- wm8994_write(0x18, 0x011F);
- wm8994_write(0x1F, 0x0000);
- wm8994_write(0x28, 0x0030); ///0x0003);
- wm8994_write(0x29, 0x0020);
- wm8994_write(0x2D, 0x0001);
- wm8994_write(0x2E, 0x0001);
- wm8994_write(0x33, 0x0018);
- wm8994_write(0x200, 0x0001);
- wm8994_write(0x204, 0x0001);
- wm8994_write(0x208, 0x0007);
- wm8994_write(0x520, 0x0000);
- wm8994_write(0x601, 0x0004);
- wm8994_write(0x602, 0x0004);
-
- wm8994_write(0x610, 0x01C0); //DAC1 Left Volume bit0~7
- wm8994_write(0x611, 0x01C0); //DAC1 Right Volume bit0~7
- wm8994_write(0x612, 0x01C0); //DAC2 Left Volume bit0~7
- wm8994_write(0x613, 0x01C0); //DAC2 Right Volume bit0~7
-
- wm8994_write(0x702, 0xC100);
- wm8994_write(0x703, 0xC100);
- wm8994_write(0x704, 0xC100);
- wm8994_write(0x706, 0x4100);
- wm8994_write(0x204, 0x0011); //AIF2 MCLK=FLL1
- wm8994_write(0x211, 0x0009); //LRCK=8KHz, Rate=MCLK/1536
- #ifdef TD688_MODE
- wm8994_write(0x310, 0x4108); ///0x4118); ///interface dsp mode 16bit
- #endif
- #ifdef CHONGY_MODE
- wm8994_write(0x310, 0x4118); ///0x4118); ///interface dsp mode 16bit
- #endif
- #ifdef MU301_MODE
- wm8994_write(0x310, 0x4118); ///0x4118); ///interface dsp mode 16bit
- wm8994_write(0x241, 0x2f04);
- wm8994_write(0x242, 0x0000);
- wm8994_write(0x243, 0x0300);
- wm8994_write(0x240, 0x0004);
- msleep(40);
- wm8994_write(0x240, 0x0005);
- wm8994_write(0x204, 0x0019);
- wm8994_write(0x211, 0x0003);
- wm8994_write(0x244, 0x0c83);
- wm8994_write(0x620, 0x0000);
- #endif
- #ifdef THINKWILL_M800_MODE
- wm8994_write(0x310, 0x4118); ///0x4118); ///interface dsp mode 16bit
- #endif
- wm8994_write(0x313, 0x00F0);
- wm8994_write(0x314, 0x0020);
- wm8994_write(0x315, 0x0020);
-
- wm8994_write(0x603, 0x018C); //Rev.D ADCL SideTone
- wm8994_write(0x604, 0x0010);
- wm8994_write(0x605, 0x0010);
- wm8994_write(0x621, 0x0000); ///0x0001);
- wm8994_write(0x317, 0x0003);
- wm8994_write(0x312, 0x0000); //AIF2 SET AS MASTER
-
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
+ if (strcmp(name, "AIF1.1 EQ Mode") == 0)
+ return 0;
+ if (strcmp(name, "AIF1.2 EQ Mode") == 0)
+ return 1;
+ if (strcmp(name, "AIF2 EQ Mode") == 0)
+ return 2;
+ return -EINVAL;
}
-void mainMIC_to_baseband_to_earpiece_and_record(void) //pcmbaseband
+static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece_and_record)return;
- wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece_and_record;
- wm8994_reset();
- msleep(50);
-
- wm8994_write(0x01, 0x0003|wm8994_mic_VCC);
- msleep(50);
- wm8994_write(0x221, 0x0700); //MCLK=12MHz
- wm8994_write(0x222, 0x3127);
- wm8994_write(0x223, 0x0100);
- wm8994_write(0x220, 0x0004);
- msleep(50);
- wm8994_write(0x220, 0x0005);
-
- wm8994_write(0x01, 0x0803|wm8994_mic_VCC);
- wm8994_write(0x02, 0x0110);
- wm8994_write(0x03, 0x00F0);
- wm8994_write(0x04, 0x3003);
- wm8994_write(0x05, 0x3003);
- wm8994_write(0x1A, 0x010B);
- wm8994_write(0x1F, 0x0000);
- wm8994_write(0x28, 0x0003);
- wm8994_write(0x2A, 0x0020);
- wm8994_write(0x2D, 0x0001);
- wm8994_write(0x2E, 0x0001);
- wm8994_write(0x33, 0x0018);
- wm8994_write(0x200, 0x0001);
- wm8994_write(0x204, 0x0001);
- wm8994_write(0x208, 0x0007);
- wm8994_write(0x520, 0x0000);
- wm8994_write(0x601, 0x0004);
- wm8994_write(0x602, 0x0004);
-
- wm8994_write(0x610, 0x01C0); //DAC1 Left Volume bit0~7
- wm8994_write(0x611, 0x01C0); //DAC1 Right Volume bit0~7
- wm8994_write(0x612, 0x01C0); //DAC2 Left Volume bit0~7
- wm8994_write(0x613, 0x01C0); //DAC2 Right Volume bit0~7
-
- wm8994_write(0x702, 0xC100);
- wm8994_write(0x703, 0xC100);
- wm8994_write(0x704, 0xC100);
- wm8994_write(0x706, 0x4100);
- wm8994_write(0x204, 0x0011); //AIF2 MCLK=FLL1
- wm8994_write(0x211, 0x0009); //LRCK=8KHz, Rate=MCLK/1536
- wm8994_write(0x310, 0x4118); //DSP/PCM 16bits
- wm8994_write(0x313, 0x00F0);
- wm8994_write(0x314, 0x0020);
- wm8994_write(0x315, 0x0020);
-
- wm8994_write(0x603, 0x018C); //Rev.D ADCL SideTone
- wm8994_write(0x604, 0x0010);
- wm8994_write(0x605, 0x0010);
- wm8994_write(0x621, 0x0001);
-
-////AIF1
- wm8994_write(0x04, 0x3303);
- wm8994_write(0x200, 0x0001);
- wm8994_write(0x208, 0x000F);
- wm8994_write(0x210, 0x0009); //LRCK=8KHz, Rate=MCLK/1536
- wm8994_write(0x300, 0xC118); //DSP/PCM 16bits, R ADC = L ADC
- wm8994_write(0x606, 0x0003);
- wm8994_write(0x607, 0x0003);
-
-////AIF1 Master Clock(SR=8KHz)
- wm8994_write(0x200, 0x0011);
- wm8994_write(0x302, 0x4000);
- wm8994_write(0x303, 0x00F0);
- wm8994_write(0x304, 0x0020);
- wm8994_write(0x305, 0x0020);
-
-////AIF1 DAC1 HP
- wm8994_write(0x05, 0x3303);
- wm8994_write(0x420, 0x0000);
- wm8994_write(0x601, 0x0001);
- wm8994_write(0x602, 0x0001);
- wm8994_write(0x700, 0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
-
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
-}
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct wm8994_priv *wm8994 = codec->private_data;
+ struct wm8994_pdata *pdata = wm8994->pdata;
+ int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
+ int value = ucontrol->value.integer.value[0];
-void mainMIC_to_baseband_to_speakers(void) //pcmbaseband
-{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers)return;
- wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers;
- wm8994_reset();
- msleep(50);
-
- wm8994_write(0x01, 0x0003|wm8994_mic_VCC); //0x0013);
- msleep(50);
- wm8994_write(0x221, 0x0700); //MCLK=12MHz //FLL1 CONTRLO(2)
- wm8994_write(0x222, 0x3127); //FLL1 CONTRLO(3)
- wm8994_write(0x223, 0x0100); //FLL1 CONTRLO(4)
- wm8994_write(0x220, 0x0004); //FLL1 CONTRLO(1)
- msleep(50);
- wm8994_write(0x220, 0x0005); //FLL1 CONTRLO(1)
-
- wm8994_write(0x01, 0x3003|wm8994_mic_VCC);
- wm8994_write(0x02, 0x0110);
- wm8994_write(0x03, 0x0030); ///0x0330);
- wm8994_write(0x04, 0x3003);
- wm8994_write(0x05, 0x3003);
- wm8994_write(0x1A, 0x011F);
- wm8994_write(0x22, 0x0000);
- wm8994_write(0x23, 0x0100); ///0x0000);
- wm8994_write(0x25, 0x0152);
- wm8994_write(0x28, 0x0003);
- wm8994_write(0x2A, 0x0020);
- wm8994_write(0x2D, 0x0001);
- wm8994_write(0x2E, 0x0001);
- wm8994_write(0x36, 0x000C); //MIXOUTL_TO_SPKMIXL MIXOUTR_TO_SPKMIXR
- wm8994_write(0x200, 0x0001); //AIF1 CLOCKING(1)
- wm8994_write(0x204, 0x0001); //AIF2 CLOCKING(1)
- wm8994_write(0x208, 0x0007); //CLOCKING(1)
- wm8994_write(0x520, 0x0000); //AIF2 DAC FILTERS(1)
- wm8994_write(0x601, 0x0004); //AIF2DACL_DAC1L
- wm8994_write(0x602, 0x0004); //AIF2DACR_DAC1R
-
- wm8994_write(0x610, 0x01C0); //DAC1 Left Volume bit0~7
- wm8994_write(0x611, 0x01C0); //DAC1 Right Volume bit0~7
- wm8994_write(0x612, 0x01C0); //DAC2 Left Volume bit0~7
- wm8994_write(0x613, 0x01C0); //DAC2 Right Volume bit0~7
-
- wm8994_write(0x702, 0xC100); //GPIO3
- wm8994_write(0x703, 0xC100); //GPIO4
- wm8994_write(0x704, 0xC100); //GPIO5
- wm8994_write(0x706, 0x4100); //GPIO7
- wm8994_write(0x204, 0x0011); //AIF2 MCLK=FLL1
- wm8994_write(0x211, 0x0009); //LRCK=8KHz, Rate=MCLK/1536
- #ifdef TD688_MODE
- wm8994_write(0x310, 0xc108); ///0x4118); ///interface dsp mode 16bit
- #endif
- #ifdef CHONGY_MODE
- wm8994_write(0x310, 0xc018); ///0x4118); ///interface dsp mode 16bit
- #endif
- #ifdef MU301_MODE
- wm8994_write(0x310, 0xc118); ///0x4118); ///interface dsp mode 16bit
- wm8994_write(0x241, 0x2f04);
- wm8994_write(0x242, 0x0000);
- wm8994_write(0x243, 0x0300);
- wm8994_write(0x240, 0x0004);
- msleep(40);
- wm8994_write(0x240, 0x0005);
- wm8994_write(0x204, 0x0019);
- wm8994_write(0x211, 0x0003);
- wm8994_write(0x244, 0x0c83);
- wm8994_write(0x620, 0x0000);
- #endif
- #ifdef THINKWILL_M800_MODE
- wm8994_write(0x310, 0xc118); ///0x4118); ///interface dsp mode 16bit
- #endif
- wm8994_write(0x313, 0x00F0); //AIF2BCLK
- wm8994_write(0x314, 0x0020); //AIF2ADCLRCK
- wm8994_write(0x315, 0x0020); //AIF2DACLRCLK
-
- wm8994_write(0x603, 0x018C); //Rev.D ADCL SideTone
- wm8994_write(0x604, 0x0020); ///0x0010); //ADC2_TO_DAC2L
- wm8994_write(0x605, 0x0020); //0x0010); //ADC2_TO_DAC2R
- wm8994_write(0x621, 0x0000); ///0x0001);
- wm8994_write(0x317, 0x0003);
- wm8994_write(0x312, 0x0000); //AIF2 SET AS MASTER
-
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
-}
+ if (block < 0)
+ return block;
-void mainMIC_to_baseband_to_speakers_and_record(void) //pcmbaseband
-{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers_and_record)return;
- wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers_and_record;
- wm8994_reset();
- msleep(50);
-
- wm8994_write(0x01, 0x0003|wm8994_mic_VCC);
- msleep(50);
- wm8994_write(0x221, 0x0700); //MCLK=12MHz
- wm8994_write(0x222, 0x3127);
- wm8994_write(0x223, 0x0100);
- wm8994_write(0x220, 0x0004);
- msleep(50);
- wm8994_write(0x220, 0x0005);
-
- wm8994_write(0x02, 0x0110);
- wm8994_write(0x03, 0x0330);
- wm8994_write(0x04, 0x3003);
- wm8994_write(0x05, 0x3003);
- wm8994_write(0x1A, 0x010B);
- wm8994_write(0x22, 0x0000);
- wm8994_write(0x23, 0x0000);
- wm8994_write(0x28, 0x0003);
- wm8994_write(0x2A, 0x0020);
- wm8994_write(0x2D, 0x0001);
- wm8994_write(0x2E, 0x0001);
- wm8994_write(0x36, 0x000C);
- wm8994_write(0x200, 0x0001);
- wm8994_write(0x204, 0x0001);
- wm8994_write(0x208, 0x0007);
- wm8994_write(0x520, 0x0000);
- wm8994_write(0x601, 0x0004);
- wm8994_write(0x602, 0x0004);
-
- wm8994_write(0x610, 0x01C0); //DAC1 Left Volume bit0~7
- wm8994_write(0x611, 0x01C0); //DAC1 Right Volume bit0~7
- wm8994_write(0x612, 0x01C0); //DAC2 Left Volume bit0~7
- wm8994_write(0x613, 0x01C0); //DAC2 Right Volume bit0~7
-
- wm8994_write(0x700, 0x8141);
- wm8994_write(0x702, 0xC100);
- wm8994_write(0x703, 0xC100);
- wm8994_write(0x704, 0xC100);
- wm8994_write(0x706, 0x4100);
- wm8994_write(0x204, 0x0011); //AIF2 MCLK=FLL1
- wm8994_write(0x211, 0x0009); //LRCK=8KHz, Rate=MCLK/1536
- wm8994_write(0x310, 0x4118); //DSP/PCM 16bits
- wm8994_write(0x313, 0x00F0);
- wm8994_write(0x314, 0x0020);
- wm8994_write(0x315, 0x0020);
-
- wm8994_write(0x603, 0x018C); //Rev.D ADCL SideTone
- wm8994_write(0x604, 0x0010);
- wm8994_write(0x605, 0x0010);
- wm8994_write(0x621, 0x0001);
-
-////AIF1
- wm8994_write(0x04, 0x3303);
- wm8994_write(0x200, 0x0001);
- wm8994_write(0x208, 0x000F);
- wm8994_write(0x210, 0x0009); //LRCK=8KHz, Rate=MCLK/1536
- wm8994_write(0x300, 0xC118); //DSP/PCM 16bits, R ADC = L ADC
- wm8994_write(0x606, 0x0003);
- wm8994_write(0x607, 0x0003);
-
-////AIF1 Master Clock(SR=8KHz)
- wm8994_write(0x200, 0x0011);
- wm8994_write(0x302, 0x4000);
- wm8994_write(0x303, 0x00F0);
- wm8994_write(0x304, 0x0020);
- wm8994_write(0x305, 0x0020);
-
-////AIF1 DAC1 HP
- wm8994_write(0x05, 0x3303);
- wm8994_write(0x420, 0x0000);
- wm8994_write(0x601, 0x0001);
- wm8994_write(0x602, 0x0001);
- wm8994_write(0x700, 0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
-
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
-}
+ if (value >= pdata->num_retune_mobile_cfgs)
+ return -EINVAL;
-void BT_baseband(void) //pcmbaseband
-{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_BT_baseband)return;
- wm8994_current_mode=wm8994_BT_baseband;
- wm8994_reset();
- msleep(50);
-
- wm8994_write(0x01 ,0x0003);
- msleep (50);
-
- wm8994_write(0x200 ,0x0001);
- wm8994_write(0x221 ,0x0700);//MCLK=12MHz
- wm8994_write(0x222 ,0x3127);
- wm8994_write(0x223 ,0x0100);
- wm8994_write(0x220 ,0x0004);
- msleep (50);
- wm8994_write(0x220 ,0x0005);
-
- wm8994_write(0x02 ,0x0000);
- wm8994_write(0x200 ,0x0011);// AIF1 MCLK=FLL1
- wm8994_write(0x210 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
- wm8994_write(0x300 ,0x4018);// DSP/PCM 16bits
-
- wm8994_write(0x204 ,0x0011);// AIF2 MCLK=FLL1
- wm8994_write(0x211 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
- wm8994_write(0x310 ,0x4118);// DSP/PCM 16bits
- wm8994_write(0x208 ,0x000F);
-
-/////AIF1
- wm8994_write(0x700 ,0x8101);
-/////AIF2
- wm8994_write(0x702 ,0xC100);
- wm8994_write(0x703 ,0xC100);
- wm8994_write(0x704 ,0xC100);
- wm8994_write(0x706 ,0x4100);
-/////AIF3
- wm8994_write(0x707 ,0xA100);
- wm8994_write(0x708 ,0xA100);
- wm8994_write(0x709 ,0xA100);
- wm8994_write(0x70A ,0xA100);
-
- wm8994_write(0x06 ,0x0001);
-
- wm8994_write(0x02 ,0x0300);
- wm8994_write(0x03 ,0x0030);
- wm8994_write(0x04 ,0x3301);//ADCL off
- wm8994_write(0x05 ,0x3301);//DACL off
-
- wm8994_write(0x2A ,0x0005);
-
- wm8994_write(0x313 ,0x00F0);
- wm8994_write(0x314 ,0x0020);
- wm8994_write(0x315 ,0x0020);
-
- wm8994_write(0x2E ,0x0001);
- wm8994_write(0x420 ,0x0000);
- wm8994_write(0x520 ,0x0000);
- wm8994_write(0x601 ,0x0001);
- wm8994_write(0x602 ,0x0001);
- wm8994_write(0x604 ,0x0001);
- wm8994_write(0x605 ,0x0001);
- wm8994_write(0x607 ,0x0002);
- wm8994_write(0x611, 0x01C0); //DAC1 Right Volume bit0~7
- wm8994_write(0x612, 0x01C0); //DAC2 Left Volume bit0~7
- wm8994_write(0x613, 0x01C0); //DAC2 Right Volume bit0~7
-
-
- wm8994_write(0x312 ,0x4000);
-
- wm8994_write(0x606 ,0x0001);
- wm8994_write(0x607 ,0x0003);//R channel for data mix/CPU record data
-
-
-////////////HP output test
- wm8994_write(0x01 ,0x0303);
- wm8994_write(0x4C ,0x9F25);
- wm8994_write(0x60 ,0x00EE);
-///////////end HP test
-
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
+ wm8994->retune_mobile_cfg[block] = value;
+
+ wm8994_set_retune_mobile(codec, block);
+
+ return 0;
}
-void BT_baseband_and_record(void) //pcmbaseband
+static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
{
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
-
- if(wm8994_current_mode==wm8994_BT_baseband_and_record)return;
- wm8994_current_mode=wm8994_BT_baseband_and_record;
- wm8994_reset();
- msleep(50);
-
- wm8994_write(0x01 ,0x0003);
- msleep (50);
-
- wm8994_write(0x200 ,0x0001);
- wm8994_write(0x221 ,0x0700);//MCLK=12MHz
- wm8994_write(0x222 ,0x3127);
- wm8994_write(0x223 ,0x0100);
- wm8994_write(0x220 ,0x0004);
- msleep (50);
- wm8994_write(0x220 ,0x0005);
-
- wm8994_write(0x02 ,0x0000);
- wm8994_write(0x200 ,0x0011);// AIF1 MCLK=FLL1
- wm8994_write(0x210 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
- wm8994_write(0x300 ,0x4018);// DSP/PCM 16bits
-
- wm8994_write(0x204 ,0x0011);// AIF2 MCLK=FLL1
- wm8994_write(0x211 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
- wm8994_write(0x310 ,0x4118);// DSP/PCM 16bits
- wm8994_write(0x208 ,0x000F);
-
-/////AIF1
- wm8994_write(0x700 ,0x8101);
-/////AIF2
- wm8994_write(0x702 ,0xC100);
- wm8994_write(0x703 ,0xC100);
- wm8994_write(0x704 ,0xC100);
- wm8994_write(0x706 ,0x4100);
-/////AIF3
- wm8994_write(0x707 ,0xA100);
- wm8994_write(0x708 ,0xA100);
- wm8994_write(0x709 ,0xA100);
- wm8994_write(0x70A ,0xA100);
-
- wm8994_write(0x06 ,0x0001);
- wm8994_write(0x02 ,0x0300);
- wm8994_write(0x03 ,0x0030);
- wm8994_write(0x04 ,0x3301);//ADCL off
- wm8994_write(0x05 ,0x3301);//DACL off
- wm8994_write(0x2A ,0x0005);
-
- wm8994_write(0x313 ,0x00F0);
- wm8994_write(0x314 ,0x0020);
- wm8994_write(0x315 ,0x0020);
-
- wm8994_write(0x2E ,0x0001);
- wm8994_write(0x420 ,0x0000);
- wm8994_write(0x520 ,0x0000);
- wm8994_write(0x602 ,0x0001);
- wm8994_write(0x604 ,0x0001);
- wm8994_write(0x605 ,0x0001);
- wm8994_write(0x607 ,0x0002);
- wm8994_write(0x611, 0x01C0); //DAC1 Right Volume bit0~7
- wm8994_write(0x612, 0x01C0); //DAC2 Left Volume bit0~7
- wm8994_write(0x613, 0x01C0); //DAC2 Right Volume bit0~7
-
- wm8994_write(0x312 ,0x4000);
-
- wm8994_write(0x606 ,0x0001);
- wm8994_write(0x607 ,0x0003);//R channel for data mix/CPU record data
-////////////HP output test
- wm8994_write(0x01 ,0x0303);
- wm8994_write(0x4C ,0x9F25);
- wm8994_write(0x60 ,0x00EE);
-///////////end HP test
-
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct wm8994_priv *wm8994 = codec->private_data;
+ int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
+
+ ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
+
+ return 0;
}
-#endif //PCM_BB
-
-
-typedef void (wm8994_codec_fnc_t) (void);
-
-wm8994_codec_fnc_t *wm8994_codec_sequence[] = {
- AP_to_headset,
- AP_to_speakers,
- recorder_and_AP_to_headset,
- recorder_and_AP_to_speakers,
- FM_to_headset,
- FM_to_headset_and_record,
- FM_to_speakers,
- FM_to_speakers_and_record,
- handsetMIC_to_baseband_to_headset,
- handsetMIC_to_baseband_to_headset_and_record,
- mainMIC_to_baseband_to_earpiece,
- mainMIC_to_baseband_to_earpiece_and_record,
- mainMIC_to_baseband_to_speakers,
- mainMIC_to_baseband_to_speakers_and_record,
- BT_baseband,
- BT_baseband_and_record,
+
+static const struct snd_kcontrol_new wm8994_snd_controls[] = {
+
+SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
+ WM8994_AIF1_ADC1_RIGHT_VOLUME,
+ 1, 119, 0, digital_tlv),
+SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
+ WM8994_AIF1_ADC2_RIGHT_VOLUME,
+ 1, 119, 0, digital_tlv),
+SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
+ WM8994_AIF2_ADC_RIGHT_VOLUME,
+ 1, 119, 0, digital_tlv),
+
+SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
+ WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
+SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
+ WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
+SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
+ WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
+
+SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
+SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
+
+SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
+SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
+SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
+
+WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
+WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
+WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
+
+WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
+WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
+WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
+
+WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
+WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
+WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
+
+SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
+ 5, 12, 0, st_tlv),
+SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
+ 0, 12, 0, st_tlv),
+SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
+ 5, 12, 0, st_tlv),
+SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
+ 0, 12, 0, st_tlv),
+SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
+SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
+
+SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
+ WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
+SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
+ WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
+
+SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
+ WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
+SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
+ WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
+
+SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
+ 6, 1, 1, wm_hubs_spkmix_tlv),
+SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
+ 2, 1, 1, wm_hubs_spkmix_tlv),
+
+SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
+ 6, 1, 1, wm_hubs_spkmix_tlv),
+SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
+ 2, 1, 1, wm_hubs_spkmix_tlv),
+
+SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
+ 10, 15, 0, wm8994_3d_tlv),
+SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
+ 8, 1, 0),
+SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
+ 10, 15, 0, wm8994_3d_tlv),
+SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
+ 8, 1, 0),
+SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
+ 10, 15, 0, wm8994_3d_tlv),
+SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
+ 8, 1, 0),
};
-/********************set wm8994 volume*****volume=0\1\2\3\4\5\6\7*******************/
+static const struct snd_kcontrol_new wm8994_eq_controls[] = {
+SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
+ eq_tlv),
+SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
+ eq_tlv),
+SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
+ eq_tlv),
+SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
+ eq_tlv),
+SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
+ eq_tlv),
+
+SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
+ eq_tlv),
+SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
+ eq_tlv),
+SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
+ eq_tlv),
+SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
+ eq_tlv),
+SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
+ eq_tlv),
+
+SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
+ eq_tlv),
+SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
+ eq_tlv),
+SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
+ eq_tlv),
+SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
+ eq_tlv),
+SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
+ eq_tlv),
+};
-void wm8994_codec_set_volume(unsigned char system_type,unsigned char volume)
+static int clk_sys_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
{
- if(system_type == BLUETOOTH_SCO )
- volume=volume/3;
+ struct snd_soc_codec *codec = w->codec;
- if(system_type == VOICE_CALL||system_type == BLUETOOTH_SCO )
- {
- if(volume<=call_maxvol)
- call_vol=volume;
- else{
- printk("%s----%d::call volume more than max value 7\n",__FUNCTION__,__LINE__);
- call_vol=call_maxvol;
- }
- if(wm8994_current_mode<null&&wm8994_current_mode>=wm8994_handsetMIC_to_baseband_to_headset)
- wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ return configure_clock(codec);
+
+ case SND_SOC_DAPM_POST_PMD:
+ configure_clock(codec);
+ break;
}
- else
- printk("%s----%d::system type error!\n",__FUNCTION__,__LINE__);
+
+ return 0;
}
-void wm8994_set_volume(unsigned char wm8994_mode,unsigned char volume,unsigned char max_volume)
+static void wm8994_update_class_w(struct snd_soc_codec *codec)
{
- unsigned short lvol=0,rvol=0;
- DBG("%s::%d\n",__FUNCTION__,__LINE__);
- if(volume>max_volume)volume=max_volume;
-
- if(wm8994_mode==wm8994_handsetMIC_to_baseband_to_headset_and_record||
- wm8994_mode==wm8994_handsetMIC_to_baseband_to_headset)
- {
- wm8994_read(0x001C, &lvol);
- wm8994_read(0x001D, &rvol);
- //HPOUT1L_VOL bit 0~5 /-57dB to +6dB in 1dB steps
- wm8994_write(0x001C, (lvol&~0x003f)|headset_vol_table[volume]);
- //HPOUT1R_VOL bit 0~5 /-57dB to +6dB in 1dB steps
- wm8994_write(0x001D, (rvol&~0x003f)|headset_vol_table[volume]);
+ int enable = 1;
+ int source = 0; /* GCC flow analysis can't track enable */
+ int reg, reg_r;
+
+ /* Only support direct DAC->headphone paths */
+ reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
+ if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
+ DBG_INFO(codec->dev, "HPL connected to output mixer\n");
+ enable = 0;
}
- else if(wm8994_mode==wm8994_mainMIC_to_baseband_to_speakers_and_record||
- wm8994_mode==wm8994_mainMIC_to_baseband_to_speakers||
- wm8994_mode==wm8994_mainMIC_to_baseband_with_AP_to_speakers)
- {
- wm8994_read(0x0026, &lvol);
- wm8994_read(0x0027, &rvol);
- //SPKOUTL_VOL bit 0~5 /-57dB to +6dB in 1dB steps
- wm8994_write(0x0026, (lvol&~0x003f)|speakers_vol_table[volume]);
- //SPKOUTR_VOL bit 0~5 /-57dB to +6dB in 1dB steps
- wm8994_write(0x0027, (rvol&~0x003f)|speakers_vol_table[volume]);
+
+ reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
+ if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
+ DBG_INFO(codec->dev, "HPR connected to output mixer\n");
+ enable = 0;
}
- else if(wm8994_mode==wm8994_mainMIC_to_baseband_to_earpiece||
- wm8994_mode==wm8994_mainMIC_to_baseband_to_earpiece_and_record)
- {
- wm8994_read(0x0020, &lvol);
- wm8994_read(0x0021, &rvol);
- //MIXOUTL_VOL bit 0~5 /-57dB to +6dB in 1dB steps
- wm8994_write(0x0020, (lvol&~0x003f)|earpiece_vol_table[volume]);
- //MIXOUTR_VOL bit 0~5 /-57dB to +6dB in 1dB steps
- wm8994_write(0x0021, (rvol&~0x003f)|earpiece_vol_table[volume]);
+ /* We also need the same setting for L/R and only one path */
+ reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
+ switch (reg) {
+ case WM8994_AIF2DACL_TO_DAC1L:
+ DBG_INFO(codec->dev, "Class W source AIF2DAC\n");
+ source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
+ break;
+ case WM8994_AIF1DAC2L_TO_DAC1L:
+ DBG_INFO(codec->dev, "Class W source AIF1DAC2\n");
+ source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
+ break;
+ case WM8994_AIF1DAC1L_TO_DAC1L:
+ DBG_INFO(codec->dev, "Class W source AIF1DAC1\n");
+ source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
+ break;
+ default:
+ DBG_INFO(codec->dev, "DAC mixer setting: %x\n", reg);
+ enable = 0;
+ break;
}
- else if(wm8994_mode==wm8994_BT_baseband||wm8994_mode==wm8994_BT_baseband_and_record)
- {
- //bit 0~4 /-16.5dB to +30dB in 1.5dB steps
- wm8994_write(0x0019, (0x0400&~0x000f)|BT_vol_table[volume]);
+
+ reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
+ if (reg_r != reg) {
+ DBG_INFO(codec->dev, "Left and right DAC mixers different\n");
+ enable = 0;
+ }
+
+ if (enable) {
+ DBG_INFO(codec->dev, "Class W enabled\n");
+ snd_soc_update_bits(codec, WM8994_CLASS_W_1,
+ WM8994_CP_DYN_PWR |
+ WM8994_CP_DYN_SRC_SEL_MASK,
+ source | WM8994_CP_DYN_PWR);
+
+ } else {
+ DBG_INFO(codec->dev, "Class W disabled\n");
+ snd_soc_update_bits(codec, WM8994_CLASS_W_1,
+ WM8994_CP_DYN_PWR, 0);
}
}
-#define SOC_DOUBLE_SWITCH_WM8994CODEC(xname, route) \
-{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
- .info = snd_soc_info_route, \
- .get = snd_soc_get_route, .put = snd_soc_put_route, \
- .private_value = route }
+static const char *hp_mux_text[] = {
+ "Mixer",
+ "DAC",
+};
-int snd_soc_info_route(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_info *uinfo)
+//--------------------------------------------------------------------------------
+//WM8994_HP_ENUM
+//--------------------------------------------------------------------------------
+#define WM8994_HP_ENUM(xname, xenum) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+ .info = snd_soc_info_enum_double, \
+ .get = snd_soc_dapm_get_enum_double, \
+ .put = wm8994_put_hp_enum, \
+ .private_value = (unsigned long)&xenum }
+
+static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
{
- uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+ struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_codec *codec = w->codec;
+ int ret;
- uinfo->count = 1;
- uinfo->value.integer.min = 0;
- uinfo->value.integer.max = 0;
- return 0;
-}
+ ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
-int snd_soc_get_route(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_value *ucontrol)
-{
- return 0;
+ wm8994_update_class_w(codec);
+
+ return ret;
}
-int snd_soc_put_route(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_value *ucontrol)
-{
- int route = kcontrol->private_value & 0xff;
+static const struct soc_enum hpl_enum =
+ SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
- switch(route)
- {
- /* Speaker*/
- case SPEAKER_NORMAL: //AP-> 8994Codec -> Speaker
- recorder_and_AP_to_speakers();
- break;
+static const struct snd_kcontrol_new hpl_mux =
+ WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
- case SPEAKER_INCALL: //BB-> 8994Codec -> Speaker
- mainMIC_to_baseband_to_speakers();
- break;
-
- /* Headset */
- case HEADSET_NORMAL: //AP-> 8994Codec -> Headset
- recorder_and_AP_to_headset();
- break;
- case HEADSET_INCALL: //AP-> 8994Codec -> Headset
- handsetMIC_to_baseband_to_headset();
- break;
-
- /* Earpiece*/
- case EARPIECE_INCALL: //:BB-> 8994Codec -> EARPIECE
-#ifdef CONFIG_SND_NO_EARPIECE
- mainMIC_to_baseband_to_speakers();
-#else
- mainMIC_to_baseband_to_earpiece();
-#endif
- break;
+static const struct soc_enum hpr_enum =
+ SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
- case EARPIECE_NORMAL: //:BB-> 8994Codec -> EARPIECE
- if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset)
- recorder_and_AP_to_headset();
- else if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers||
- wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece)
- recorder_and_AP_to_speakers();
- else if(wm8994_current_mode==wm8994_recorder_and_AP_to_speakers||
- wm8994_current_mode==wm8994_recorder_and_AP_to_speakers)
- break;
- else{
- recorder_and_AP_to_speakers();
- printk("%s--%d--: wm8994 with null mode\n",__FUNCTION__,__LINE__);
- }
- break;
+static const struct snd_kcontrol_new hpr_mux =
+ WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
+static const char *adc_mux_text[] = {
+ "ADC",
+ "DMIC",
+};
- /* BLUETOOTH_SCO*/
- case BLUETOOTH_SCO_INCALL: //BB-> 8994Codec -> BLUETOOTH_SCO
- BT_baseband();
- break;
+static const struct soc_enum adc_enum =
+ SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
- /* BLUETOOTH_A2DP*/
- case BLUETOOTH_A2DP_NORMAL: //AP-> 8994Codec -> BLUETOOTH_A2DP
- break;
-
- case MIC_CAPTURE:
- if(wm8994_current_mode==wm8994_AP_to_headset)
- recorder_and_AP_to_headset();
- else if(wm8994_current_mode==wm8994_AP_to_speakers)
- recorder_and_AP_to_speakers();
- else if(wm8994_current_mode==wm8994_recorder_and_AP_to_speakers||
- wm8994_current_mode==wm8994_recorder_and_AP_to_headset)
- break;
- else{
- recorder_and_AP_to_speakers();
- printk("%s--%d--: wm8994 with null mode\n",__FUNCTION__,__LINE__);
- }
- break;
+static const struct snd_kcontrol_new adcl_mux =
+ SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
- case EARPIECE_RINGTONE:
- AP_to_speakers();
- break;
+static const struct snd_kcontrol_new adcr_mux =
+ SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
- case HEADSET_RINGTONE:
- AP_to_headset();
- break;
+static const struct snd_kcontrol_new left_speaker_mixer[] = {
+SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
+SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
+SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
+SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
+SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
+};
- case SPEAKER_RINGTONE:
- AP_to_speakers();
- break;
+static const struct snd_kcontrol_new right_speaker_mixer[] = {
+SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
+SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
+SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
+SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
+SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
+};
- default:
- //codec_daout_route();
- break;
- }
+/* Debugging; dump chip status after DAPM transitions */
+static int post_ev(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ DBG_INFO(codec->dev, "SRC status: %x\n",
+ snd_soc_read(codec, WM8994_RATE_STATUS));
+
return 0;
}
-/*
- * WM8994 Controls
- */
-static const char *bass_boost_txt[] = {"Linear Control", "Adaptive Boost"};
-static const struct soc_enum bass_boost =
- SOC_ENUM_SINGLE(WM8994_BASS, 7, 2, bass_boost_txt);
+static const struct snd_kcontrol_new aif1adc1l_mix[] = {
+SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
+ 1, 1, 0),
+SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
+ 0, 1, 0),
+};
-static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
-static const struct soc_enum bass_filter =
- SOC_ENUM_SINGLE(WM8994_BASS, 6, 2, bass_filter_txt);
+static const struct snd_kcontrol_new aif1adc1r_mix[] = {
+SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
+ 1, 1, 0),
+SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
+ 0, 1, 0),
+};
-static const char *treble_txt[] = {"8kHz", "4kHz"};
-static const struct soc_enum treble =
- SOC_ENUM_SINGLE(WM8994_TREBLE, 6, 2, treble_txt);
+static const struct snd_kcontrol_new aif2dac2l_mix[] = {
+SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
+ 5, 1, 0),
+SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
+ 4, 1, 0),
+SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
+ 2, 1, 0),
+SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
+ 1, 1, 0),
+SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
+ 0, 1, 0),
+};
-static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
-static const struct soc_enum stereo_3d_lc =
- SOC_ENUM_SINGLE(WM8994_3D, 5, 2, stereo_3d_lc_txt);
+static const struct snd_kcontrol_new aif2dac2r_mix[] = {
+SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
+ 5, 1, 0),
+SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
+ 4, 1, 0),
+SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
+ 2, 1, 0),
+SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
+ 1, 1, 0),
+SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
+ 0, 1, 0),
+};
-static const char *stereo_3d_uc_txt[] = {"2.2kHz", "1.5kHz"};
-static const struct soc_enum stereo_3d_uc =
- SOC_ENUM_SINGLE(WM8994_3D, 6, 2, stereo_3d_uc_txt);
+//--------------------------------------------------------------------------------
+//WM8994_CLASS_W_SWITCH
+//--------------------------------------------------------------------------------
+#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+ .info = snd_soc_info_volsw, \
+ .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
+ .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
+
+static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_codec *codec = w->codec;
+ int ret;
-static const char *stereo_3d_func_txt[] = {"Capture", "Playback"};
-static const struct soc_enum stereo_3d_func =
- SOC_ENUM_SINGLE(WM8994_3D, 7, 2, stereo_3d_func_txt);
+ ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
-static const char *alc_func_txt[] = {"Off", "Right", "Left", "Stereo"};
-static const struct soc_enum alc_func =
- SOC_ENUM_SINGLE(WM8994_ALC1, 7, 4, alc_func_txt);
+ wm8994_update_class_w(codec);
-static const char *ng_type_txt[] = {"Constant PGA Gain",
- "Mute ADC Output"};
-static const struct soc_enum ng_type =
- SOC_ENUM_SINGLE(WM8994_NGATE, 1, 2, ng_type_txt);
+ return ret;
+}
-static const char *deemph_txt[] = {"None", "32Khz", "44.1Khz", "48Khz"};
-static const struct soc_enum deemph =
- SOC_ENUM_SINGLE(WM8994_ADCDAC, 1, 4, deemph_txt);
+static const struct snd_kcontrol_new dac1l_mix[] = {
+WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
+ 5, 1, 0),
+WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
+ 4, 1, 0),
+WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
+ 2, 1, 0),
+WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
+ 1, 1, 0),
+WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
+ 0, 1, 0),
+};
-static const char *adcpol_txt[] = {"Normal", "L Invert", "R Invert",
- "L + R Invert"};
-static const struct soc_enum adcpol =
- SOC_ENUM_SINGLE(WM8994_ADCDAC, 5, 4, adcpol_txt);
+static const struct snd_kcontrol_new dac1r_mix[] = {
+WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
+ 5, 1, 0),
+WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
+ 4, 1, 0),
+WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
+ 2, 1, 0),
+WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
+ 1, 1, 0),
+WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
+ 0, 1, 0),
+};
-static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
-static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
-static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
-static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
-static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
+static const char *sidetone_text[] = {
+ "ADC/DMIC1", "DMIC2",
+};
-static const struct snd_kcontrol_new wm8994_snd_controls[] = {
+static const struct soc_enum sidetone1_enum =
+ SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
-SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker incall Switch", SPEAKER_INCALL),
-SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker normal Switch", SPEAKER_NORMAL),
+static const struct snd_kcontrol_new sidetone1_mux =
+ SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
-SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece incall Switch", EARPIECE_INCALL),
-SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece normal Switch", EARPIECE_NORMAL),
+static const struct soc_enum sidetone2_enum =
+ SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
-SOC_DOUBLE_SWITCH_WM8994CODEC("Headset incall Switch", HEADSET_INCALL),
-SOC_DOUBLE_SWITCH_WM8994CODEC("Headset normal Switch", HEADSET_NORMAL),
+static const struct snd_kcontrol_new sidetone2_mux =
+ SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
-SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth incall Switch", BLUETOOTH_SCO_INCALL),
-SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth normal Switch", BLUETOOTH_SCO_NORMAL),
+static const char *aif1dac_text[] = {
+ "AIF1DACDAT", "AIF3DACDAT",
+};
-SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth-A2DP incall Switch", BLUETOOTH_A2DP_INCALL),
-SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth-A2DP normal Switch", BLUETOOTH_A2DP_NORMAL),
+static const struct soc_enum aif1dac_enum =
+ SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
-SOC_DOUBLE_SWITCH_WM8994CODEC("Capture Switch", MIC_CAPTURE),
+static const struct snd_kcontrol_new aif1dac_mux =
+ SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
-SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece ringtone Switch",EARPIECE_RINGTONE),
-SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker ringtone Switch",SPEAKER_RINGTONE),
-SOC_DOUBLE_SWITCH_WM8994CODEC("Headset ringtone Switch",HEADSET_RINGTONE),
+static const char *aif2dac_text[] = {
+ "AIF2DACDAT", "AIF3DACDAT",
};
-/*
- * DAPM Controls
- */
+static const struct soc_enum aif2dac_enum =
+ SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
-static int wm8994_lrc_control(struct snd_soc_dapm_widget *w,
- struct snd_kcontrol *kcontrol, int event)
-{
- return 0;
-}
+static const struct snd_kcontrol_new aif2dac_mux =
+ SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
-static const char *wm8994_line_texts[] = {
- "Line 1", "Line 2", "PGA", "Differential"};
-
-static const unsigned int wm8994_line_values[] = {
- 0, 1, 3, 4};
-
-static const struct soc_enum wm8994_lline_enum =
- SOC_VALUE_ENUM_SINGLE(WM8994_LOUTM1, 0, 7,
- ARRAY_SIZE(wm8994_line_texts),
- wm8994_line_texts,
- wm8994_line_values);
-static const struct snd_kcontrol_new wm8994_left_line_controls =
- SOC_DAPM_VALUE_ENUM("Route", wm8994_lline_enum);
-
-static const struct soc_enum wm8994_rline_enum =
- SOC_VALUE_ENUM_SINGLE(WM8994_ROUTM1, 0, 7,
- ARRAY_SIZE(wm8994_line_texts),
- wm8994_line_texts,
- wm8994_line_values);
-static const struct snd_kcontrol_new wm8994_right_line_controls =
- SOC_DAPM_VALUE_ENUM("Route", wm8994_lline_enum);
-
-/* Left Mixer */
-static const struct snd_kcontrol_new wm8994_left_mixer_controls[] = {
- SOC_DAPM_SINGLE("Playback Switch", WM8994_LOUTM1, 8, 1, 0),
- SOC_DAPM_SINGLE("Left Bypass Switch", WM8994_LOUTM1, 7, 1, 0),
- SOC_DAPM_SINGLE("Right Playback Switch", WM8994_LOUTM2, 8, 1, 0),
- SOC_DAPM_SINGLE("Right Bypass Switch", WM8994_LOUTM2, 7, 1, 0),
+static const char *aif2adc_text[] = {
+ "AIF2ADCDAT", "AIF3DACDAT",
};
-/* Right Mixer */
-static const struct snd_kcontrol_new wm8994_right_mixer_controls[] = {
- SOC_DAPM_SINGLE("Left Playback Switch", WM8994_ROUTM1, 8, 1, 0),
- SOC_DAPM_SINGLE("Left Bypass Switch", WM8994_ROUTM1, 7, 1, 0),
- SOC_DAPM_SINGLE("Playback Switch", WM8994_ROUTM2, 8, 1, 0),
- SOC_DAPM_SINGLE("Right Bypass Switch", WM8994_ROUTM2, 7, 1, 0),
+static const struct soc_enum aif2adc_enum =
+ SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
+
+static const struct snd_kcontrol_new aif2adc_mux =
+ SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
+
+static const char *aif3adc_text[] = {
+ "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT",
};
-static const char *wm8994_pga_sel[] = {"Line 1", "Line 2", "Differential"};
-static const unsigned int wm8994_pga_val[] = { 0, 1, 3 };
-
-/* Left PGA Mux */
-static const struct soc_enum wm8994_lpga_enum =
- SOC_VALUE_ENUM_SINGLE(WM8994_LADCIN, 6, 3,
- ARRAY_SIZE(wm8994_pga_sel),
- wm8994_pga_sel,
- wm8994_pga_val);
-static const struct snd_kcontrol_new wm8994_left_pga_controls =
- SOC_DAPM_VALUE_ENUM("Route", wm8994_lpga_enum);
-
-/* Right PGA Mux */
-static const struct soc_enum wm8994_rpga_enum =
- SOC_VALUE_ENUM_SINGLE(WM8994_RADCIN, 6, 3,
- ARRAY_SIZE(wm8994_pga_sel),
- wm8994_pga_sel,
- wm8994_pga_val);
-static const struct snd_kcontrol_new wm8994_right_pga_controls =
- SOC_DAPM_VALUE_ENUM("Route", wm8994_rpga_enum);
-
-/* Differential Mux */
-static const char *wm8994_diff_sel[] = {"Line 1", "Line 2"};
-static const struct soc_enum diffmux =
- SOC_ENUM_SINGLE(WM8994_ADCIN, 8, 2, wm8994_diff_sel);
-static const struct snd_kcontrol_new wm8994_diffmux_controls =
- SOC_DAPM_ENUM("Route", diffmux);
-
-/* Mono ADC Mux */
-static const char *wm8994_mono_mux[] = {"Stereo", "Mono (Left)",
- "Mono (Right)", "Digital Mono"};
-static const struct soc_enum monomux =
- SOC_ENUM_SINGLE(WM8994_ADCIN, 6, 4, wm8994_mono_mux);
-static const struct snd_kcontrol_new wm8994_monomux_controls =
- SOC_DAPM_ENUM("Route", monomux);
+static const struct soc_enum aif3adc_enum =
+ SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
+
+static const struct snd_kcontrol_new aif3adc_mux =
+ SOC_DAPM_ENUM("AIF3ADC Mux", aif3adc_enum);
static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
- SND_SOC_DAPM_MICBIAS("Mic Bias", WM8994_PWR1, 1, 0),
-
- SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
- &wm8994_diffmux_controls),
- SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
- &wm8994_monomux_controls),
- SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
- &wm8994_monomux_controls),
-
- SND_SOC_DAPM_MUX("Left PGA Mux", WM8994_PWR1, 5, 0,
- &wm8994_left_pga_controls),
- SND_SOC_DAPM_MUX("Right PGA Mux", WM8994_PWR1, 4, 0,
- &wm8994_right_pga_controls),
-
- SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
- &wm8994_left_line_controls),
- SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
- &wm8994_right_line_controls),
-
- SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8994_PWR1, 2, 0),
- SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8994_PWR1, 3, 0),
-
- SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8994_PWR2, 7, 0),
- SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8994_PWR2, 8, 0),
-
- SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
- &wm8994_left_mixer_controls[0],
- ARRAY_SIZE(wm8994_left_mixer_controls)),
- SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
- &wm8994_right_mixer_controls[0],
- ARRAY_SIZE(wm8994_right_mixer_controls)),
-
- SND_SOC_DAPM_PGA("Right Out 2", WM8994_PWR2, 3, 0, NULL, 0),
- SND_SOC_DAPM_PGA("Left Out 2", WM8994_PWR2, 4, 0, NULL, 0),
- SND_SOC_DAPM_PGA("Right Out 1", WM8994_PWR2, 5, 0, NULL, 0),
- SND_SOC_DAPM_PGA("Left Out 1", WM8994_PWR2, 6, 0, NULL, 0),
-
- SND_SOC_DAPM_POST("LRC control", wm8994_lrc_control),
-
- SND_SOC_DAPM_OUTPUT("LOUT1"),
- SND_SOC_DAPM_OUTPUT("ROUT1"),
- SND_SOC_DAPM_OUTPUT("LOUT2"),
- SND_SOC_DAPM_OUTPUT("ROUT2"),
- SND_SOC_DAPM_OUTPUT("VREF"),
-
- SND_SOC_DAPM_INPUT("LINPUT1"),
- SND_SOC_DAPM_INPUT("LINPUT2"),
- SND_SOC_DAPM_INPUT("RINPUT1"),
- SND_SOC_DAPM_INPUT("RINPUT2"),
-};
-static const struct snd_soc_dapm_route audio_map[] = {
-
- { "Left Line Mux", "Line 1", "LINPUT1" },
- { "Left Line Mux", "Line 2", "LINPUT2" },
- { "Left Line Mux", "PGA", "Left PGA Mux" },
- { "Left Line Mux", "Differential", "Differential Mux" },
-
- { "Right Line Mux", "Line 1", "RINPUT1" },
- { "Right Line Mux", "Line 2", "RINPUT2" },
- { "Right Line Mux", "PGA", "Right PGA Mux" },
- { "Right Line Mux", "Differential", "Differential Mux" },
-
- { "Left PGA Mux", "Line 1", "LINPUT1" },
- { "Left PGA Mux", "Line 2", "LINPUT2" },
- { "Left PGA Mux", "Differential", "Differential Mux" },
-
- { "Right PGA Mux", "Line 1", "RINPUT1" },
- { "Right PGA Mux", "Line 2", "RINPUT2" },
- { "Right PGA Mux", "Differential", "Differential Mux" },
-
- { "Differential Mux", "Line 1", "LINPUT1" },
- { "Differential Mux", "Line 1", "RINPUT1" },
- { "Differential Mux", "Line 2", "LINPUT2" },
- { "Differential Mux", "Line 2", "RINPUT2" },
-
- { "Left ADC Mux", "Stereo", "Left PGA Mux" },
- { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
- { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
-
- { "Right ADC Mux", "Stereo", "Right PGA Mux" },
- { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
- { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
-
- { "Left ADC", NULL, "Left ADC Mux" },
- { "Right ADC", NULL, "Right ADC Mux" },
-
- { "Left Line Mux", "Line 1", "LINPUT1" },
- { "Left Line Mux", "Line 2", "LINPUT2" },
- { "Left Line Mux", "PGA", "Left PGA Mux" },
- { "Left Line Mux", "Differential", "Differential Mux" },
-
- { "Right Line Mux", "Line 1", "RINPUT1" },
- { "Right Line Mux", "Line 2", "RINPUT2" },
- { "Right Line Mux", "PGA", "Right PGA Mux" },
- { "Right Line Mux", "Differential", "Differential Mux" },
-
- { "Left Mixer", "Playback Switch", "Left DAC" },
- { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
- { "Left Mixer", "Right Playback Switch", "Right DAC" },
- { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
-
- { "Right Mixer", "Left Playback Switch", "Left DAC" },
- { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
- { "Right Mixer", "Playback Switch", "Right DAC" },
- { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
-
- { "Left Out 1", NULL, "Left Mixer" },
- { "LOUT1", NULL, "Left Out 1" },
- { "Right Out 1", NULL, "Right Mixer" },
- { "ROUT1", NULL, "Right Out 1" },
-
- { "Left Out 2", NULL, "Left Mixer" },
- { "LOUT2", NULL, "Left Out 2" },
- { "Right Out 2", NULL, "Right Mixer" },
- { "ROUT2", NULL, "Right Out 2" },
-};
+SND_SOC_DAPM_INPUT("DMIC1DAT"),
+SND_SOC_DAPM_INPUT("DMIC2DAT"),
+
+SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+
+SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
+
+SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
+
+SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
+ 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
+SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
+ 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
+SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0,
+ WM8994_POWER_MANAGEMENT_5, 9, 0),
+SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0,
+ WM8994_POWER_MANAGEMENT_5, 8, 0),
+
+SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
+ 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
+SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
+ 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
+SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0,
+ WM8994_POWER_MANAGEMENT_5, 11, 0),
+SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0,
+ WM8994_POWER_MANAGEMENT_5, 10, 0),
+
+SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
+ aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
+SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
+ aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
+
+SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
+ aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
+SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
+ aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
+
+SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
+SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
+
+SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
+ dac1l_mix, ARRAY_SIZE(dac1l_mix)),
+SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
+ dac1r_mix, ARRAY_SIZE(dac1r_mix)),
+
+SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
+ WM8994_POWER_MANAGEMENT_4, 13, 0),
+SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
+ WM8994_POWER_MANAGEMENT_4, 12, 0),
+SND_SOC_DAPM_AIF_IN("AIF2DACL", NULL, 0,
+ WM8994_POWER_MANAGEMENT_5, 13, 0),
+SND_SOC_DAPM_AIF_IN("AIF2DACR", NULL, 0,
+ WM8994_POWER_MANAGEMENT_5, 12, 0),
+
+SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
+SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
+SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
+
+SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
+SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
+SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
+SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &aif3adc_mux),
+
+SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
+SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
+
+SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
+
+SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
+SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
+SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
+SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
+
+/* Power is done with the muxes since the ADC power also controls the
+ * downsampling chain, the chip will automatically manage the analogue
+ * specific portions.
+ */
+SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
+SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
+
+SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
+SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
+
+SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
+SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
+SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
+SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
+
+SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
+SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
+
+SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
+ left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
+SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
+ right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
-struct _coeff_div {
- u32 mclk;
- u32 rate;
- u16 fs;
- u8 sr:5;
- u8 usb:1;
+SND_SOC_DAPM_POST("Debug log", post_ev),
};
-/* codec hifi mclk clock divider coefficients */
-static const struct _coeff_div coeff_div[] = {
- /* 8k */
- {12288000, 8000, 1536, 0x6, 0x0},
- {11289600, 8000, 1408, 0x16, 0x0},
- {18432000, 8000, 2304, 0x7, 0x0},
- {16934400, 8000, 2112, 0x17, 0x0},
- {12000000, 8000, 1500, 0x6, 0x1},
-
- /* 11.025k */
- {11289600, 11025, 1024, 0x18, 0x0},
- {16934400, 11025, 1536, 0x19, 0x0},
- {12000000, 11025, 1088, 0x19, 0x1},
-
- /* 16k */
- {12288000, 16000, 768, 0xa, 0x0},
- {18432000, 16000, 1152, 0xb, 0x0},
- {12000000, 16000, 750, 0xa, 0x1},
-
- /* 22.05k */
- {11289600, 22050, 512, 0x1a, 0x0},
- {16934400, 22050, 768, 0x1b, 0x0},
- {12000000, 22050, 544, 0x1b, 0x1},
-
- /* 32k */
- {12288000, 32000, 384, 0xc, 0x0},
- {18432000, 32000, 576, 0xd, 0x0},
- {12000000, 32000, 375, 0xa, 0x1},
-
- /* 44.1k */
- {11289600, 44100, 256, 0x10, 0x0},
- {16934400, 44100, 384, 0x11, 0x0},
- {12000000, 44100, 272, 0x11, 0x1},
-
- /* 48k */
- {12288000, 48000, 256, 0x0, 0x0},
- {18432000, 48000, 384, 0x1, 0x0},
- {12000000, 48000, 250, 0x0, 0x1},
-
- /* 88.2k */
- {11289600, 88200, 128, 0x1e, 0x0},
- {16934400, 88200, 192, 0x1f, 0x0},
- {12000000, 88200, 136, 0x1f, 0x1},
-
- /* 96k */
- {12288000, 96000, 128, 0xe, 0x0},
- {18432000, 96000, 192, 0xf, 0x0},
- {12000000, 96000, 125, 0xe, 0x1},
+static const struct snd_soc_dapm_route intercon[] = {
+ { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
+ { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
+
+ { "DSP1CLK", NULL, "CLK_SYS" },
+ { "DSP2CLK", NULL, "CLK_SYS" },
+ { "DSPINTCLK", NULL, "CLK_SYS" },
+
+ { "AIF1ADC1L", NULL, "AIF1CLK" },
+ { "AIF1ADC1L", NULL, "DSP1CLK" },
+ { "AIF1ADC1R", NULL, "AIF1CLK" },
+ { "AIF1ADC1R", NULL, "DSP1CLK" },
+ { "AIF1ADC1R", NULL, "DSPINTCLK" },
+
+ { "AIF1DAC1L", NULL, "AIF1CLK" },
+ { "AIF1DAC1L", NULL, "DSP1CLK" },
+ { "AIF1DAC1R", NULL, "AIF1CLK" },
+ { "AIF1DAC1R", NULL, "DSP1CLK" },
+ { "AIF1DAC1R", NULL, "DSPINTCLK" },
+
+ { "AIF1ADC2L", NULL, "AIF1CLK" },
+ { "AIF1ADC2L", NULL, "DSP1CLK" },
+ { "AIF1ADC2R", NULL, "AIF1CLK" },
+ { "AIF1ADC2R", NULL, "DSP1CLK" },
+ { "AIF1ADC2R", NULL, "DSPINTCLK" },
+
+ { "AIF1DAC2L", NULL, "AIF1CLK" },
+ { "AIF1DAC2L", NULL, "DSP1CLK" },
+ { "AIF1DAC2R", NULL, "AIF1CLK" },
+ { "AIF1DAC2R", NULL, "DSP1CLK" },
+ { "AIF1DAC2R", NULL, "DSPINTCLK" },
+
+ { "AIF2ADCL", NULL, "AIF2CLK" },
+ { "AIF2ADCL", NULL, "DSP2CLK" },
+ { "AIF2ADCR", NULL, "AIF2CLK" },
+ { "AIF2ADCR", NULL, "DSP2CLK" },
+ { "AIF2ADCR", NULL, "DSPINTCLK" },
+
+ { "AIF2DACL", NULL, "AIF2CLK" },
+ { "AIF2DACL", NULL, "DSP2CLK" },
+ { "AIF2DACR", NULL, "AIF2CLK" },
+ { "AIF2DACR", NULL, "DSP2CLK" },
+ { "AIF2DACR", NULL, "DSPINTCLK" },
+
+ { "DMIC1L", NULL, "DMIC1DAT" },
+ { "DMIC1L", NULL, "CLK_SYS" },
+ { "DMIC1R", NULL, "DMIC1DAT" },
+ { "DMIC1R", NULL, "CLK_SYS" },
+ { "DMIC2L", NULL, "DMIC2DAT" },
+ { "DMIC2L", NULL, "CLK_SYS" },
+ { "DMIC2R", NULL, "DMIC2DAT" },
+ { "DMIC2R", NULL, "CLK_SYS" },
+
+ { "ADCL", NULL, "AIF1CLK" },
+ { "ADCL", NULL, "DSP1CLK" },
+ { "ADCL", NULL, "DSPINTCLK" },
+
+ { "ADCR", NULL, "AIF1CLK" },
+ { "ADCR", NULL, "DSP1CLK" },
+ { "ADCR", NULL, "DSPINTCLK" },
+
+ { "ADCL Mux", "ADC", "ADCL" },
+ { "ADCL Mux", "DMIC", "DMIC1L" },
+ { "ADCR Mux", "ADC", "ADCR" },
+ { "ADCR Mux", "DMIC", "DMIC1R" },
+
+ { "DAC1L", NULL, "AIF1CLK" },
+ { "DAC1L", NULL, "DSP1CLK" },
+ { "DAC1L", NULL, "DSPINTCLK" },
+
+ { "DAC1R", NULL, "AIF1CLK" },
+ { "DAC1R", NULL, "DSP1CLK" },
+ { "DAC1R", NULL, "DSPINTCLK" },
+
+ { "DAC2L", NULL, "AIF2CLK" },
+ { "DAC2L", NULL, "DSP2CLK" },
+ { "DAC2L", NULL, "DSPINTCLK" },
+
+ { "DAC2R", NULL, "AIF2DACR" },
+ { "DAC2R", NULL, "AIF2CLK" },
+ { "DAC2R", NULL, "DSP2CLK" },
+ { "DAC2R", NULL, "DSPINTCLK" },
+
+ { "TOCLK", NULL, "CLK_SYS" },
+
+ /* AIF1 outputs */
+ { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
+ { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
+ { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
+
+ { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
+ { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
+ { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
+
+ /* Pin level routing for AIF3 */
+ { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
+ { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
+ { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
+ { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
+
+ { "AIF2DACL", NULL, "AIF2DAC Mux" },
+ { "AIF2DACR", NULL, "AIF2DAC Mux" },
+
+ { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
+ { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
+ { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
+ { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
+ { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
+ { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
+ { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
+
+ /* DAC1 inputs */
+ { "DAC1L", NULL, "DAC1L Mixer" },
+ { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
+ { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
+ { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
+ { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
+ { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
+
+ { "DAC1R", NULL, "DAC1R Mixer" },
+ { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
+ { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
+ { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
+ { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
+ { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
+
+ /* DAC2/AIF2 outputs */
+ { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
+ { "DAC2L", NULL, "AIF2DAC2L Mixer" },
+ { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
+ { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
+ { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
+ { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
+ { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
+
+ { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
+ { "DAC2R", NULL, "AIF2DAC2R Mixer" },
+ { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
+ { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
+ { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
+ { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
+ { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
+
+ { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
+
+ /* AIF3 output */
+ { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
+ { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
+ { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
+ { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
+ { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
+ { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
+ { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
+ { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
+
+ /* Sidetone */
+ { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
+ { "Left Sidetone", "DMIC2", "DMIC2L" },
+ { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
+ { "Right Sidetone", "DMIC2", "DMIC2R" },
+
+ /* Output stages */
+ { "Left Output Mixer", "DAC Switch", "DAC1L" },
+ { "Right Output Mixer", "DAC Switch", "DAC1R" },
+
+ { "SPKL", "DAC1 Switch", "DAC1L" },
+ { "SPKL", "DAC2 Switch", "DAC2L" },
+
+ { "SPKR", "DAC1 Switch", "DAC1R" },
+ { "SPKR", "DAC2 Switch", "DAC2R" },
+
+ { "Left Headphone Mux", "DAC", "DAC1L" },
+ { "Right Headphone Mux", "DAC", "DAC1R" },
};
+/* The size in bits of the FLL divide multiplied by 10
+ * to allow rounding later */
+#define FIXED_FLL_SIZE ((1 << 16) * 10)
-static inline int get_coeff(int mclk, int rate)
+struct fll_div {
+ u16 outdiv;
+ u16 n;
+ u16 k;
+ u16 clk_ref_div;
+ u16 fll_fratio;
+};
+
+static int wm8994_get_fll_config(struct fll_div *fll,
+ int freq_in, int freq_out)
{
- int i;
+ u64 Kpart;
+ unsigned int K, Ndiv, Nmod;
+
+ DBG_CLK("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
- for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
- if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
- return i;
+ /* Scale the input frequency down to <= 13.5MHz */
+ fll->clk_ref_div = 0;
+ while (freq_in > 13500000) {
+ fll->clk_ref_div++;
+ freq_in /= 2;
+
+ if (fll->clk_ref_div > 3)
+ return -EINVAL;
+ }
+ DBG_CLK("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
+
+ /* Scale the output to give 90MHz<=Fvco<=100MHz */
+ fll->outdiv = 3;
+ while (freq_out * (fll->outdiv + 1) < 90000000) {
+ fll->outdiv++;
+ if (fll->outdiv > 63)
+ return -EINVAL;
}
+ freq_out *= fll->outdiv + 1;
+ DBG_CLK("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
+
+ if (freq_in > 1000000) {
+ fll->fll_fratio = 0;
+ } else {
+ fll->fll_fratio = 3;
+ freq_in *= 8;
+ }
+ DBG_CLK("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
- return -EINVAL;
-}
+ /* Now, calculate N.K */
+ Ndiv = freq_out / freq_in;
-/* The set of rates we can generate from the above for each SYSCLK */
+ fll->n = Ndiv;
+ Nmod = freq_out % freq_in;
+ DBG_CLK("Nmod=%d\n", Nmod);
-static unsigned int rates_12288[] = {
- 8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
-};
+ /* Calculate fractional part - scale up so we can round. */
+ Kpart = FIXED_FLL_SIZE * (long long)Nmod;
-static struct snd_pcm_hw_constraint_list constraints_12288 = {
- .count = ARRAY_SIZE(rates_12288),
- .list = rates_12288,
-};
+ do_div(Kpart, freq_in);
-static unsigned int rates_112896[] = {
- 8000, 11025, 22050, 44100,
-};
+ K = Kpart & 0xFFFFFFFF;
-static struct snd_pcm_hw_constraint_list constraints_112896 = {
- .count = ARRAY_SIZE(rates_112896),
- .list = rates_112896,
-};
+ if ((K % 10) >= 5)
+ K += 5;
-static unsigned int rates_12[] = {
- 8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000,
- 48000, 88235, 96000,
-};
+ /* Move down to proper range now rounding is done */
+ fll->k = K / 10;
-static struct snd_pcm_hw_constraint_list constraints_12 = {
- .count = ARRAY_SIZE(rates_12),
- .list = rates_12,
-};
+ DBG_CLK("N=%x K=%x\n", fll->n, fll->k);
-/*
- * Note that this should be called from init rather than from hw_params.
- */
-static int wm8994_set_dai_sysclk(struct snd_soc_dai *codec_dai,
- int clk_id, unsigned int freq, int dir)
+ return 0;
+}
+
+//static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
+// unsigned int freq_in, unsigned int freq_out)
+static int wm8994_set_fll(struct snd_soc_dai *dai, int id,
+ unsigned int freq_in, unsigned int freq_out)
{
- struct snd_soc_codec *codec = codec_dai->codec;
+ struct snd_soc_codec *codec = dai->codec;
struct wm8994_priv *wm8994 = codec->private_data;
-
- DBG("%s----%d\n",__FUNCTION__,__LINE__);
-
- switch (freq) {
- case 11289600:
- case 18432000:
- case 22579200:
- case 36864000:
- wm8994->sysclk_constraints = &constraints_112896;
- wm8994->sysclk = freq;
- return 0;
+ int reg_offset, ret;
+ struct fll_div fll;
+ u16 reg, aif1, aif2;
+// DBG("Enter %s::%s---%d\n",__FILE__,__FUNCTION__,__LINE__);
+ aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)//0x200
+ & WM8994_AIF1CLK_ENA;
+
+ aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
+ & WM8994_AIF2CLK_ENA;
+
+ switch (id) {
+ case WM8994_FLL1:
+ reg_offset = 0;
+ id = 0;
+ break;
+ case WM8994_FLL2:
+ reg_offset = 0x20;
+ id = 1;
+ break;
+ default:
+ return -EINVAL;
+ }
- case 12288000:
- case 16934400:
- case 24576000:
- case 33868800:
- wm8994->sysclk_constraints = &constraints_12288;
- wm8994->sysclk = freq;
+ /* Are we changing anything? wm8994->fll[id].src == src && */
+ if ( wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
return 0;
- case 12000000:
- case 24000000:
- wm8994->sysclk_constraints = &constraints_12;
- wm8994->sysclk = freq;
- return 0;
+ /* If we're stopping the FLL redo the old config - no
+ * registers will actually be written but we avoid GCC flow
+ * analysis bugs spewing warnings.
+ */
+ if (freq_out)
+ ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
+ else
+ ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
+ wm8994->fll[id].out);
+ if (ret < 0)
+ return ret;
+
+ /* Gate the AIF clocks while we reclock */
+ snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
+ WM8994_AIF1CLK_ENA, 0);
+ snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
+ WM8994_AIF2CLK_ENA, 0);
+
+ /* We always need to disable the FLL while reconfiguring */
+ snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, //0x220 ÏȹØFLL
+ WM8994_FLL1_ENA, 0);
+
+ reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
+ (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
+ snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,//0x221 DIV
+ WM8994_FLL1_OUTDIV_MASK |
+ WM8994_FLL1_FRATIO_MASK, reg);
+
+ snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);//0x222 K
+
+ snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset, //0x223 N
+ WM8994_FLL1_N_MASK,
+ fll.n << WM8994_FLL1_N_SHIFT);
+
+ snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,//0x224
+ WM8994_FLL1_REFCLK_DIV_MASK,
+ fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT);
+
+ /* Enable (with fractional mode if required) */
+ if (freq_out) {
+ if (fll.k)
+ reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
+ else
+ reg = WM8994_FLL1_ENA;
+ snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,//0x220
+ WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
+ reg);
}
- return -EINVAL;
-}
-static int wm8994_set_dai_fmt(struct snd_soc_dai *codec_dai,
- unsigned int fmt)
-{
+ wm8994->fll[id].in = freq_in;
+ wm8994->fll[id].out = freq_out;
+
+ /* Enable any gated AIF clocks */
+ snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
+ WM8994_AIF1CLK_ENA, aif1);
+ snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
+ WM8994_AIF2CLK_ENA, aif2);
+
+ configure_clock(codec);
+
return 0;
}
-static int wm8994_pcm_startup(struct snd_pcm_substream *substream,
- struct snd_soc_dai *dai)
+static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
+ int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = dai->codec;
struct wm8994_priv *wm8994 = codec->private_data;
-
- /* The set of sample rates that can be supported depends on the
- * MCLK supplied to the CODEC - enforce this.
- */
+// DBG("Enter %s::%s---%d\n",__FILE__,__FUNCTION__,__LINE__);
+ switch (dai->id) {
+ case 1:
+ case 2:
+ break;
+ default:
+ // AIF3 shares clocking with AIF1/2
+ DBG_CLK("ERROR:AIF3 shares clocking with AIF1/2. \n");
+ return -EINVAL;
+ }
+
- if (!wm8994->sysclk) {
- dev_err(codec->dev,
- "No MCLK configured, call set_sysclk() on init\n");
+ switch (clk_id) {
+ case WM8994_SYSCLK_MCLK1:
+ wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
+ wm8994->mclk[0] = freq;
+ DBG_INFO(dai->dev, "AIF%d using MCLK1 at %uHz\n",
+ dai->id, freq);
+ break;
+
+ case WM8994_SYSCLK_MCLK2:
+ //TODO: Set GPIO AF
+ wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
+ wm8994->mclk[1] = freq;
+ DBG_INFO(dai->dev, "AIF%d using MCLK2 at %uHz\n",
+ dai->id, freq);
+ break;
+
+ case WM8994_SYSCLK_FLL1:
+ wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
+ DBG_INFO(dai->dev, "AIF%d using FLL1\n", dai->id);
+ break;
+
+ case WM8994_SYSCLK_FLL2:
+ wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
+ DBG_INFO(dai->dev, "AIF%d using FLL2\n", dai->id);
+ break;
+
+ default:
+ DBG_CLK("ERROR:AIF3 shares clocking with AIF1/2. \n");
return -EINVAL;
}
- snd_pcm_hw_constraint_list(substream->runtime, 0,
- SNDRV_PCM_HW_PARAM_RATE,
- wm8994->sysclk_constraints);
+ configure_clock(codec);
return 0;
}
-static int wm8994_pcm_hw_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params,
- struct snd_soc_dai *dai)
+static int wm8994_set_bias_level(struct snd_soc_codec *codec,
+ enum snd_soc_bias_level level)
{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_soc_device *socdev = rtd->socdev;
- struct snd_soc_codec *codec = socdev->card->codec;
- struct wm8994_priv *wm8994 = codec->private_data;
- int coeff;
-
- coeff = get_coeff(wm8994->sysclk, params_rate(params));
- if (coeff < 0) {
- coeff = get_coeff(wm8994->sysclk / 2, params_rate(params));
+// DBG("Enter %s---%d\n",__FUNCTION__,__LINE__);
+ switch (level) {
+ case SND_SOC_BIAS_ON:
+ break;
+
+ case SND_SOC_BIAS_PREPARE:
+ /* VMID=2x40k */
+ snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
+ WM8994_VMID_SEL_MASK, 0x2);
+ break;
+
+ case SND_SOC_BIAS_STANDBY:
+ if (codec->bias_level == SND_SOC_BIAS_OFF) {
+ /* Tweak DC servo configuration for improved
+ * performance. */
+ snd_soc_write(codec, 0x102, 0x3);
+ snd_soc_write(codec, 0x56, 0x3);
+ snd_soc_write(codec, 0x102, 0);
+
+ /* Discharge LINEOUT1 & 2 */
+ snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
+ WM8994_LINEOUT1_DISCH |
+ WM8994_LINEOUT2_DISCH,
+ WM8994_LINEOUT1_DISCH |
+ WM8994_LINEOUT2_DISCH);
+
+ /* Startup bias, VMID ramp & buffer */
+ snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
+ WM8994_STARTUP_BIAS_ENA |
+ WM8994_VMID_BUF_ENA |
+ WM8994_VMID_RAMP_MASK,
+ WM8994_STARTUP_BIAS_ENA |
+ WM8994_VMID_BUF_ENA |
+ (0x11 << WM8994_VMID_RAMP_SHIFT));
+
+ /* Main bias enable, VMID=2x40k */
+ snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
+ WM8994_BIAS_ENA |
+ WM8994_VMID_SEL_MASK,
+ WM8994_BIAS_ENA | 0x2);
+
+ msleep(20);
+ }
+
+ /* VMID=2x500k */
+ snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
+ WM8994_VMID_SEL_MASK, 0x4);
+
+ break;
+
+ case SND_SOC_BIAS_OFF:
+ if (codec->bias_level == SND_SOC_BIAS_STANDBY) {
+ /* Switch over to startup biases */
+ snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
+ WM8994_BIAS_SRC |
+ WM8994_STARTUP_BIAS_ENA |
+ WM8994_VMID_BUF_ENA |
+ WM8994_VMID_RAMP_MASK,
+ WM8994_BIAS_SRC |
+ WM8994_STARTUP_BIAS_ENA |
+ WM8994_VMID_BUF_ENA |
+ (1 << WM8994_VMID_RAMP_SHIFT));
+
+ /* Disable main biases */
+ snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
+ WM8994_BIAS_ENA |
+ WM8994_VMID_SEL_MASK, 0);
+
+ /* Discharge line */
+ snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
+ WM8994_LINEOUT1_DISCH |
+ WM8994_LINEOUT2_DISCH,
+ WM8994_LINEOUT1_DISCH |
+ WM8994_LINEOUT2_DISCH);
+
+ msleep(5);
+
+ /* Switch off startup biases */
+ snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
+ WM8994_BIAS_SRC |
+ WM8994_STARTUP_BIAS_ENA |
+ WM8994_VMID_BUF_ENA |
+ WM8994_VMID_RAMP_MASK, 0);
+ }
+ break;
}
- if (coeff < 0) {
- dev_err(codec->dev,
- "Unable to configure sample rate %dHz with %dHz MCLK\n",
- params_rate(params), wm8994->sysclk);
- return coeff;
+ codec->bias_level = level;
+ return 0;
+}
+
+//ÉèÖÃmater slave ÒÔ¼°I2Sģʽ
+static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ int ms_reg;
+ int aif1_reg;
+ int ms = 0;
+ int aif1 = 0;
+// DBG("Enter %s---%d\n",__FUNCTION__,__LINE__);
+ switch (dai->id) {
+ case 1:
+ ms_reg = WM8994_AIF1_MASTER_SLAVE;
+ aif1_reg = WM8994_AIF1_CONTROL_1;
+ break;
+ case 2:
+ ms_reg = WM8994_AIF2_MASTER_SLAVE;
+ aif1_reg = WM8994_AIF2_CONTROL_1;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBS_CFS:
+ break;
+ case SND_SOC_DAIFMT_CBM_CFM:
+ // ms = WM8994_AIF1_MSTR;
+ ms = WM8994_AIF1_MSTR|WM8994_AIF1_CLK_FRC|WM8994_AIF1_LRCLK_FRC;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_DSP_B:
+ aif1 |= WM8994_AIF1_LRCLK_INV;
+ case SND_SOC_DAIFMT_DSP_A:
+ aif1 |= 0x18;
+ break;
+ case SND_SOC_DAIFMT_I2S:
+ aif1 |= 0x10;
+ break;
+ case SND_SOC_DAIFMT_RIGHT_J:
+ break;
+ case SND_SOC_DAIFMT_LEFT_J:
+ aif1 |= 0x8;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_DSP_A:
+ case SND_SOC_DAIFMT_DSP_B:
+ /* frame inversion not valid for DSP modes */
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ aif1 |= WM8994_AIF1_BCLK_INV;
+ break;
+ default:
+ return -EINVAL;
+ }
+ break;
+
+ case SND_SOC_DAIFMT_I2S:
+ case SND_SOC_DAIFMT_RIGHT_J:
+ case SND_SOC_DAIFMT_LEFT_J:
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ break;
+ case SND_SOC_DAIFMT_IB_IF:
+ aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ aif1 |= WM8994_AIF1_BCLK_INV;
+ break;
+ case SND_SOC_DAIFMT_NB_IF:
+ aif1 |= WM8994_AIF1_LRCLK_INV;
+ break;
+ default:
+ return -EINVAL;
+ }
+ break;
+ default:
+ return -EINVAL;
}
- params_format(params);
+
+ snd_soc_update_bits(codec, aif1_reg,
+ WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
+ WM8994_AIF1_FMT_MASK,
+ aif1);
+ snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
+ ms);
return 0;
}
-static int wm8994_mute(struct snd_soc_dai *dai, int mute)
+static struct {
+ int val, rate;
+} srs[] = {
+ { 0, 8000 },
+ { 1, 11025 },
+ { 2, 12000 },
+ { 3, 16000 },
+ { 4, 22050 },
+ { 5, 24000 },
+ { 6, 32000 },
+ { 7, 44100 },
+ { 8, 48000 },
+ { 9, 88200 },
+ { 10, 96000 },
+};
+
+static int fs_ratios[] = {
+ 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
+};
+
+static int bclk_divs[] = {
+ 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
+ 640, 880, 960, 1280, 1760, 1920
+};
+
+static int wm8994_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
{
+ struct snd_soc_codec *codec = dai->codec;
+ struct wm8994_priv *wm8994 = codec->private_data;
+ int aif1_reg;
+ int bclk_reg;
+ int lrclk_reg;
+ int rate_reg;
+ int aif1 = 0;
+ int bclk = 0;
+ int lrclk = 0;
+ int rate_val = 0;
+ int id = dai->id - 1;
+
+ int i, cur_val, best_val, bclk_rate, best;
+
+// DBG("Enter %s::%s---%d\n",__FILE__,__FUNCTION__,__LINE__);
+
+ switch (dai->id) {
+ case 1:
+ aif1_reg = WM8994_AIF1_CONTROL_1;
+ bclk_reg = WM8994_AIF1_BCLK;
+ rate_reg = WM8994_AIF1_RATE;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
+ wm8994->lrclk_shared[0])
+ lrclk_reg = WM8994_AIF1DAC_LRCLK;
+ else
+ lrclk_reg = WM8994_AIF1ADC_LRCLK;
+ break;
+ case 2:
+ aif1_reg = WM8994_AIF2_CONTROL_1;
+ bclk_reg = WM8994_AIF2_BCLK;
+ rate_reg = WM8994_AIF2_RATE;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
+ wm8994->lrclk_shared[1])
+ lrclk_reg = WM8994_AIF2DAC_LRCLK;
+ else
+ lrclk_reg = WM8994_AIF2ADC_LRCLK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ bclk_rate = params_rate(params) * 2;
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S16_LE:
+ bclk_rate *= 16;
+ break;
+ case SNDRV_PCM_FORMAT_S20_3LE:
+ bclk_rate *= 20;
+ aif1 |= 0x20;
+ break;
+ case SNDRV_PCM_FORMAT_S24_LE:
+ bclk_rate *= 24;
+ aif1 |= 0x40;
+ break;
+ case SNDRV_PCM_FORMAT_S32_LE:
+ bclk_rate *= 32;
+ aif1 |= 0x60;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ // Try to find an appropriate sample rate; look for an exact match.
+ for (i = 0; i < ARRAY_SIZE(srs); i++)
+ if (srs[i].rate == params_rate(params))
+ break;
+ if (i == ARRAY_SIZE(srs))
+ return -EINVAL;
+ rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
+
+ DBG_INFO(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
+ DBG_INFO(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
+ dai->id, wm8994->aifclk[id], bclk_rate);
+
+ if (wm8994->aifclk[id] == 0) {
+ dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
+ return -EINVAL;
+ }
+
+ /* AIFCLK/fs ratio; look for a close match in either direction */
+ best = 0;
+ best_val = abs((fs_ratios[0] * params_rate(params))
+ - wm8994->aifclk[id]);
+ for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
+ cur_val = abs((fs_ratios[i] * params_rate(params))
+ - wm8994->aifclk[id]);
+ if (cur_val >= best_val)
+ continue;
+ best = i;
+ best_val = cur_val;
+ }
+ DBG_INFO(dai->dev, "Selected AIF%dCLK/fs = %d\n",
+ dai->id, fs_ratios[best]);
+ rate_val |= best;
+
+ // We may not get quite the right frequency if using
+ // approximate clocks so look for the closest match that is
+ // higher than the target (we need to ensure that there enough
+ // BCLKs to clock out the samples).
+ //
+ best = 0;
+ for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
+ cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
+ if (cur_val < 0) // BCLK table is sorted
+ break;
+ best = i;
+ }
+ bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
+ DBG_INFO(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
+ bclk_divs[best], bclk_rate);
+ bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
+
+ lrclk = bclk_rate / params_rate(params);
+ DBG_INFO(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
+ lrclk, bclk_rate / lrclk);
+
+ snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
+ snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
+ snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
+ lrclk);
+ snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
+ WM8994_AIF1CLK_RATE_MASK, rate_val);
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ switch (dai->id) {
+ case 1:
+ wm8994->dac_rates[0] = params_rate(params);
+ wm8994_set_retune_mobile(codec, 0);
+ wm8994_set_retune_mobile(codec, 1);
+ break;
+ case 2:
+ wm8994->dac_rates[1] = params_rate(params);
+ wm8994_set_retune_mobile(codec, 2);
+ break;
+ }
+ }
+
return 0;
}
-static int wm8994_set_bias_level(struct snd_soc_codec *codec,
- enum snd_soc_bias_level level)
+static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
{
+ struct snd_soc_codec *codec = codec_dai->codec;
+ int mute_reg;
+ int reg;
+
+ switch (codec_dai->id) {
+ case 1:
+ mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
+ break;
+ case 2:
+ mute_reg = WM8994_AIF2_DAC_FILTERS_1;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (mute)
+ reg = WM8994_AIF1DAC1_MUTE;
+ else
+ reg = 0;
+
+ snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
- codec->bias_level = level;
return 0;
}
-#define WM8994_RATES SNDRV_PCM_RATE_48000
+#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
- SNDRV_PCM_FMTBIT_S24_LE)
-
-static struct snd_soc_dai_ops wm8994_ops = {
- .startup = wm8994_pcm_startup,
- .hw_params = wm8994_pcm_hw_params,
- .set_fmt = wm8994_set_dai_fmt,
- .set_sysclk = wm8994_set_dai_sysclk,
- .digital_mute = wm8994_mute,
- /*add by qiuen for volume*/
- .set_volume = wm8994_codec_set_volume,
+ SNDRV_PCM_FMTBIT_S24_LE)
+
+//============================================================================================
+//============================================================================================
+//============================================================================================
+static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
+ .set_sysclk = wm8994_set_dai_sysclk,
+ .set_fmt = wm8994_set_dai_fmt,
+ .hw_params = wm8994_hw_params,
+ .digital_mute = wm8994_aif_mute,
+ .set_pll = wm8994_set_fll,
+};
+
+static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
+ .set_sysclk = wm8994_set_dai_sysclk,//ÉèÖÃAIFCLKµÄÀ´Ô´,²¢ÉèÖÃƵÂÊ
+ .set_fmt = wm8994_set_dai_fmt,//ÉèÖÃmaster¡¢slave
+ .hw_params = wm8994_hw_params,//¿ÉÄÜÊÇÉèÖÃbclkºÍLRCK
+ .digital_mute = wm8994_aif_mute,//¾²Òô
+ .set_pll = wm8994_set_fll,//ÉèÖÃFLL
};
-struct snd_soc_dai wm8994_dai = {
- .name = "WM8994",
- .playback = {
- .stream_name = "Playback",
- .channels_min = 1,
- .channels_max = 2,
- .rates = WM8994_RATES,
- .formats = WM8994_FORMATS,
+struct snd_soc_dai wm8994_dai[] = {
+ {
+ .name = "WM8994 AIF1",
+ .id = 1,
+ .playback = {
+ .stream_name = "AIF1 Playback",
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = WM8994_RATES,
+ .formats = WM8994_FORMATS,
+ },
+ .capture = {
+ .stream_name = "AIF1 Capture",
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = WM8994_RATES,
+ .formats = WM8994_FORMATS,
+ },
+ .ops = &wm8994_aif1_dai_ops,
+ },
+ {
+ .name = "WM8994 AIF2",
+ .id = 2,
+ .playback = {
+ .stream_name = "AIF2 Playback",
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = WM8994_RATES,
+ .formats = WM8994_FORMATS,
+ },
+ .capture = {
+ .stream_name = "AIF2 Capture",
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = WM8994_RATES,
+ .formats = WM8994_FORMATS,
+ },
+ .ops = &wm8994_aif2_dai_ops,
},
- .capture = {
- .stream_name = "Capture",
- .channels_min = 2,
- .channels_max = 2,
- .rates = WM8994_RATES,
- .formats = WM8994_FORMATS,
- },
- .ops = &wm8994_ops,
- .symmetric_rates = 1,
+ {
+ .name = "WM8994 AIF3",
+ .playback = {
+ .stream_name = "AIF3 Playback",
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = WM8994_RATES,
+ .formats = WM8994_FORMATS,
+ },
+ .capture = {
+ .stream_name = "AIF3 Capture",
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = WM8994_RATES,
+ .formats = WM8994_FORMATS,
+ },
+ }
};
EXPORT_SYMBOL_GPL(wm8994_dai);
+#ifdef CONFIG_PM
static int wm8994_suspend(struct platform_device *pdev, pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
+ struct wm8994_priv *wm8994 = codec->private_data;
+ int i, ret;
+
+ for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
+ memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
+ sizeof(struct fll_config));
+ // ret = wm8994_set_fll(&codec->dai[0], i + 1, 0, 0, 0);
+ ret = wm8994_set_fll(&codec->dai[0], i + 1, 0, 0);
+ if (ret < 0)
+ dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
+ i + 1, ret);
+ }
+
+ wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
- wm8994_set_bias_level(codec,SND_SOC_BIAS_OFF);
- wm8994_reset();
- msleep(WM8994_DELAY);
return 0;
}
@@ -2708,31 +3510,185 @@ static int wm8994_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
- wm8994_codec_fnc_t **wm8994_fnc_ptr=wm8994_codec_sequence;
- unsigned char wm8994_resume_mode=wm8994_current_mode;
- wm8994_current_mode=null;
+ struct wm8994_priv *wm8994 = codec->private_data;
+ u16 *reg_cache = codec->reg_cache;
+ int i, ret;
+
+ /* Restore the registers */
+ for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) {
+ switch (i) {
+ case WM8994_LDO_1:
+ case WM8994_LDO_2:
+ case WM8994_SOFTWARE_RESET:
+ /* Handled by other MFD drivers */
+ continue;
+ default:
+ break;
+ }
- wm8994_set_bias_level(codec,SND_SOC_BIAS_STANDBY);
- if(wm8994_resume_mode<=wm8994_recorder_and_AP_to_speakers)
- {
- wm8994_fnc_ptr+=wm8994_resume_mode;
- (*wm8994_fnc_ptr)() ;
- }
- else if(wm8994_resume_mode>wm8994_BT_baseband_and_record)
- {
- printk("%s--%d--: Wm8994 resume with null mode\n",__FUNCTION__,__LINE__);
+ if (!access_masks[i].writable)
+ continue;
+
+ wm8994_reg_write(codec->control_data, i, reg_cache[i]);
}
- else
- {
- wm8994_fnc_ptr+=wm8994_resume_mode;
- (*wm8994_fnc_ptr)();
- printk("%s--%d--: Wm8994 resume with error mode\n",__FUNCTION__,__LINE__);
+
+ wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+ for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
+ // ret = wm8994_set_fll(&codec->dai[0], i + 1,
+ // wm8994->fll_suspend[i].src,
+ // wm8994->fll_suspend[i].in,
+ // wm8994->fll_suspend[i].out);
+ ret = wm8994_set_fll(&codec->dai[0], i + 1,
+ wm8994->fll_suspend[i].in,
+ wm8994->fll_suspend[i].out);
+ if (ret < 0)
+ dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
+ i + 1, ret);
}
return 0;
}
+#else
+#define wm8994_suspend NULL
+#define wm8994_resume NULL
+#endif
-static struct snd_soc_codec *wm8994_codec;
+//Ö»µ÷ÓÃÒ»´Î
+static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
+{
+ struct snd_soc_codec *codec = &wm8994->codec;
+ struct wm8994_pdata *pdata = wm8994->pdata;
+ struct snd_kcontrol_new controls[] = {
+ SOC_ENUM_EXT("AIF1.1 EQ Mode",
+ wm8994->retune_mobile_enum,
+ wm8994_get_retune_mobile_enum,
+ wm8994_put_retune_mobile_enum),
+ SOC_ENUM_EXT("AIF1.2 EQ Mode",
+ wm8994->retune_mobile_enum,
+ wm8994_get_retune_mobile_enum,
+ wm8994_put_retune_mobile_enum),
+ SOC_ENUM_EXT("AIF2 EQ Mode",
+ wm8994->retune_mobile_enum,
+ wm8994_get_retune_mobile_enum,
+ wm8994_put_retune_mobile_enum),
+ };
+ int ret, i, j;
+ const char **t;
+
+ /* We need an array of texts for the enum API but the number
+ * of texts is likely to be less than the number of
+ * configurations due to the sample rate dependency of the
+ * configurations. */
+ wm8994->num_retune_mobile_texts = 0;
+ wm8994->retune_mobile_texts = NULL;
+ for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
+ for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
+ if (strcmp(pdata->retune_mobile_cfgs[i].name,
+ wm8994->retune_mobile_texts[j]) == 0)
+ break;
+ }
+
+ if (j != wm8994->num_retune_mobile_texts)
+ continue;
+
+ /* Expand the array... */
+ t = krealloc(wm8994->retune_mobile_texts,
+ sizeof(char *) *
+ (wm8994->num_retune_mobile_texts + 1),
+ GFP_KERNEL);
+ if (t == NULL)
+ continue;
+
+ /* ...store the new entry... */
+ t[wm8994->num_retune_mobile_texts] =
+ pdata->retune_mobile_cfgs[i].name;
+
+ /* ...and remember the new version. */
+ wm8994->num_retune_mobile_texts++;
+ wm8994->retune_mobile_texts = t;
+ }
+
+ DBG_INFO(codec->dev, "Allocated %d unique ReTune Mobile names\n",
+ wm8994->num_retune_mobile_texts);
+
+ wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
+ wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
+
+ ret = snd_soc_add_controls(&wm8994->codec, controls,
+ ARRAY_SIZE(controls));
+ if (ret != 0)
+ dev_err(wm8994->codec.dev,
+ "Failed to add ReTune Mobile controls: %d\n", ret);
+}
+
+static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
+{
+ struct snd_soc_codec *codec = &wm8994->codec;
+ struct wm8994_pdata *pdata = wm8994->pdata;
+ int ret, i;
+
+ if (!pdata)
+ return;
+
+ wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
+ pdata->lineout2_diff,
+ pdata->lineout1fb,
+ pdata->lineout2fb,
+ pdata->jd_scthr,
+ pdata->jd_thr,
+ pdata->micbias1_lvl,
+ pdata->micbias2_lvl);
+ pdata->num_drc_cfgs = 0;//add
+ DBG_INFO(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
+
+ if (pdata->num_drc_cfgs)
+ {
+ struct snd_kcontrol_new controls[] =
+ {
+ SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
+ wm8994_get_drc_enum, wm8994_put_drc_enum),
+ SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
+ wm8994_get_drc_enum, wm8994_put_drc_enum),
+ SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
+ wm8994_get_drc_enum, wm8994_put_drc_enum),
+ };
+
+ // We need an array of texts for the enum API
+ wm8994->drc_texts = kmalloc(sizeof(char *)
+ * pdata->num_drc_cfgs, GFP_KERNEL);
+ if (!wm8994->drc_texts)
+ {
+ dev_err(wm8994->codec.dev,"Failed to allocate %d DRC config texts\n",
+ pdata->num_drc_cfgs);
+ return;
+ }
+
+ for (i = 0; i < pdata->num_drc_cfgs; i++)
+ wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
+
+ wm8994->drc_enum.max = pdata->num_drc_cfgs;
+ wm8994->drc_enum.texts = wm8994->drc_texts;
+
+ ret = snd_soc_add_controls(&wm8994->codec, controls,
+ ARRAY_SIZE(controls));
+ if (ret != 0)
+ dev_err(wm8994->codec.dev,
+ "Failed to add DRC mode controls: %d\n", ret);
+
+ for (i = 0; i < WM8994_NUM_DRC; i++)
+ wm8994_set_drc(codec, i);
+ }
+ pdata->num_retune_mobile_cfgs = 0;//add
+ DBG_INFO(codec->dev, "%d ReTune Mobile configurations\n",
+ pdata->num_retune_mobile_cfgs);
+
+ if (pdata->num_retune_mobile_cfgs)
+ wm8994_handle_retune_mobile_pdata(wm8994);
+ else
+ snd_soc_add_controls(&wm8994->codec, wm8994_eq_controls,
+ ARRAY_SIZE(wm8994_eq_controls));
+}
static int wm8994_probe(struct platform_device *pdev)
{
@@ -2752,16 +3708,20 @@ static int wm8994_probe(struct platform_device *pdev)
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
dev_err(codec->dev, "failed to create pcms: %d\n", ret);
- goto pcm_err;
+ return ret;
}
- snd_soc_add_controls(codec,wm8994_snd_controls,
- ARRAY_SIZE(wm8994_snd_controls));
- snd_soc_dapm_new_controls(codec,wm8994_dapm_widgets,
- ARRAY_SIZE(wm8994_dapm_widgets));
- snd_soc_dapm_add_routes(codec,audio_map, ARRAY_SIZE(audio_map));
- snd_soc_dapm_new_widgets(codec);
+ wm8994_handle_pdata(codec->private_data);
+ wm_hubs_add_analogue_controls(codec);
+ snd_soc_add_controls(codec, wm8994_snd_controls,
+ ARRAY_SIZE(wm8994_snd_controls));
+ snd_soc_dapm_new_controls(codec, wm8994_dapm_widgets,
+ ARRAY_SIZE(wm8994_dapm_widgets));
+ wm_hubs_add_analogue_routes(codec, 0, 0);
+ snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
+ snd_soc_dapm_new_widgets(codec); //and
+
ret = snd_soc_init_card(socdev);
if (ret < 0) {
dev_err(codec->dev, "failed to register card: %d\n", ret);
@@ -2773,7 +3733,6 @@ static int wm8994_probe(struct platform_device *pdev)
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
-pcm_err:
return ret;
}
@@ -2794,66 +3753,318 @@ struct snd_soc_codec_device soc_codec_dev_wm8994 = {
.resume = wm8994_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_wm8994);
+//=====================================================================
+//Proc
+#ifdef WM8994_PROC
+static ssize_t wm8994_proc_write(struct file *file, const char __user *buffer,
+ unsigned long len, void *data)
+{
+ char *cookie_pot;
+ char *p;
+ int reg;
+ int value;
+
+ cookie_pot = (char *)vmalloc( len );
+ if (!cookie_pot)
+ {
+ return -ENOMEM;
+ }
+ else
+ {
+ if (copy_from_user( cookie_pot, buffer, len ))
+ return -EFAULT;
+ }
-static int wm8994_register(struct wm8994_priv *wm8994,
- enum snd_soc_control_type control)
+ switch(cookie_pot[0])
+ {
+ case 'l':
+ case 'L':
+ if(debug_write_read == 0)
+ debug_write_read = 1;
+ //power
+ DBG("----- power ---\n");
+ snd_soc_read(wm8994_codec,0x01);//wm8994_write(0x01, 0x3003);
+ snd_soc_read(wm8994_codec,0x03);//wm8994_write(0x03, 0x0330);
+ snd_soc_read(wm8994_codec,0x05);//wm8994_write(0x05, 0x0303);
+ snd_soc_read(wm8994_codec,0x4C);//wm8994_write(0x4C, 0x9F25);
+ //clk
+ DBG("----- CLK ----\n");
+ snd_soc_read(wm8994_codec,0x208);//wm8994_write(0x208, 0x000A);
+ snd_soc_read(wm8994_codec,0x200);//wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1) 0x0011
+ snd_soc_read(wm8994_codec,0x220);//wm8994_write(0x220, 0x0005);
+ snd_soc_read(wm8994_codec,0x221);//wm8994_write(0x221, 0x0700);
+ snd_soc_read(wm8994_codec,0x222);//wm8994_write(0x222, 0x3126);
+ snd_soc_read(wm8994_codec,0x223);//wm8994_write(0x223, 0x0100);
+ snd_soc_read(wm8994_codec,0x210);//wm8994_write(0x210, 0x0083); // SR=48KHz
+ snd_soc_read(wm8994_codec,0x303);//wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
+ snd_soc_read(wm8994_codec,0x304);//wm8994_write(0x304, 0x0040);AIF1 ADCLRCK DIV-----BCLK/64
+ snd_soc_read(wm8994_codec,0x305);//wm8994_write(0x305, 0x0040);AIF1 DACLRCK DIV-----BCLK/64
+ snd_soc_read(wm8994_codec,0x302);//wm8994_write(0x302, 0x7000);AIF1_MSTR=1
+ snd_soc_read(wm8994_codec,0x300);//wm8994_write(0x300, 0xC010); // i2s 16 bits
+ //path
+ DBG("----- path ------ \n");
+ snd_soc_read(wm8994_codec,0x420);//wm8994_write(0x420, 0x0000);
+ snd_soc_read(wm8994_codec,0x601);//wm8994_write(0x601, 0x0001);
+ snd_soc_read(wm8994_codec,0x602);//wm8994_write(0x602, 0x0001);
+ snd_soc_read(wm8994_codec,0x2D);//wm8994_write(0x2D, 0x0100);
+ snd_soc_read(wm8994_codec,0x2E);//wm8994_write(0x2E, 0x0100);
+ snd_soc_read(wm8994_codec,0x36);//wm8994_write(0x36, 0x0003);
+ //volume
+ DBG("------ volume ----- \n");
+ snd_soc_read(wm8994_codec,0x22);//wm8994_write(0x22, 0x0000);
+ snd_soc_read(wm8994_codec,0x23);//wm8994_write(0x23, 0x0100);
+ snd_soc_read(wm8994_codec,0x26);//wm8994_write(0x26, 0x017F); //Speaker Left Output Volume
+ snd_soc_read(wm8994_codec,0x27);//wm8994_write(0x27, 0x017F); //Speaker Right Output Volume
+ snd_soc_read(wm8994_codec,0x610);//wm8994_write(0x610, 0x01c0); //DAC1 Left Volume bit0~7
+ snd_soc_read(wm8994_codec,0x611);//wm8994_write(0x611, 0x01c0); //DAC1 Right Volume bit0~7
+ break;
+ case 'd':
+ case 'D':
+ debug_write_read ++;
+ debug_write_read %= 2;
+ if(debug_write_read != 0)
+ DBG("Debug read and write reg on\n");
+ else
+ DBG("Debug read and write reg off\n");
+ break;
+ case 'r':
+ case 'R':
+ DBG("Read reg debug\n");
+ if(cookie_pot[1] ==':')
+ {
+ debug_write_read = 1;
+ strsep(&cookie_pot,":");
+ while((p=strsep(&cookie_pot,",")))
+ {
+ snd_soc_read(wm8994_codec,simple_strtol(p,NULL,16));
+ }
+ debug_write_read = 0;;
+ DBG("\n");
+ }
+ else
+ {
+ DBG("Error Read reg debug.\n");
+ DBG("For example: r:22,23,24,25\n");
+ }
+ break;
+ case 'w':
+ case 'W':
+ DBG("Write reg debug\n");
+ if(cookie_pot[1] ==':')
+ {
+ debug_write_read = 1;
+ strsep(&cookie_pot,":");
+ while((p=strsep(&cookie_pot,"=")))
+ {
+ reg = simple_strtol(p,NULL,16);
+ p=strsep(&cookie_pot,",");
+ value = simple_strtol(p,NULL,16);
+ snd_soc_write(wm8994_codec,reg,value);
+ }
+ debug_write_read = 0;;
+ DBG("\n");
+ }
+ else
+ {
+ DBG("Error Write reg debug.\n");
+ DBG("For example: w:22=0,23=0,24=0,25=0\n");
+ }
+ break;
+ default:
+ printk("Please press 'l'!\n");
+ break;
+ }
+
+ return len;
+}
+static const struct file_operations wm8994_proc_fops = {
+ .owner = THIS_MODULE,
+ //.open = snd_mem_proc_open,
+ //.read = seq_read,
+//#ifdef CONFIG_PCI
+ .write = wm8994_proc_write,
+//#endif
+ //.llseek = seq_lseek,
+ //.release = single_release,
+};
+
+static int wm8994_proc_init(void)
{
- struct snd_soc_codec *codec = &wm8994->codec;
- int ret;
+ struct proc_dir_entry *wm8994_proc_entry;
+ wm8994_proc_entry = create_proc_entry("driver/wm8994_ts", 0777, NULL);
+ if(wm8994_proc_entry != NULL)
+ {
+ wm8994_proc_entry->write_proc = wm8994_proc_write;
+ return -1;
+ }
+ else
+ {
+ printk("create proc error !\n");
+ }
+ return 0;
+}
+
+#endif
+//=======================================================================================
+static int wm8994_codec_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct wm8994_priv *wm8994;
+ struct snd_soc_codec *codec;
+ int i;
+ u16 rev;
+
+#ifdef WM8994_PROC
+ wm8994_proc_init();
+#endif
+
+// DBG("Enter %s::%s---%d\n",__FILE__,__FUNCTION__,__LINE__);
if (wm8994_codec) {
- dev_err(codec->dev, "Another WM8994 is registered\n");
- ret = -EINVAL;
- goto err;
+ dev_err(&pdev->dev, "Another WM8994 is registered\n");
+ return -EINVAL;
+ }
+
+ wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
+ if (!wm8994) {
+ dev_err(&pdev->dev, "Failed to allocate private data\n");
+ return -ENOMEM;
}
+ codec = &wm8994->codec;
+
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->private_data = wm8994;
+ codec->control_data = dev_get_drvdata(pdev->dev.parent);
codec->name = "WM8994";
codec->owner = THIS_MODULE;
- codec->dai = &wm8994_dai;
- codec->num_dai = 1;
- codec->reg_cache_size = ARRAY_SIZE(wm8994->reg_cache);
- codec->reg_cache = &wm8994->reg_cache;
+ codec->read = wm8994_read;
+ codec->write = wm8994_write;
+ codec->readable_register = wm8994_readable;
codec->bias_level = SND_SOC_BIAS_OFF;
codec->set_bias_level = wm8994_set_bias_level;
+ codec->dai = &wm8994_dai[0];
+ codec->num_dai = 3;
+ codec->reg_cache_size = WM8994_MAX_REGISTER;
+ codec->reg_cache = &wm8994->reg_cache;
+ codec->dev = &pdev->dev;
+
+ wm8994->pdata = pdev->dev.parent->platform_data;
+
+ /* Fill the cache with physical values we inherited; don't reset */
+ ret = wm8994_bulk_read(codec->control_data, 0,
+ ARRAY_SIZE(wm8994->reg_cache) - 1,
+ codec->reg_cache);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to fill register cache: %d\n",
+ ret);
+ goto err;
+ }
- memcpy(codec->reg_cache, wm8994_reg,
- sizeof(wm8994_reg));
+ /* Clear the cached values for unreadable/volatile registers to
+ * avoid potential confusion.
+ */
+ for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++)
+ if (wm8994_volatile(i) || !wm8994_readable(i))
+ wm8994->reg_cache[i] = 0;
+
+ /* Set revision-specific configuration */
+ rev = snd_soc_read(codec, WM8994_CHIP_REVISION);
+ switch (rev) {
+ case 2:
+ case 3:
+ wm8994->hubs.dcs_codes = -5;
+ wm8994->hubs.hp_startup_mode = 1;
+ wm8994->hubs.dcs_readback_mode = 1;
+ break;
+ default:
+ wm8994->hubs.dcs_readback_mode = 1;
+ break;
+ }
- ret = snd_soc_codec_set_cache_io(codec,7, 9, control);
+ /* Remember if AIFnLRCLK is configured as a GPIO. This should be
+ * configured on init - if a system wants to do this dynamically
+ * at runtime we can deal with that then.
+ */
+ ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
if (ret < 0) {
- dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+ dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
goto err;
}
+ if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
+ wm8994->lrclk_shared[0] = 1;
+ wm8994_dai[0].symmetric_rates = 1;
+ } else {
+ wm8994->lrclk_shared[0] = 0;
+ }
- ret = 0;
+ ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
if (ret < 0) {
- dev_err(codec->dev, "Failed to issue reset\n");
+ dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
goto err;
}
+ if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
+ wm8994->lrclk_shared[1] = 1;
+ wm8994_dai[1].symmetric_rates = 1;
+ } else {
+ wm8994->lrclk_shared[1] = 0;
+ }
- wm8994_set_bias_level(&wm8994->codec, SND_SOC_BIAS_STANDBY);
+ for (i = 0; i < ARRAY_SIZE(wm8994_dai); i++)
+ wm8994_dai[i].dev = codec->dev;
- wm8994_dai.dev = codec->dev;
+ wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
wm8994_codec = codec;
+ /* Latch volume updates (right only; we always do left then right). */
+ snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
+ WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
+ snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
+ WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
+ snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
+ WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
+ snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
+ WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
+ snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
+ WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
+ snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
+ WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
+ snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
+ WM8994_DAC1_VU, WM8994_DAC1_VU);
+ snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
+ WM8994_DAC2_VU, WM8994_DAC2_VU);
+
+ /* Set the low bit of the 3D stereo depth so TLV matches */
+ snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
+ 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
+ 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
+ snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
+ 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
+ 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
+ snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
+ 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
+ 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
+
+ wm8994_update_class_w(codec);
+
ret = snd_soc_register_codec(codec);
if (ret != 0) {
dev_err(codec->dev, "Failed to register codec: %d\n", ret);
goto err;
}
- ret = snd_soc_register_dai(&wm8994_dai);
+ ret = snd_soc_register_dais(wm8994_dai, ARRAY_SIZE(wm8994_dai));
if (ret != 0) {
- dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
- snd_soc_unregister_codec(codec);
+ dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
goto err_codec;
}
+
+ platform_set_drvdata(pdev, wm8994);
+
return 0;
err_codec:
@@ -2863,206 +4074,38 @@ err:
return ret;
}
-static void wm8994_unregister(struct wm8994_priv *wm8994)
+static int __devexit wm8994_codec_remove(struct platform_device *pdev)
{
- wm8994_set_bias_level(&wm8994->codec, SND_SOC_BIAS_OFF);
- snd_soc_unregister_dai(&wm8994_dai);
+ struct wm8994_priv *wm8994 = platform_get_drvdata(pdev);
+ struct snd_soc_codec *codec = &wm8994->codec;
+
+ wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
+ snd_soc_unregister_dais(wm8994_dai, ARRAY_SIZE(wm8994_dai));
snd_soc_unregister_codec(&wm8994->codec);
kfree(wm8994);
wm8994_codec = NULL;
-}
-
-#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-static int wm8994_i2c_probe(struct i2c_client *i2c,
- const struct i2c_device_id *id)
-{
- struct wm8994_priv *wm8994;
- struct snd_soc_codec *codec;
- wm8994_client=i2c;
-
- wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
- if (wm8994 == NULL)
- return -ENOMEM;
-
- codec = &wm8994->codec;
-
- i2c_set_clientdata(i2c, wm8994);
- codec->control_data = i2c;
-
- codec->dev = &i2c->dev;
-
- return wm8994_register(wm8994, SND_SOC_I2C);
-}
-
-static int wm8994_i2c_remove(struct i2c_client *client)
-{
- struct wm8994_priv *wm8994 = i2c_get_clientdata(client);
- wm8994_unregister(wm8994);
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int wm8994_i2c_suspend(struct i2c_client *client, pm_message_t msg)
-{
- return snd_soc_suspend_device(&client->dev);
-}
-
-static int wm8994_i2c_resume(struct i2c_client *client)
-{
- return snd_soc_resume_device(&client->dev);
-}
-#else
-#define wm8994_i2c_suspend NULL
-#define wm8994_i2c_resume NULL
-#endif
-
-static const struct i2c_device_id wm8994_i2c_id[] = {
- { "wm8994", 0 },
- { }
-};
-MODULE_DEVICE_TABLE(i2c, wm8994_i2c_id);
-
-static struct i2c_driver wm8994_i2c_driver = {
- .driver = {
- .name = "WM8994",
- .owner = THIS_MODULE,
- },
- .probe = wm8994_i2c_probe,
- .remove = wm8994_i2c_remove,
- .suspend = wm8994_i2c_suspend,
- .resume = wm8994_i2c_resume,
- .id_table = wm8994_i2c_id,
-};
-
-int reg_send_data(struct i2c_client *client, unsigned short *reg, unsigned short *data, u32 scl_rate)
-{
- int ret;
- struct i2c_adapter *adap = client->adapter;
- struct i2c_msg msg;
- char tx_buf[4];
-
- memcpy(tx_buf, reg, 2);
- memcpy(tx_buf+2, data, 2);
- msg.addr = client->addr;
- msg.buf = tx_buf;
- msg.len = 4;
- msg.flags = client->flags;
- msg.scl_rate = scl_rate;
- msg.read_type = I2C_NORMAL;
- ret = i2c_transfer(adap, &msg, 1);
-
- return ret;
-}
-
-int reg_recv_data(struct i2c_client *client, unsigned short *reg, unsigned short *buf, u32 scl_rate)
-{
- int ret;
- struct i2c_adapter *adap = client->adapter;
- struct i2c_msg msgs[2];
-
- msgs[0].addr = client->addr;
- msgs[0].buf = (char *)reg;
- msgs[0].flags = client->flags;
- msgs[0].len = 2;
- msgs[0].scl_rate = scl_rate;
- msgs[0].read_type = I2C_NO_STOP;
-
- msgs[1].addr = client->addr;
- msgs[1].buf = (char *)buf;
- msgs[1].flags = client->flags | I2C_M_RD;
- msgs[1].len = 2;
- msgs[1].scl_rate = scl_rate;
- msgs[1].read_type = I2C_NO_STOP;
-
- ret = i2c_transfer(adap, msgs, 2);
-
- return ret;
-}
-
-#endif
-
-#if defined(CONFIG_SPI_MASTER)
-static int __devinit wm8994_spi_probe(struct spi_device *spi)
-{
- struct wm8994_priv *wm8994;
- struct snd_soc_codec *codec;
-
- wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
- if (wm8994 == NULL)
- return -ENOMEM;
-
- codec = &wm8994->codec;
- codec->control_data = spi;
- codec->dev = &spi->dev;
-
- dev_set_drvdata(&spi->dev, wm8994);
-
- return wm8994_register(wm8994, SND_SOC_SPI);
-}
-
-static int __devexit wm8994_spi_remove(struct spi_device *spi)
-{
- struct wm8994_priv *wm8994 = dev_get_drvdata(&spi->dev);
-
- wm8994_unregister(wm8994);
return 0;
}
-#ifdef CONFIG_PM
-static int wm8994_spi_suspend(struct spi_device *spi, pm_message_t msg)
-{
- return snd_soc_suspend_device(&spi->dev);
-}
-
-static int wm8994_spi_resume(struct spi_device *spi)
-{
- return snd_soc_resume_device(&spi->dev);
-}
-#else
-#define wm8994_spi_suspend NULL
-#define wm8994_spi_resume NULL
-#endif
-
-static struct spi_driver wm8994_spi_driver = {
+static struct platform_driver wm8994_codec_driver = {
.driver = {
- .name = "wm8994",
- .bus = &spi_bus_type,
- .owner = THIS_MODULE,
- },
- .probe = wm8994_spi_probe,
- .remove = __devexit_p(wm8994_spi_remove),
- .suspend = wm8994_spi_suspend,
- .resume = wm8994_spi_resume,
+ .name = "wm8994-codec",
+ .owner = THIS_MODULE,
+ },
+ .probe = wm8994_codec_probe,
+ .remove = __devexit_p(wm8994_codec_remove),
};
-#endif
-static int __init wm8994_modinit(void)
+static __init int wm8994_init(void)
{
- int ret;
-
-#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
- ret = i2c_add_driver(&wm8994_i2c_driver);
- if (ret != 0)
- pr_err("WM8994: Unable to register I2C driver: %d\n", ret);
-#endif
-#if defined(CONFIG_SPI_MASTER)
- ret = spi_register_driver(&wm8994_spi_driver);
- if (ret != 0)
- pr_err("WM8994: Unable to register SPI driver: %d\n", ret);
-#endif
- return ret;
+ return platform_driver_register(&wm8994_codec_driver);
}
-module_init(wm8994_modinit);
+module_init(wm8994_init);
-static void __exit wm8994_exit(void)
+static __exit void wm8994_exit(void)
{
-#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
- i2c_del_driver(&wm8994_i2c_driver);
-#endif
-#if defined(CONFIG_SPI_MASTER)
- spi_unregister_driver(&wm8994_spi_driver);
-#endif
+ platform_driver_unregister(&wm8994_codec_driver);
}
module_exit(wm8994_exit);
@@ -3070,3 +4113,4 @@ module_exit(wm8994_exit);
MODULE_DESCRIPTION("ASoC WM8994 driver");
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:wm8994-codec");
diff --git a/sound/soc/codecs/wm8994.h b/sound/soc/codecs/wm8994.h
index ff9051e28674..0a5e1424dea0 100755
--- a/sound/soc/codecs/wm8994.h
+++ b/sound/soc/codecs/wm8994.h
@@ -1,75 +1,26 @@
/*
- * Copyright 2005 Openedhand Ltd.
- *
- * Author: Richard Purdie <richard@openedhand.com>
- *
- * Based on WM8753.h
+ * wm8994.h -- WM8994 Soc Audio driver
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
- *
*/
#ifndef _WM8994_H
#define _WM8994_H
-/* WM8994 register space */
+#include <sound/soc.h>
-#define WM8994_LINVOL 0x0f
-#define WM8994_RINVOL 0x01
-#define WM8994_LOUT1V 0x02
-#define WM8994_ROUT1V 0x03
-#define WM8994_ADCDAC 0x05
-#define WM8994_IFACE 0x07
-#define WM8994_SRATE 0x08
-#define WM8994_LDAC 0x0a
-#define WM8994_RDAC 0x0b
-#define WM8994_BASS 0x0c
-#define WM8994_TREBLE 0x0d
-#define WM8994_RESET 0x00
-#define WM8994_3D 0x10
-#define WM8994_ALC1 0x11
-#define WM8994_ALC2 0x12
-#define WM8994_ALC3 0x13
-#define WM8994_NGATE 0x14
-#define WM8994_LADC 0x15
-#define WM8994_RADC 0x16
-#define WM8994_ADCTL1 0x17
-#define WM8994_ADCTL2 0x18
-#define WM8994_PWR1 0x19
-#define WM8994_PWR2 0x1a
-#define WM8994_ADCTL3 0x1b
-#define WM8994_ADCIN 0x1f
-#define WM8994_LADCIN 0x20
-#define WM8994_RADCIN 0x21
-#define WM8994_LOUTM1 0x22
-#define WM8994_LOUTM2 0x23
-#define WM8994_ROUTM1 0x24
-#define WM8994_ROUTM2 0x25
-#define WM8994_LOUT2V 0x28
-#define WM8994_ROUT2V 0x29
-#define WM8994_LPPB 0x43
-#define WM8994_NUM_REG 0x44
-
-#define WM8994_SYSCLK 0
-
-extern struct snd_soc_dai wm8994_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm8994;
-void wm8994_codec_set_volume(unsigned char mode,unsigned char volume);
+extern struct snd_soc_dai wm8994_dai[];
+
+/* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */
+#define WM8994_SYSCLK_MCLK1 1
+#define WM8994_SYSCLK_MCLK2 2
+#define WM8994_SYSCLK_FLL1 3
+#define WM8994_SYSCLK_FLL2 4
-struct wm8994_platform_data {
- unsigned int mic_input;
- unsigned int micBase_vcc;
- unsigned int bb_input;
- unsigned int bb_output;
- unsigned int frequence;
- unsigned int enable_pin;
- unsigned int headset_pin;
- unsigned int headset_call_vol;
- unsigned int speaker_call_vol;
- unsigned int earpiece_call_vol;
- unsigned int bt_call_vol;
-};
+#define WM8994_FLL1 1
+#define WM8994_FLL2 2
#endif
diff --git a/sound/soc/codecs/wm_hubs.c b/sound/soc/codecs/wm_hubs.c
old mode 100644
new mode 100755
index e542027eea89..019ac214ced7
--- a/sound/soc/codecs/wm_hubs.c
+++ b/sound/soc/codecs/wm_hubs.c
@@ -62,36 +62,108 @@ static const char *speaker_mode_text[] = {
static const struct soc_enum speaker_mode =
SOC_ENUM_SINGLE(WM8993_SPKMIXR_ATTENUATION, 8, 2, speaker_mode_text);
-static void wait_for_dc_servo(struct snd_soc_codec *codec)
+static void wait_for_dc_servo(struct snd_soc_codec *codec, unsigned int op)
{
unsigned int reg;
int count = 0;
+ unsigned int val;
+
+ val = op | WM8993_DCS_ENA_CHAN_0 | WM8993_DCS_ENA_CHAN_1;
+
+ /* Trigger the command */
+ snd_soc_write(codec, WM8993_DC_SERVO_0, val);
+
+ dev_info(codec->dev, "Waiting for DC servo...\n");
- dev_dbg(codec->dev, "Waiting for DC servo...\n");
do {
count++;
- msleep(1);
- reg = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_0);
- dev_dbg(codec->dev, "DC servo status: %x\n", reg);
- } while ((reg & WM8993_DCS_CAL_COMPLETE_MASK)
- != WM8993_DCS_CAL_COMPLETE_MASK && count < 1000);
-
- if ((reg & WM8993_DCS_CAL_COMPLETE_MASK)
- != WM8993_DCS_CAL_COMPLETE_MASK)
+ msleep(10);
+ reg = snd_soc_read(codec, WM8993_DC_SERVO_0);
+ dev_info(codec->dev, "DC servo: %x\n", reg);
+ } while (reg & op && count < 400);
+
+ if (reg & op)
dev_err(codec->dev, "Timed out waiting for DC Servo\n");
}
+/*
+ * Startup calibration of the DC servo
+ */
+static void calibrate_dc_servo(struct snd_soc_codec *codec)
+{
+ struct wm_hubs_data *hubs = codec->private_data;
+ u16 reg, reg_l, reg_r, dcs_cfg;
+
+ /* Set for 32 series updates */
+ snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
+ WM8993_DCS_SERIES_NO_01_MASK,
+ 32 << WM8993_DCS_SERIES_NO_01_SHIFT);
+ wait_for_dc_servo(codec,
+ WM8993_DCS_TRIG_SERIES_0 | WM8993_DCS_TRIG_SERIES_1);
+
+ /* Apply correction to DC servo result */
+ if (hubs->dcs_codes) {
+ dev_dbg(codec->dev, "Applying %d code DC servo correction\n",
+ hubs->dcs_codes);
+
+ /* Different chips in the family support different
+ * readback methods.
+ */
+ switch (hubs->dcs_readback_mode) {
+ case 0:
+ reg_l = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_1)
+ & WM8993_DCS_INTEG_CHAN_0_MASK;;
+ reg_r = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_2)
+ & WM8993_DCS_INTEG_CHAN_1_MASK;
+ break;
+ case 1:
+ reg = snd_soc_read(codec, WM8993_DC_SERVO_3);
+ reg_l = (reg & WM8993_DCS_DAC_WR_VAL_1_MASK)
+ >> WM8993_DCS_DAC_WR_VAL_1_SHIFT;
+ reg_r = reg & WM8993_DCS_DAC_WR_VAL_0_MASK;
+ break;
+ default:
+ WARN(1, "Unknown DCS readback method");
+ break;
+ }
+
+ /* HPOUT1L */
+ if (reg_l + hubs->dcs_codes > 0 &&
+ reg_l + hubs->dcs_codes < 0xff)
+ reg_l += hubs->dcs_codes;
+ dcs_cfg = reg_l << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
+
+ /* HPOUT1R */
+ if (reg_r + hubs->dcs_codes > 0 &&
+ reg_r + hubs->dcs_codes < 0xff)
+ reg_r += hubs->dcs_codes;
+ dcs_cfg |= reg_r;
+
+ /* Do it */
+ snd_soc_write(codec, WM8993_DC_SERVO_3, dcs_cfg);
+ wait_for_dc_servo(codec,
+ WM8993_DCS_TRIG_DAC_WR_0 |
+ WM8993_DCS_TRIG_DAC_WR_1);
+ }
+}
+
/*
* Update the DC servo calibration on gain changes
*/
static int wm8993_put_dc_servo(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_value *ucontrol)
+ struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct wm_hubs_data *hubs = codec->private_data;
int ret;
ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
+ /* If we're applying an offset correction then updating the
+ * callibration would be likely to introduce further offsets. */
+ if (hubs->dcs_codes)
+ return ret;
+
/* Only need to do this if the outputs are active */
if (snd_soc_read(codec, WM8993_POWER_MANAGEMENT_1)
& (WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA))
@@ -251,6 +323,47 @@ SOC_SINGLE_TLV("LINEOUT2 Volume", WM8993_LINE_OUTPUTS_VOLUME, 0, 1, 1,
line_tlv),
};
+static int hp_supply_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct wm_hubs_data *hubs = codec->private_data;
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ switch (hubs->hp_startup_mode) {
+ case 0:
+ break;
+ case 1:
+ /* Enable the headphone amp */
+ snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
+ WM8993_HPOUT1L_ENA |
+ WM8993_HPOUT1R_ENA,
+ WM8993_HPOUT1L_ENA |
+ WM8993_HPOUT1R_ENA);
+
+ /* Enable the second stage */
+ snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
+ WM8993_HPOUT1L_DLY |
+ WM8993_HPOUT1R_DLY,
+ WM8993_HPOUT1L_DLY |
+ WM8993_HPOUT1R_DLY);
+ break;
+ default:
+ dev_err(codec->dev, "Unknown HP startup mode %d\n",
+ hubs->hp_startup_mode);
+ break;
+ }
+
+ case SND_SOC_DAPM_PRE_PMD:
+ snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
+ WM8993_CP_ENA, 0);
+ break;
+ }
+
+ return 0;
+}
+
static int hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
@@ -271,14 +384,11 @@ static int hp_event(struct snd_soc_dapm_widget *w,
reg |= WM8993_HPOUT1L_DLY | WM8993_HPOUT1R_DLY;
snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg);
- /* Start the DC servo */
- snd_soc_update_bits(codec, WM8993_DC_SERVO_0,
- 0xFFFF,
- WM8993_DCS_ENA_CHAN_0 |
- WM8993_DCS_ENA_CHAN_1 |
- WM8993_DCS_TRIG_STARTUP_1 |
- WM8993_DCS_TRIG_STARTUP_0);
- wait_for_dc_servo(codec);
+ /* Smallest supported update interval */
+ snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
+ WM8993_DCS_TIMER_PERIOD_01_MASK, 1);
+
+ calibrate_dc_servo(codec);
reg |= WM8993_HPOUT1R_OUTP | WM8993_HPOUT1R_RMV_SHORT |
WM8993_HPOUT1L_OUTP | WM8993_HPOUT1L_RMV_SHORT;
@@ -286,23 +396,19 @@ static int hp_event(struct snd_soc_dapm_widget *w,
break;
case SND_SOC_DAPM_PRE_PMD:
- reg &= ~(WM8993_HPOUT1L_RMV_SHORT |
- WM8993_HPOUT1L_DLY |
- WM8993_HPOUT1L_OUTP |
- WM8993_HPOUT1R_RMV_SHORT |
- WM8993_HPOUT1R_DLY |
- WM8993_HPOUT1R_OUTP);
+ snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
+ WM8993_HPOUT1L_DLY |
+ WM8993_HPOUT1R_DLY |
+ WM8993_HPOUT1L_RMV_SHORT |
+ WM8993_HPOUT1R_RMV_SHORT, 0);
- snd_soc_update_bits(codec, WM8993_DC_SERVO_0,
- 0xffff, 0);
+ snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
+ WM8993_HPOUT1L_OUTP |
+ WM8993_HPOUT1R_OUTP, 0);
- snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg);
snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
0);
-
- snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
- WM8993_CP_ENA, 0);
break;
}
@@ -438,11 +544,11 @@ static const struct snd_soc_dapm_widget analogue_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN1LN"),
SND_SOC_DAPM_INPUT("IN1LP"),
SND_SOC_DAPM_INPUT("IN2LN"),
-SND_SOC_DAPM_INPUT("IN2LP/VXRN"),
+SND_SOC_DAPM_INPUT("IN2LP:VXRN"),
SND_SOC_DAPM_INPUT("IN1RN"),
SND_SOC_DAPM_INPUT("IN1RP"),
SND_SOC_DAPM_INPUT("IN2RN"),
-SND_SOC_DAPM_INPUT("IN2RP/VXRP"),
+SND_SOC_DAPM_INPUT("IN2RP:VXRP"),
SND_SOC_DAPM_MICBIAS("MICBIAS2", WM8993_POWER_MANAGEMENT_1, 5, 0),
SND_SOC_DAPM_MICBIAS("MICBIAS1", WM8993_POWER_MANAGEMENT_1, 4, 0),
@@ -473,6 +579,8 @@ SND_SOC_DAPM_MIXER("Right Output Mixer", WM8993_POWER_MANAGEMENT_3, 4, 0,
SND_SOC_DAPM_PGA("Left Output PGA", WM8993_POWER_MANAGEMENT_3, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Output PGA", WM8993_POWER_MANAGEMENT_3, 6, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0, hp_supply_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0,
NULL, 0,
hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
@@ -537,14 +645,14 @@ static const struct snd_soc_dapm_route analogue_routes[] = {
{ "IN1R PGA", "IN1RP Switch", "IN1RP" },
{ "IN1R PGA", "IN1RN Switch", "IN1RN" },
- { "IN2L PGA", "IN2LP Switch", "IN2LP/VXRN" },
+ { "IN2L PGA", "IN2LP Switch", "IN2LP:VXRN" },
{ "IN2L PGA", "IN2LN Switch", "IN2LN" },
- { "IN2R PGA", "IN2RP Switch", "IN2RP/VXRP" },
+ { "IN2R PGA", "IN2RP Switch", "IN2RP:VXRP" },
{ "IN2R PGA", "IN2RN Switch", "IN2RN" },
- { "Direct Voice", NULL, "IN2LP/VXRN" },
- { "Direct Voice", NULL, "IN2RP/VXRP" },
+ { "Direct Voice", NULL, "IN2LP:VXRN" },
+ { "Direct Voice", NULL, "IN2RP:VXRP" },
{ "MIXINL", "IN1L Switch", "IN1L PGA" },
{ "MIXINL", "IN2L Switch", "IN2L PGA" },
@@ -565,7 +673,7 @@ static const struct snd_soc_dapm_route analogue_routes[] = {
{ "Left Output Mixer", "Right Input Switch", "MIXINR" },
{ "Left Output Mixer", "IN2RN Switch", "IN2RN" },
{ "Left Output Mixer", "IN2LN Switch", "IN2LN" },
- { "Left Output Mixer", "IN2LP Switch", "IN2LP/VXRN" },
+ { "Left Output Mixer", "IN2LP Switch", "IN2LP:VXRN" },
{ "Left Output Mixer", "IN1L Switch", "IN1L PGA" },
{ "Left Output Mixer", "IN1R Switch", "IN1R PGA" },
@@ -573,7 +681,7 @@ static const struct snd_soc_dapm_route analogue_routes[] = {
{ "Right Output Mixer", "Right Input Switch", "MIXINR" },
{ "Right Output Mixer", "IN2LN Switch", "IN2LN" },
{ "Right Output Mixer", "IN2RN Switch", "IN2RN" },
- { "Right Output Mixer", "IN2RP Switch", "IN2RP/VXRP" },
+ { "Right Output Mixer", "IN2RP Switch", "IN2RP:VXRP" },
{ "Right Output Mixer", "IN1L Switch", "IN1L PGA" },
{ "Right Output Mixer", "IN1R Switch", "IN1R PGA" },
@@ -626,6 +734,7 @@ static const struct snd_soc_dapm_route analogue_routes[] = {
{ "Headphone PGA", NULL, "Left Headphone Mux" },
{ "Headphone PGA", NULL, "Right Headphone Mux" },
{ "Headphone PGA", NULL, "CLK_SYS" },
+ { "Headphone PGA", NULL, "Headphone Supply" },
{ "HPOUT1L", NULL, "Headphone PGA" },
{ "HPOUT1R", NULL, "Headphone PGA" },
@@ -738,6 +847,47 @@ int wm_hubs_add_analogue_routes(struct snd_soc_codec *codec,
}
EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_routes);
+int wm_hubs_handle_analogue_pdata(struct snd_soc_codec *codec,
+ int lineout1_diff, int lineout2_diff,
+ int lineout1fb, int lineout2fb,
+ int jd_scthr, int jd_thr, int micbias1_lvl,
+ int micbias2_lvl)
+{
+ if (!lineout1_diff)
+ snd_soc_update_bits(codec, WM8993_LINE_MIXER1,
+ WM8993_LINEOUT1_MODE,
+ WM8993_LINEOUT1_MODE);
+ if (!lineout2_diff)
+ snd_soc_update_bits(codec, WM8993_LINE_MIXER2,
+ WM8993_LINEOUT2_MODE,
+ WM8993_LINEOUT2_MODE);
+
+ /* If the line outputs are differential then we aren't presenting
+ * VMID as an output and can disable it.
+ */
+// if (lineout1_diff && lineout2_diff)
+// codec->idle_bias_off = 1;
+
+ if (lineout1fb)
+ snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
+ WM8993_LINEOUT1_FB, WM8993_LINEOUT1_FB);
+
+ if (lineout2fb)
+ snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
+ WM8993_LINEOUT2_FB, WM8993_LINEOUT2_FB);
+
+ snd_soc_update_bits(codec, WM8993_MICBIAS,
+ WM8993_JD_SCTHR_MASK | WM8993_JD_THR_MASK |
+ WM8993_MICB1_LVL | WM8993_MICB2_LVL,
+ jd_scthr << WM8993_JD_SCTHR_SHIFT |
+ jd_thr << WM8993_JD_THR_SHIFT |
+ micbias1_lvl |
+ micbias2_lvl << WM8993_MICB2_LVL_SHIFT);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(wm_hubs_handle_analogue_pdata);
+
MODULE_DESCRIPTION("Shared support for Wolfson hubs products");
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm_hubs.h b/sound/soc/codecs/wm_hubs.h
old mode 100644
new mode 100755
index ec09cb6a2939..e51c16683589
--- a/sound/soc/codecs/wm_hubs.h
+++ b/sound/soc/codecs/wm_hubs.h
@@ -18,7 +18,19 @@ struct snd_soc_codec;
extern const unsigned int wm_hubs_spkmix_tlv[];
+/* This *must* be the first element of the codec->private_data struct */
+struct wm_hubs_data {
+ int dcs_codes;
+ int dcs_readback_mode;
+ int hp_startup_mode;
+};
+
extern int wm_hubs_add_analogue_controls(struct snd_soc_codec *);
extern int wm_hubs_add_analogue_routes(struct snd_soc_codec *, int, int);
+extern int wm_hubs_handle_analogue_pdata(struct snd_soc_codec *,
+ int lineout1_diff, int lineout2_diff,
+ int lineout1fb, int lineout2fb,
+ int jd_scthr, int jd_thr,
+ int micbias1_lvl, int micbias2_lvl);
#endif
diff --git a/sound/soc/rk29/Kconfig b/sound/soc/rk29/Kconfig
index 37f8ce9860d1..84e566608218 100755
--- a/sound/soc/rk29/Kconfig
+++ b/sound/soc/rk29/Kconfig
@@ -41,6 +41,15 @@ config SND_RK29_SOC_WM8900
Say Y if you want to add support for SoC audio on rockchip
with the WM8900.
+config SND_RK29_SOC_WM8994
+ tristate "SoC I2S Audio support for rockchip - WM8994"
+ depends on SND_RK29_SOC && I2C_RK29
+ select SND_RK29_SOC_I2S
+ select SND_SOC_WM8994
+ help
+ Say Y if you want to add support for SoC audio on rockchip
+ with the WM8994.
+
config SND_RK29_SOC_RK1000
tristate "SoC I2S Audio support for rockchip - RK1000"
depends on SND_RK29_SOC && RK1000_CONTROL && I2C_RK29
diff --git a/sound/soc/rk29/rk29_pcm.c b/sound/soc/rk29/rk29_pcm.c
index f04bc5f812d8..d9ac85e96ed7 100755
--- a/sound/soc/rk29/rk29_pcm.c
+++ b/sound/soc/rk29/rk29_pcm.c
@@ -426,7 +426,7 @@ static int rockchip_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
struct rockchip_runtime_data *prtd = substream->runtime->private_data;
int ret = 0;
/**************add by qiuen for volume*****/
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
+/* struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *pCodec_dai = rtd->dai->codec_dai;
int vol = 0;
int streamType = 0;
@@ -438,7 +438,7 @@ static int rockchip_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
streamType = (substream->number / 100) % 100;
DBG("enter:vol=%d,streamType=%d\n",vol,streamType);
pCodec_dai->ops->set_volume(streamType, vol);
- }
+ }*/
/****************************************************/
spin_lock(&prtd->lock);
diff --git a/sound/soc/rk29/rk29_wm8994.c b/sound/soc/rk29/rk29_wm8994.c
new file mode 100755
index 000000000000..f2a0d379d1e5
--- /dev/null
+++ b/sound/soc/rk29/rk29_wm8994.c
@@ -0,0 +1,207 @@
+/*
+ * rk29_wm8994.c -- SoC audio for rockchip
+ *
+ * Driver for rockchip wm8994 audio
+ * Copyright (C) 2009 lhh
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <asm/io.h>
+#include <mach/hardware.h>
+#include <mach/rk29_iomap.h>
+#include "../codecs/wm8994.h"
+#include "rk29_pcm.h"
+#include "rk29_i2s.h"
+
+#if 0
+#define DBG(x...) printk(KERN_INFO x)
+#else
+#define DBG(x...)
+#endif
+
+static int rk29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
+ struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+ unsigned int pll_out = 0;
+ int ret;
+
+ DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ /*by Vincent Hsiung for EQ Vol Change*/
+// #define HW_PARAMS_FLAG_EQVOL_ON 0x21
+// #define HW_PARAMS_FLAG_EQVOL_OFF 0x22
+// if ((params->flags == HW_PARAMS_FLAG_EQVOL_ON)||(params->flags == HW_PARAMS_FLAG_EQVOL_OFF))
+// {
+// ret = codec_dai->ops->hw_params(substream, params, codec_dai); //by Vincent
+// }
+// else
+ {
+ /* set codec DAI configuration */
+ #if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
+ DBG("Set codec_dai slave\n");
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
+ #endif
+ #if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER)
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
+ DBG("Set codec_dai master\n",ret);
+ #endif
+ if (ret < 0)
+ return ret;
+
+ /* set cpu DAI configuration */
+ #if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
+ DBG("Set cpu_dai slave\n");
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
+ #endif
+ #if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER)
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
+ DBG("Set cpu_dai master\n",ret);
+ #endif
+ if (ret < 0)
+ return ret;
+ }
+ switch(params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 24000:
+ case 32000:
+ case 48000:
+ pll_out = 12288000;
+ break;
+ case 11025:
+ case 22050:
+ case 44100:
+ pll_out = 11289600;
+ break;
+ default:
+ DBG("Enter:%s, %d, Error rate=%d\n",__FUNCTION__,__LINE__,params_rate(params));
+ return -EINVAL;
+ break;
+ }
+ DBG("Enter:%s, %d, rate=%d\n",__FUNCTION__,__LINE__,params_rate(params));
+ //1¡¢ÉèÖÃSYSCLK = FLL1
+ snd_soc_dai_set_sysclk(codec_dai,WM8994_SYSCLK_FLL1,12000000,pll_out);
+ //2¡¢ÉèÖÃFLL1 CLK
+ snd_soc_dai_set_pll(codec_dai,WM8994_FLL1,12000000,pll_out);
+
+
+ return 0;
+}
+/*
+static const struct snd_soc_dapm_widget rk2818_dapm_widgets[] = {
+ SND_SOC_DAPM_LINE("Audio Out", NULL),
+ SND_SOC_DAPM_LINE("Line in", NULL),
+ SND_SOC_DAPM_MIC("Micn", NULL),
+ SND_SOC_DAPM_MIC("Micp", NULL),
+};
+
+static const struct snd_soc_dapm_route audio_map[]= {
+
+ {"Audio Out", NULL, "HP_L"},
+ {"Audio Out", NULL, "HP_R"},
+ {"Line in", NULL, "RINPUT1"},
+ {"Line in", NULL, "LINPUT1"},
+ {"Micn", NULL, "RINPUT2"},
+ {"Micp", NULL, "LINPUT2"},
+};
+*/
+/*
+ * Logic for a wm8994 as connected on a rockchip board.
+ ¿ª»ú³õʼ»¯codecÒ»´Î? Ó¦¸Ã¿ÉÒÔ×Ô¼º¸Ä¶¯
+ */
+static int rk29_wm8994_init(struct snd_soc_codec *codec)
+{
+// struct snd_soc_dai *codec_dai = &codec->dai[0];
+ DBG("Enter %s::%s---%d\n",__FILE__,__FUNCTION__,__LINE__);
+
+ /* Add specific widgets */
+// snd_soc_dapm_new_controls(codec, rk2818_dapm_widgets,
+// ARRAY_SIZE(rk2818_dapm_widgets));
+// snd_soc_dapm_nc_pin(codec, "LOUT2");
+// snd_soc_dapm_nc_pin(codec, "ROUT2");
+
+ /* Set up specific audio path audio_mapnects */
+// snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+
+// snd_soc_dapm_sync(codec);
+
+ return 0;
+}
+
+static struct snd_soc_ops rk29_ops = {
+ .hw_params = rk29_hw_params,
+};
+
+static struct snd_soc_dai_link rk29_dai = {
+ .name = "WM8994",
+ .stream_name = "WM8994 PCM",
+ .cpu_dai = &rk29_i2s_dai[0],
+ .codec_dai = &wm8994_dai,
+ .init = rk29_wm8994_init,
+ .ops = &rk29_ops,
+};
+
+static struct snd_soc_card snd_soc_card_rk29 = {
+ .name = "RK29_WM8994",
+ .platform = &rk29_soc_platform,
+ .dai_link = &rk29_dai,
+ .num_links = 1,
+};
+
+
+static struct snd_soc_device rk29_snd_devdata = {
+ .card = &snd_soc_card_rk29,
+ .codec_dev = &soc_codec_dev_wm8994,
+};
+
+static struct platform_device *rk29_snd_device;
+
+static int __init audio_card_init(void)
+{
+ int ret =0;
+ DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ rk29_snd_device = platform_device_alloc("soc-audio", -1);
+ if (!rk29_snd_device) {
+ DBG("platform device allocation failed\n");
+ ret = -ENOMEM;
+ return ret;
+ }
+ platform_set_drvdata(rk29_snd_device, &rk29_snd_devdata);
+ rk29_snd_devdata.dev = &rk29_snd_device->dev;
+ ret = platform_device_add(rk29_snd_device);
+ if (ret) {
+ DBG("platform device add failed\n");
+ platform_device_put(rk29_snd_device);
+ }
+ return ret;
+}
+
+static void __exit audio_card_exit(void)
+{
+ platform_device_unregister(rk29_snd_device);
+}
+
+module_init(audio_card_init);
+module_exit(audio_card_exit);
+/* Module information */
+MODULE_AUTHOR("rockchip");
+MODULE_DESCRIPTION("ROCKCHIP i2s ASoC Interface");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
index 66d4c165f99b..0b2918d7eaab 100644
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -1243,6 +1243,44 @@ static int dapm_mux_update_power(struct snd_soc_dapm_widget *widget,
return 0;
}
+/* test and update the power status of a mux widget */
+//copy on 2.6.34 by qjb
+static int dapm_mux_update_power_34(struct snd_soc_dapm_widget *widget,
+ struct snd_kcontrol *kcontrol, int change,
+ int mux, struct soc_enum *e)
+{
+ struct snd_soc_dapm_path *path;
+ int found = 0;
+
+ if (widget->id != snd_soc_dapm_mux &&
+ widget->id != snd_soc_dapm_value_mux)
+ return -ENODEV;
+
+ if (!change)
+ return 0;
+
+ /* find dapm widget path assoc with kcontrol */
+ list_for_each_entry(path, &widget->codec->dapm_paths, list) {
+ if (path->kcontrol != kcontrol)
+ continue;
+
+ if (!path->name || !e->texts[mux])
+ continue;
+
+ found = 1;
+ /* we now need to match the string in the enum to the path */
+ if (!(strcmp(path->name, e->texts[mux])))
+ path->connect = 1; /* new connection */
+ else
+ path->connect = 0; /* old connection must be powered down */
+ }
+
+ if (found)
+ dapm_power_widgets(widget->codec, SND_SOC_DAPM_STREAM_NOP);
+
+ return 0;
+}
+
/* test and update the power status of a mixer or switch widget */
static int dapm_mixer_update_power(struct snd_soc_dapm_widget *widget,
struct snd_kcontrol *kcontrol, int reg,
@@ -1807,6 +1845,56 @@ out:
}
EXPORT_SYMBOL_GPL(snd_soc_dapm_put_enum_double);
+/**
+ * snd_soc_dapm_get_enum_virt - Get virtual DAPM mux
+ * @kcontrol: mixer control
+ * @ucontrol: control element information
+ *
+ * Returns 0 for success.
+ */
+ //copy on 2.6.34 by qjb
+int snd_soc_dapm_get_enum_virt(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
+
+ ucontrol->value.enumerated.item[0] = widget->value;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(snd_soc_dapm_get_enum_virt);
+
+/**
+ * snd_soc_dapm_put_enum_virt - Set virtual DAPM mux
+ * @kcontrol: mixer control
+ * @ucontrol: control element information
+ *
+ * Returns 0 for success.
+ */
+ //copy on 2.6.34 by qjb
+int snd_soc_dapm_put_enum_virt(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
+ struct soc_enum *e =
+ (struct soc_enum *)kcontrol->private_value;
+ int change;
+ int ret = 0;
+
+ if (ucontrol->value.enumerated.item[0] >= e->max)
+ return -EINVAL;
+
+ mutex_lock(&widget->codec->mutex);
+
+ change = widget->value != ucontrol->value.enumerated.item[0];
+ widget->value = ucontrol->value.enumerated.item[0];
+ dapm_mux_update_power_34(widget, kcontrol, change, widget->value, e);
+
+ mutex_unlock(&widget->codec->mutex);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(snd_soc_dapm_put_enum_virt);
+
/**
* snd_soc_dapm_get_value_enum_double - dapm semi enumerated double mixer get
* callback
--
2.34.1