From 861e105e6141c4e44f3d8f9e7e13c2ea14d2950e Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Tue, 3 Feb 2015 19:43:59 +0000 Subject: [PATCH] [Hexagon] Updating XTYPE/PRED intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228019 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonIntrinsics.td | 38 ++--- lib/Target/Hexagon/HexagonIntrinsicsV4.td | 19 +++ test/CodeGen/Hexagon/intrinsics/xtype_pred.ll | 155 +++++++++++++++++- 3 files changed, 192 insertions(+), 20 deletions(-) diff --git a/lib/Target/Hexagon/HexagonIntrinsics.td b/lib/Target/Hexagon/HexagonIntrinsics.td index 22a02480a05..b84d9d3b0a0 100644 --- a/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/lib/Target/Hexagon/HexagonIntrinsics.td @@ -1089,6 +1089,25 @@ def : T_P_pat ; def : T_P_pat ; def : T_P_pat ; +/******************************************************************** +* STYPE/PRED * +*********************************************************************/ + +// Predicate transfer +def: Pat<(i32 (int_hexagon_C2_tfrpr (I32:$Rs))), + (i32 (C2_tfrpr (C2_tfrrp (I32:$Rs))))>; +def: Pat<(i32 (int_hexagon_C2_tfrrp (I32:$Rs))), + (i32 (C2_tfrpr (C2_tfrrp (I32:$Rs))))>; + +// Mask generate from predicate +def: Pat<(i64 (int_hexagon_C2_mask (I32:$Rs))), + (i64 (C2_mask (C2_tfrrp (I32:$Rs))))>; + +// Viterbi pack even and odd predicate bits +def: Pat<(i32 (int_hexagon_C2_vitpack (I32:$Rs), (I32:$Rt))), + (i32 (C2_vitpack (C2_tfrrp (I32:$Rs)), + (C2_tfrrp (I32:$Rt))))>; + /******************************************************************** * STYPE/SHIFT * *********************************************************************/ @@ -1704,25 +1723,6 @@ class di_LDInstPI_diu4 [], "$src1 = $dst">; -/******************************************************************** -* STYPE/PRED * -*********************************************************************/ - -// STYPE / PRED / Mask generate from predicate. -def HEXAGON_C2_mask: - di_SInst_qi <"mask", int_hexagon_C2_mask>; - -// STYPE / PRED / Predicate transfer. -def HEXAGON_C2_tfrpr: - si_SInst_qi <"", int_hexagon_C2_tfrpr>; -def HEXAGON_C2_tfrrp: - qi_SInst_si <"", int_hexagon_C2_tfrrp>; - -// STYPE / PRED / Viterbi pack even and odd predicate bits. -def HEXAGON_C2_vitpack: - si_SInst_qiqi <"vitpack",int_hexagon_C2_vitpack>; - - /******************************************************************** * STYPE/VH * *********************************************************************/ diff --git a/lib/Target/Hexagon/HexagonIntrinsicsV4.td b/lib/Target/Hexagon/HexagonIntrinsicsV4.td index 556e19d2cc0..8d068eb9721 100644 --- a/lib/Target/Hexagon/HexagonIntrinsicsV4.td +++ b/lib/Target/Hexagon/HexagonIntrinsicsV4.td @@ -78,6 +78,25 @@ def: T_RR_pat; def: T_RR_pat; def: T_RI_pat; + +class vcmpImm_pat : + Pat <(IntID (i64 DoubleRegs:$src1), immPred:$src2), + (MI (i64 DoubleRegs:$src1), immPred:$src2)>; + +def : vcmpImm_pat ; +def : vcmpImm_pat ; +def : vcmpImm_pat ; + +def : vcmpImm_pat ; +def : vcmpImm_pat ; +def : vcmpImm_pat ; + +def : vcmpImm_pat ; +def : vcmpImm_pat ; +def : vcmpImm_pat ; + +def : T_PP_pat; + def : T_RR_pat; def : T_RR_pat; def : T_RR_pat; diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll b/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll index ffedfd99908..96e63d8d779 100644 --- a/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll +++ b/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll @@ -158,7 +158,7 @@ define i64 @C2_mask(i32 %a) { %z = call i64 @llvm.hexagon.C2.mask(i32 %a) ret i64 %z } -; CHECK: = mask(r0) +; CHECK: = mask(p0) ; Check for TLB match declare i32 @llvm.hexagon.A4.tlbmatch(i64, i32) @@ -196,3 +196,156 @@ define i32 @S4_ntstbit_r(i32 %a, i32 %b) { ret i32 %z } ; CHECK: p0 = !tstbit(r0, r1) + +; Vector compare halfwords +declare i32 @llvm.hexagon.A2.vcmpheq(i64, i64) +define i32 @A2_vcmpheq(i64 %a, i64 %b) { + %z = call i32 @llvm.hexagon.A2.vcmpheq(i64 %a, i64 %b) + ret i32 %z +} +; CHECK: p0 = vcmph.eq(r1:0, r3:2) + +declare i32 @llvm.hexagon.A2.vcmphgt(i64, i64) +define i32 @A2_vcmphgt(i64 %a, i64 %b) { + %z = call i32 @llvm.hexagon.A2.vcmphgt(i64 %a, i64 %b) + ret i32 %z +} +; CHECK: p0 = vcmph.gt(r1:0, r3:2) + +declare i32 @llvm.hexagon.A2.vcmphgtu(i64, i64) +define i32 @A2_vcmphgtu(i64 %a, i64 %b) { + %z = call i32 @llvm.hexagon.A2.vcmphgtu(i64 %a, i64 %b) + ret i32 %z +} +; CHECK: p0 = vcmph.gtu(r1:0, r3:2) + +declare i32 @llvm.hexagon.A4.vcmpheqi(i64, i32) +define i32 @A4_vcmpheqi(i64 %a) { + %z = call i32 @llvm.hexagon.A4.vcmpheqi(i64 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = vcmph.eq(r1:0, #0) + +declare i32 @llvm.hexagon.A4.vcmphgti(i64, i32) +define i32 @A4_vcmphgti(i64 %a) { + %z = call i32 @llvm.hexagon.A4.vcmphgti(i64 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = vcmph.gt(r1:0, #0) + +declare i32 @llvm.hexagon.A4.vcmphgtui(i64, i32) +define i32 @A4_vcmphgtui(i64 %a) { + %z = call i32 @llvm.hexagon.A4.vcmphgtui(i64 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = vcmph.gtu(r1:0, #0) + +; Vector compare bytes for any match +declare i32 @llvm.hexagon.A4.vcmpbeq.any(i64, i64) +define i32 @A4_vcmpbeq_any(i64 %a, i64 %b) { + %z = call i32 @llvm.hexagon.A4.vcmpbeq.any(i64 %a, i64 %b) + ret i32 %z +} +; CHECK: p0 = any8(vcmpb.eq(r1:0, r3:2)) + +; Vector compare bytes +declare i32 @llvm.hexagon.A2.vcmpbeq(i64, i64) +define i32 @A2_vcmpbeq(i64 %a, i64 %b) { + %z = call i32 @llvm.hexagon.A2.vcmpbeq(i64 %a, i64 %b) + ret i32 %z +} +; CHECK: p0 = vcmpb.eq(r1:0, r3:2) + +declare i32 @llvm.hexagon.A2.vcmpbgtu(i64, i64) +define i32 @A2_vcmpbgtu(i64 %a, i64 %b) { + %z = call i32 @llvm.hexagon.A2.vcmpbgtu(i64 %a, i64 %b) + ret i32 %z +} +; CHECK: p0 = vcmpb.gtu(r1:0, r3:2) + +declare i32 @llvm.hexagon.A4.vcmpbgt(i64, i64) +define i32 @A4_vcmpbgt(i64 %a, i64 %b) { + %z = call i32 @llvm.hexagon.A4.vcmpbgt(i64 %a, i64 %b) + ret i32 %z +} +; CHECK: p0 = vcmpb.gt(r1:0, r3:2) + +declare i32 @llvm.hexagon.A4.vcmpbeqi(i64, i32) +define i32 @A4_vcmpbeqi(i64 %a) { + %z = call i32 @llvm.hexagon.A4.vcmpbeqi(i64 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = vcmpb.eq(r1:0, #0) + +declare i32 @llvm.hexagon.A4.vcmpbgti(i64, i32) +define i32 @A4_vcmpbgti(i64 %a) { + %z = call i32 @llvm.hexagon.A4.vcmpbgti(i64 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = vcmpb.gt(r1:0, #0) + +declare i32 @llvm.hexagon.A4.vcmpbgtui(i64, i32) +define i32 @A4_vcmpbgtui(i64 %a) { + %z = call i32 @llvm.hexagon.A4.vcmpbgtui(i64 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = vcmpb.gtu(r1:0, #0) + +; Vector compare words +declare i32 @llvm.hexagon.A2.vcmpweq(i64, i64) +define i32 @A2_vcmpweq(i64 %a, i64 %b) { + %z = call i32 @llvm.hexagon.A2.vcmpweq(i64 %a, i64 %b) + ret i32 %z +} +; CHECK: p0 = vcmpw.eq(r1:0, r3:2) + +declare i32 @llvm.hexagon.A2.vcmpwgt(i64, i64) +define i32 @A2_vcmpwgt(i64 %a, i64 %b) { + %z = call i32 @llvm.hexagon.A2.vcmpwgt(i64 %a, i64 %b) + ret i32 %z +} +; CHECK: p0 = vcmpw.gt(r1:0, r3:2) + +declare i32 @llvm.hexagon.A2.vcmpwgtu(i64, i64) +define i32 @A2_vcmpwgtu(i64 %a, i64 %b) { + %z = call i32 @llvm.hexagon.A2.vcmpwgtu(i64 %a, i64 %b) + ret i32 %z +} +; CHECK: p0 = vcmpw.gtu(r1:0, r3:2) + +declare i32 @llvm.hexagon.A4.vcmpweqi(i64, i32) +define i32 @A4_vcmpweqi(i64 %a) { + %z = call i32 @llvm.hexagon.A4.vcmpweqi(i64 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = vcmpw.eq(r1:0, #0) + +declare i32 @llvm.hexagon.A4.vcmpwgti(i64, i32) +define i32 @A4_vcmpwgti(i64 %a) { + %z = call i32 @llvm.hexagon.A4.vcmpwgti(i64 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = vcmpw.gt(r1:0, #0) + +declare i32 @llvm.hexagon.A4.vcmpwgtui(i64, i32) +define i32 @A4_vcmpwgtui(i64 %a) { + %z = call i32 @llvm.hexagon.A4.vcmpwgtui(i64 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = vcmpw.gtu(r1:0, #0) + +; Viterbi pack even and odd predicate bitsclr +declare i32 @llvm.hexagon.C2.vitpack(i32, i32) +define i32 @C2_vitpack(i32 %a, i32 %b) { + %z = call i32 @llvm.hexagon.C2.vitpack(i32 %a, i32 %b) + ret i32 %z +} +; CHECK: r0 = vitpack(p1, p0) + +; Vector mux +declare i64 @llvm.hexagon.C2.vmux(i32, i64, i64) +define i64 @C2_vmux(i32 %a, i64 %b, i64 %c) { + %z = call i64 @llvm.hexagon.C2.vmux(i32 %a, i64 %b, i64 %c) + ret i64 %z +} +; CHECK: = vmux(p0, r3:2, r5:4) -- 2.34.1