From 8666da7f001578b26d9dd795b23062c42551d44a Mon Sep 17 00:00:00 2001 From: dkl Date: Thu, 20 Mar 2014 20:10:51 +0800 Subject: [PATCH] rk3288: fix some mux clks with unexcepted reg val --- arch/arm/boot/dts/rk3288-clocks.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-clocks.dtsi b/arch/arm/boot/dts/rk3288-clocks.dtsi index 9e93daafcfc4..ff2399ef6c5f 100644 --- a/arch/arm/boot/dts/rk3288-clocks.dtsi +++ b/arch/arm/boot/dts/rk3288-clocks.dtsi @@ -422,7 +422,7 @@ clk_uart4: uart4_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 2>; - clocks = <&clk_uart4_div>, <&uart4_frac>, <&xin24m>; + clocks = <&clk_uart4_div>, <&uart4_frac>, <&xin24m>, <&dummy>; clock-output-names = "clk_uart4"; #clock-cells = <0>; rockchip,clkops-idx = @@ -505,7 +505,7 @@ clk_spdif: spdif_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 2>; - clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>; + clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>, <&dummy>; clock-output-names = "clk_spdif"; #clock-cells = <0>; rockchip,flags = ; @@ -789,7 +789,7 @@ clk_uart0: uart0_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 2>; - clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>; + clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&dummy>; clock-output-names = "clk_uart0"; #clock-cells = <0>; rockchip,clkops-idx = @@ -845,7 +845,7 @@ clk_uart1: uart1_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 2>; - clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>; + clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>, <&dummy>; clock-output-names = "clk_uart1"; #clock-cells = <0>; rockchip,clkops-idx = @@ -876,7 +876,7 @@ clk_uart2: uart2_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 2>; - clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>; + clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>, <&dummy>; clock-output-names = "clk_uart2"; #clock-cells = <0>; rockchip,clkops-idx = @@ -907,7 +907,7 @@ clk_uart3: uart3_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 2>; - clocks = <&clk_uart3_div>, <&uart3_frac>, <&xin24m>; + clocks = <&clk_uart3_div>, <&uart3_frac>, <&xin24m>, <&dummy>; clock-output-names = "clk_uart3"; #clock-cells = <0>; rockchip,clkops-idx = -- 2.34.1