From 86ca3cacc5a56e862c8258ac9c9ee1e37598ebd8 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 13 Feb 2008 07:39:09 +0000 Subject: [PATCH] In SDISel, for targets that support FORMAL_ARGUMENTS nodes, lower this node as soon as we create it in SDISel. Previously we would lower it in legalize. The problem with this is that it only exposes the argument loads implied by FORMAL_ARGUMENTs after legalize, so that only dag combine 2 can hack on them. This causes us to miss some optimizations because datatype expansion also happens here. Exposing the loads early allows us to do optimizations on them. For example we now compile arg-cast.ll to: _foo: movl $2147483647, %eax andl 8(%esp), %eax ret where we previously produced: _foo: subl $12, %esp movsd 16(%esp), %xmm0 movsd %xmm0, (%esp) movl $2147483647, %eax andl 4(%esp), %eax addl $12, %esp ret It might also make sense to do this for ISD::CALL nodes, which have implicit stores on many targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47054 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 16 +++++++++++++++- test/CodeGen/X86/arg-cast.ll | 18 ++++++++++++++++++ 2 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/X86/arg-cast.ll diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 76e8d2824e2..e767c280d42 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -4074,8 +4074,22 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { // Create the node. SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, - DAG.getNodeValueTypes(RetVals), RetVals.size(), + DAG.getVTList(&RetVals[0], RetVals.size()), &Ops[0], Ops.size()).Val; + + // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but + // allows exposing the loads that may be part of the argument access to the + // first DAGCombiner pass. + SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG); + + // The number of results should match up, except that the lowered one may have + // an extra flag result. + assert((Result->getNumValues() == TmpRes.Val->getNumValues() || + (Result->getNumValues()+1 == TmpRes.Val->getNumValues() && + TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag)) + && "Lowering produced unexpected number of results!"); + Result = TmpRes.Val; + unsigned NumArgRegs = Result->getNumValues() - 1; DAG.setRoot(SDOperand(Result, NumArgRegs)); diff --git a/test/CodeGen/X86/arg-cast.ll b/test/CodeGen/X86/arg-cast.ll new file mode 100644 index 00000000000..37afbc6ba6d --- /dev/null +++ b/test/CodeGen/X86/arg-cast.ll @@ -0,0 +1,18 @@ +; This should compile to movl $2147483647, %eax + andl only. +; RUN: llvm-as < %s | llc | grep andl +; RUN: llvm-as < %s | llc | not grep movsd +; RUN: llvm-as < %s | llc | not grep esp +; rdar://5736574 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i686-apple-darwin8" + +define i32 @foo(double %x) nounwind { +entry: + %x15 = bitcast double %x to i64 ; [#uses=1] + %tmp713 = lshr i64 %x15, 32 ; [#uses=1] + %tmp714 = trunc i64 %tmp713 to i32 ; [#uses=1] + %tmp8 = and i32 %tmp714, 2147483647 ; [#uses=1] + ret i32 %tmp8 +} + -- 2.34.1