From 8729843d31f8e010d1deb80ad01a7488f0ab8fd1 Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Tue, 9 Dec 2014 10:58:36 +0000 Subject: [PATCH] [x86] Bring some sanity to the x86 CPU processor definitions. Notably, this adds simple micro-architecture names for the Intel CPU variants, and defines the old 'core'-based names as aliases. GCC has started to simplify their documented interface to use these names as well, so it seems like we can start to converge on a consistent pattern. I'd appreciate Intel double checking the entries that aren't yet documented widely, especially Atom (Bonnell and Silvermont), Knights Landing, and Skylake. But this change shouldn't break any existing users. Also, ran clang-format to re-format this code and it actually worked (modulo a tiny bug) so hopefully we can start to stop thinking about formatting this stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223769 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86.td | 200 +++++++++++++++++++++++++++++------------- 1 file changed, 139 insertions(+), 61 deletions(-) diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td index 49ae8b4fe3d..88f831d2642 100644 --- a/lib/Target/X86/X86.td +++ b/lib/Target/X86/X86.td @@ -240,82 +240,155 @@ def : ProcessorModel<"core2", SandyBridgeModel, def : ProcessorModel<"penryn", SandyBridgeModel, [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>; -// Atom. -def : ProcessorModel<"atom", AtomModel, - [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B, - FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP, - FeatureSlowDivide32, FeatureSlowDivide64, - FeatureCallRegIndirect, - FeatureLEAUsesAG, - FeaturePadShortFunctions]>; - -// Atom Silvermont. -def : ProcessorModel<"slm", SLMModel, [ProcIntelSLM, - FeatureSSE42, FeatureCMPXCHG16B, - FeatureMOVBE, FeaturePOPCNT, - FeaturePCLMUL, FeatureAES, - FeatureSlowDivide64, - FeatureCallRegIndirect, - FeaturePRFCHW, - FeatureSlowLEA, FeatureSlowIncDec, - FeatureSlowBTMem, FeatureFastUAMem]>; +// Atom CPUs. +class BonnellProc : ProcessorModel; +def : BonnellProc<"bonnell">; +def : BonnellProc<"atom">; // Pin the generic name to the baseline. + +class SilvermontProc : ProcessorModel; +def : SilvermontProc<"silvermont">; +def : SilvermontProc<"slm">; // Legacy alias. + // "Arrandale" along with corei3 and corei5 -def : ProcessorModel<"corei7", SandyBridgeModel, - [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem, - FeatureFastUAMem, FeaturePOPCNT, FeatureAES]>; +class NehalemProc AdditionalFeatures> + : ProcessorModel; +def : NehalemProc<"nehalem", []>; +def : NehalemProc<"corei7", [FeatureAES]>; -def : ProcessorModel<"nehalem", SandyBridgeModel, - [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem, - FeatureFastUAMem, FeaturePOPCNT]>; // Westmere is a similar machine to nehalem with some additional features. // Westmere is the corei3/i5/i7 path from nehalem to sandybridge -def : ProcessorModel<"westmere", SandyBridgeModel, - [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem, - FeatureFastUAMem, FeaturePOPCNT, FeatureAES, - FeaturePCLMUL]>; -// Sandy Bridge +class WestmereProc : ProcessorModel; +def : WestmereProc<"westmere">; + // SSE is not listed here since llvm treats AVX as a reimplementation of SSE, // rather than a superset. -def : ProcessorModel<"corei7-avx", SandyBridgeModel, - [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem, - FeatureSlowUAMem32, FeaturePOPCNT, FeatureAES, - FeaturePCLMUL]>; -// Ivy Bridge -def : ProcessorModel<"core-avx-i", SandyBridgeModel, - [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem, - FeatureSlowUAMem32, FeaturePOPCNT, FeatureAES, - FeaturePCLMUL, FeatureRDRAND, FeatureF16C, - FeatureFSGSBase]>; - -// Haswell -def : ProcessorModel<"core-avx2", HaswellModel, - [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem, - FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND, - FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, - FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM, - FeatureHLE, FeatureSlowIncDec]>; - -// Broadwell -def : ProcessorModel<"broadwell", HaswellModel, - [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem, - FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND, - FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, - FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM, - FeatureHLE, FeatureADX, FeatureRDSEED, FeatureSMAP, - FeatureSlowIncDec]>; -// KNL +class SandyBridgeProc : ProcessorModel; +def : SandyBridgeProc<"sandybridge">; +def : SandyBridgeProc<"corei7-avx">; // Legacy alias. + +class IvyBridgeProc : ProcessorModel; +def : IvyBridgeProc<"ivybridge">; +def : IvyBridgeProc<"core-avx-i">; // Legacy alias. + +class HaswellProc : ProcessorModel; +def : HaswellProc<"haswell">; +def : HaswellProc<"core-avx2">; // Legacy alias. + +class BroadwellProc : ProcessorModel; +def : BroadwellProc<"broadwell">; + // FIXME: define KNL model -def : ProcessorModel<"knl", HaswellModel, +class KnightsLandingProc : ProcessorModel; +def : KnightsLandingProc<"knl">; -// SKX // FIXME: define SKX model -def : ProcessorModel<"skx", HaswellModel, +class SkylakeProc : ProcessorModel; +def : SkylakeProc<"skylake">; +def : SkylakeProc<"skx">; // Legacy alias. + + +// AMD CPUs. def : Proc<"k6", [FeatureMMX]>; def : Proc<"k6-2", [Feature3DNow]>; -- 2.34.1