From 87ea294b0d72ef5f29c6d3ea9c9c5faa8be7abc4 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Thu, 15 Jul 2010 20:04:36 +0000 Subject: [PATCH] Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108452 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/ScheduleDAGInstrs.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index 09202f84cb2..40670da56e1 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -159,8 +159,9 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) { std::map > AliasMemUses, NonAliasMemUses; // Keep track of dangling debug references to registers. - std::pair - DanglingDebugValue[TargetRegisterInfo::FirstVirtualRegister]; + std::vector > + DanglingDebugValue(TRI->getNumRegs(), + std::make_pair(static_cast(0), 0)); // Check to see if the scheduler cares about latencies. bool UnitLatencies = ForceUnitLatencies(); @@ -172,7 +173,6 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) { // Remove any stale debug info; sometimes BuildSchedGraph is called again // without emitting the info from the previous call. DbgValueVec.clear(); - std::memset(DanglingDebugValue, 0, sizeof(DanglingDebugValue)); // Walk the list of instructions, from bottom moving up. for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin; -- 2.34.1