From 88c809fe6e82c6f2798333cb096b1272dc723b9e Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Wed, 9 Jan 2013 11:08:02 +0800 Subject: [PATCH] rk3188: initial support --- arch/arm/Kconfig | 19 +- arch/arm/Makefile | 1 + arch/arm/configs/rk3188_fpga_defconfig | 137 +++ arch/arm/mach-rk30/devices.c | 18 +- arch/arm/mach-rk30/include/mach/rk30_camera.h | 2 +- arch/arm/mach-rk3188/Kconfig | 21 + arch/arm/mach-rk3188/Makefile | 14 + arch/arm/mach-rk3188/Makefile.boot | 1 + arch/arm/mach-rk3188/board-rk30-sdk-sdmmc.c | 1 + arch/arm/mach-rk3188/board-rk3188-fpga.c | 953 ++++++++++++++++++ arch/arm/mach-rk3188/include/mach/board.h | 90 ++ arch/arm/mach-rk3188/include/mach/clkdev.h | 1 + arch/arm/mach-rk3188/include/mach/clock.h | 1 + arch/arm/mach-rk3188/include/mach/cpu.h | 1 + arch/arm/mach-rk3188/include/mach/cru.h | 4 + arch/arm/mach-rk3188/include/mach/ddr.h | 1 + .../mach-rk3188/include/mach/debug-macro.S | 1 + .../arm/mach-rk3188/include/mach/debug_uart.h | 1 + arch/arm/mach-rk3188/include/mach/dma-pl330.h | 1 + arch/arm/mach-rk3188/include/mach/dvfs.h | 1 + .../mach-rk3188/include/mach/entry-macro.S | 1 + arch/arm/mach-rk3188/include/mach/fiq.h | 1 + arch/arm/mach-rk3188/include/mach/gpio.h | 1 + arch/arm/mach-rk3188/include/mach/grf.h | 111 ++ arch/arm/mach-rk3188/include/mach/hardware.h | 4 + arch/arm/mach-rk3188/include/mach/io.h | 213 ++++ arch/arm/mach-rk3188/include/mach/iomux.h | 155 +++ arch/arm/mach-rk3188/include/mach/irqs.h | 96 ++ arch/arm/mach-rk3188/include/mach/loader.h | 1 + arch/arm/mach-rk3188/include/mach/memory.h | 15 + arch/arm/mach-rk3188/include/mach/pmu.h | 64 ++ .../mach-rk3188/include/mach/rk30_camera.h | 1 + arch/arm/mach-rk3188/include/mach/sram.h | 1 + arch/arm/mach-rk3188/include/mach/system.h | 1 + arch/arm/mach-rk3188/include/mach/timex.h | 1 + .../arm/mach-rk3188/include/mach/uncompress.h | 1 + arch/arm/mach-rk3188/include/mach/vmalloc.h | 1 + arch/arm/mach-rk3188/io.c | 72 ++ arch/arm/plat-rk/include/plat/cpu.h | 34 + arch/arm/plat-rk/sram.c | 7 +- drivers/adc/plat/Kconfig | 2 +- drivers/gpio/Makefile | 1 + drivers/gpio/gpio-rk30.c | 55 +- drivers/i2c/busses/i2c-rk30.h | 2 +- sound/soc/rk29/Kconfig | 2 +- 45 files changed, 2090 insertions(+), 22 deletions(-) create mode 100644 arch/arm/configs/rk3188_fpga_defconfig create mode 100644 arch/arm/mach-rk3188/Kconfig create mode 100644 arch/arm/mach-rk3188/Makefile create mode 100644 arch/arm/mach-rk3188/Makefile.boot create mode 100644 arch/arm/mach-rk3188/board-rk30-sdk-sdmmc.c create mode 100644 arch/arm/mach-rk3188/board-rk3188-fpga.c create mode 100644 arch/arm/mach-rk3188/include/mach/board.h create mode 100644 arch/arm/mach-rk3188/include/mach/clkdev.h create mode 100644 arch/arm/mach-rk3188/include/mach/clock.h create mode 100644 arch/arm/mach-rk3188/include/mach/cpu.h create mode 100644 arch/arm/mach-rk3188/include/mach/cru.h create mode 100644 arch/arm/mach-rk3188/include/mach/ddr.h create mode 100644 arch/arm/mach-rk3188/include/mach/debug-macro.S create mode 100644 arch/arm/mach-rk3188/include/mach/debug_uart.h create mode 100644 arch/arm/mach-rk3188/include/mach/dma-pl330.h create mode 100644 arch/arm/mach-rk3188/include/mach/dvfs.h create mode 100644 arch/arm/mach-rk3188/include/mach/entry-macro.S create mode 100644 arch/arm/mach-rk3188/include/mach/fiq.h create mode 100644 arch/arm/mach-rk3188/include/mach/gpio.h create mode 100644 arch/arm/mach-rk3188/include/mach/grf.h create mode 100644 arch/arm/mach-rk3188/include/mach/hardware.h create mode 100644 arch/arm/mach-rk3188/include/mach/io.h create mode 100644 arch/arm/mach-rk3188/include/mach/iomux.h create mode 100644 arch/arm/mach-rk3188/include/mach/irqs.h create mode 100644 arch/arm/mach-rk3188/include/mach/loader.h create mode 100644 arch/arm/mach-rk3188/include/mach/memory.h create mode 100644 arch/arm/mach-rk3188/include/mach/pmu.h create mode 100644 arch/arm/mach-rk3188/include/mach/rk30_camera.h create mode 100644 arch/arm/mach-rk3188/include/mach/sram.h create mode 100644 arch/arm/mach-rk3188/include/mach/system.h create mode 100644 arch/arm/mach-rk3188/include/mach/timex.h create mode 100644 arch/arm/mach-rk3188/include/mach/uncompress.h create mode 100644 arch/arm/mach-rk3188/include/mach/vmalloc.h create mode 100644 arch/arm/mach-rk3188/io.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6c2522812c15..50f3ae922fc0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -884,7 +884,7 @@ config ARCH_RK2928 Support for Rockchip's RK2928 SoCs. config ARCH_RK30 - bool "Rockchip RK30xx/RK31xx" + bool "Rockchip RK30xx/RK3108/RK3168" select PLAT_RK select CPU_V7 select ARM_GIC @@ -895,7 +895,21 @@ config ARCH_RK30 select ARM_ERRATA_754322 select ARM_ERRATA_775420 help - Support for Rockchip's RK30xx/RK31xx SoCs. + Support for Rockchip's RK30xx/RK3108/RK3168 SoCs. + +config ARCH_RK3188 + bool "Rockchip RK3188" + select PLAT_RK + select CPU_V7 + select ARM_GIC + select RK_PL330_DMA + select HAVE_SMP + select MIGHT_HAVE_CACHE_L2X0 + select ARM_ERRATA_764369 + select ARM_ERRATA_754322 + select ARM_ERRATA_775420 + help + Support for Rockchip's RK3188 SoCs. config PLAT_SPEAR bool "ST SPEAr" @@ -1001,6 +1015,7 @@ source "arch/arm/plat-rk/Kconfig" source "arch/arm/mach-rk29/Kconfig" source "arch/arm/mach-rk2928/Kconfig" source "arch/arm/mach-rk30/Kconfig" +source "arch/arm/mach-rk3188/Kconfig" source "arch/arm/mach-sa1100/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 43c17789695f..a159d5d84244 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -174,6 +174,7 @@ machine-$(CONFIG_ARCH_REALVIEW) := realview machine-$(CONFIG_ARCH_RK29) := rk29 machine-$(CONFIG_ARCH_RK2928) := rk2928 machine-$(CONFIG_ARCH_RK30) := rk30 +machine-$(CONFIG_ARCH_RK3188) := rk3188 machine-$(CONFIG_ARCH_RPC) := rpc machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443 machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 diff --git a/arch/arm/configs/rk3188_fpga_defconfig b/arch/arm/configs/rk3188_fpga_defconfig new file mode 100644 index 000000000000..4f5a5a1a537e --- /dev/null +++ b/arch/arm/configs/rk3188_fpga_defconfig @@ -0,0 +1,137 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_LZO=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="root" +CONFIG_INITRAMFS_COMPRESSION_GZIP=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_PANIC_TIMEOUT=1 +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_ELF_CORE is not set +CONFIG_ASHMEM=y +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_ARCH_RK3188=y +# CONFIG_DDR_TEST is not set +# CONFIG_RK29_LAST_LOG is not set +CONFIG_RK_DEBUG_UART=1 +CONFIG_MACH_RK3188_FPGA=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_FIQ_DEBUGGER=y +CONFIG_FIQ_DEBUGGER_NO_SLEEP=y +CONFIG_FIQ_DEBUGGER_CONSOLE=y +CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_COMPACTION=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init debug" +CONFIG_VFP=y +CONFIG_WAKELOCK=y +CONFIG_PM_RUNTIME=y +CONFIG_SUSPEND_TIME=y +CONFIG_NET=y +CONFIG_UNIX=y +# CONFIG_NET_ACTIVITY_STATS is not set +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_MTD=y +CONFIG_MISC_DEVICES=y +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_CONSOLE_TRANSLATIONS is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C0_CONTROLLER_RK30=y +CONFIG_I2C1_CONTROLLER_RK30=y +CONFIG_I2C2_CONTROLLER_RK30=y +# CONFIG_I2C3_RK30 is not set +# CONFIG_ADC is not set +CONFIG_EXPANDED_GPIO_NUM=0 +CONFIG_EXPANDED_GPIO_IRQ_NUM=0 +CONFIG_SPI_FPGA_GPIO_NUM=0 +CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0 +# CONFIG_HWMON is not set +# CONFIG_MFD_SUPPORT is not set +CONFIG_MEDIA_SUPPORT=y +CONFIG_VIDEO_DEV=y +CONFIG_SOC_CAMERA=y +CONFIG_SOC_CAMERA_OV2659=y +CONFIG_VIDEO_RK29=y +CONFIG_VIDEO_RK29_CAMMEM_ION=y +CONFIG_ION=y +CONFIG_ION_ROCKCHIP=y +CONFIG_FB=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_DISPLAY_SUPPORT=y +CONFIG_LCD_TD043MGEA1=y +CONFIG_FB_ROCKCHIP=y +# CONFIG_THREE_FB_BUFFER is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_VERBOSE_PROCFS is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +CONFIG_SND_SOC=y +CONFIG_SND_RK29_SOC=y +CONFIG_SND_RK29_SOC_I2S_2CH=y +CONFIG_SND_I2S_DMA_EVENT_STATIC=y +CONFIG_SND_RK29_SOC_RK1000=y +CONFIG_SND_RK29_CODEC_SOC_SLAVE=y +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_RTC_CLASS=y +# CONFIG_CMMB is not set +# CONFIG_DNOTIFY is not set +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +CONFIG_SLUB_DEBUG_ON=y +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set diff --git a/arch/arm/mach-rk30/devices.c b/arch/arm/mach-rk30/devices.c index 42c85604129b..63658836ebe0 100755 --- a/arch/arm/mach-rk30/devices.c +++ b/arch/arm/mach-rk30/devices.c @@ -29,7 +29,7 @@ #ifdef CONFIG_ADC_RK30 static struct adc_platform_data rk30_adc_pdata = { - #if defined(CONFIG_ARCH_RK3066B) + #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188) .ref_volt = 1800, //1800mV #else .ref_volt = 2500, //2500mV @@ -60,7 +60,7 @@ struct platform_device device_adc = { }; #endif -#if !defined(CONFIG_ARCH_RK3066B) +#if !defined(CONFIG_ARCH_RK3066B) && defined(IRQ_TSADC) static struct resource rk30_tsadc_resource[] = { { .start = IRQ_TSADC, @@ -80,6 +80,13 @@ static struct platform_device device_tsadc = { .num_resources = ARRAY_SIZE(rk30_tsadc_resource), .resource = rk30_tsadc_resource, }; + +static void __init rk30_init_tsadc(void) +{ + platform_device_register(&device_tsadc); +} +#else +static void __init rk30_init_tsadc(void) {} #endif static u64 dma_dmamask = DMA_BIT_MASK(32); @@ -96,7 +103,8 @@ static struct resource resource_dmac1[] = { .flags = IORESOURCE_IRQ, }, }; -#if defined(CONFIG_ARCH_RK3066B) + +#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188) static struct rk29_pl330_platdata dmac1_pdata = { .peri = { @@ -1195,9 +1203,7 @@ static int __init rk30_init_devices(void) #ifdef CONFIG_KEYS_RK29 platform_device_register(&device_keys); #endif -#if !defined(CONFIG_ARCH_RK3066B) - platform_device_register(&device_tsadc); -#endif + rk30_init_tsadc(); rk30_init_sdmmc(); #if defined(CONFIG_FIQ_DEBUGGER) && defined(DEBUG_UART_PHYS) rk_serial_debug_init(DEBUG_UART_BASE, IRQ_DEBUG_UART, IRQ_UART_SIGNAL, -1); diff --git a/arch/arm/mach-rk30/include/mach/rk30_camera.h b/arch/arm/mach-rk30/include/mach/rk30_camera.h index 9ba83825861d..39a6064fe2a1 100755 --- a/arch/arm/mach-rk30/include/mach/rk30_camera.h +++ b/arch/arm/mach-rk30/include/mach/rk30_camera.h @@ -21,7 +21,7 @@ #ifndef __ASM_ARCH_CAMERA_RK30_H_ #define __ASM_ARCH_CAMERA_RK30_H_ -#if defined(CONFIG_ARCH_RK3066B) +#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188) #define RK29_CAM_DRV_NAME "rk3066b-camera" #define RK_SUPPORT_CIF0 1 #define RK_SUPPORT_CIF1 0 diff --git a/arch/arm/mach-rk3188/Kconfig b/arch/arm/mach-rk3188/Kconfig new file mode 100644 index 000000000000..4e186db672f2 --- /dev/null +++ b/arch/arm/mach-rk3188/Kconfig @@ -0,0 +1,21 @@ +choice + prompt "Rockchip SoC Type" + +config SOC_RK3188 + bool "RK3188" + +endchoice + +if SOC_RK3188 +choice + prompt "RK3188 Board Type" + +config MACH_RK3188_TB + bool "RK3188 Top Board" + +config MACH_RK3188_FPGA + bool "RK3188 FPGA board" + select RK_FPGA + +endchoice +endif diff --git a/arch/arm/mach-rk3188/Makefile b/arch/arm/mach-rk3188/Makefile new file mode 100644 index 000000000000..d98d674555bd --- /dev/null +++ b/arch/arm/mach-rk3188/Makefile @@ -0,0 +1,14 @@ +EXTRA_CFLAGS += -Os +ifneq ($(CONFIG_RK_FPGA),y) +obj-y += ../plat-rk/clock.o +obj-y += clock_data.o +obj-y += ../mach-rk30/ddr.o +CFLAGS_ddr.o += -mthumb +obj-y += ../mach-rk30/reset.o +endif +obj-y += ../mach-rk30/common.o +CFLAGS_common.o += -DTEXT_OFFSET=$(TEXT_OFFSET) +obj-y += ../mach-rk30/devices.o +obj-y += io.o + +obj-$(CONFIG_MACH_RK3188_FPGA) += board-rk3188-fpga.o diff --git a/arch/arm/mach-rk3188/Makefile.boot b/arch/arm/mach-rk3188/Makefile.boot new file mode 100644 index 000000000000..15a97895015f --- /dev/null +++ b/arch/arm/mach-rk3188/Makefile.boot @@ -0,0 +1 @@ +include $(srctree)/arch/arm/mach-rk30/Makefile.boot diff --git a/arch/arm/mach-rk3188/board-rk30-sdk-sdmmc.c b/arch/arm/mach-rk3188/board-rk30-sdk-sdmmc.c new file mode 100644 index 000000000000..ca53d8717352 --- /dev/null +++ b/arch/arm/mach-rk3188/board-rk30-sdk-sdmmc.c @@ -0,0 +1 @@ +#include "../mach-rk30/board-rk30-sdk-sdmmc.c" diff --git a/arch/arm/mach-rk3188/board-rk3188-fpga.c b/arch/arm/mach-rk3188/board-rk3188-fpga.c new file mode 100644 index 000000000000..80bb0a9a7e27 --- /dev/null +++ b/arch/arm/mach-rk3188/board-rk3188-fpga.c @@ -0,0 +1,953 @@ +/* + * Copyright (C) 2013 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#ifdef CONFIG_VIDEO_RK29 +/*---------------- Camera Sensor Macro Define Begin ------------------------*/ +/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/ +#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */ +#define CONFIG_SENSOR_IIC_ADDR_0 0 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 4 +#define CONFIG_SENSOR_ORIENTATION_0 90 +#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_0 INVALID_GPIO +#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000 + +#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */ +#define CONFIG_SENSOR_IIC_ADDR_01 0x00 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4 +#define CONFIG_SENSOR_ORIENTATION_01 90 +#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_01 INVALID_GPIO +#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000 + +#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */ +#define CONFIG_SENSOR_IIC_ADDR_02 0x00 +#define CONFIG_SENSOR_CIF_INDEX_02 0 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4 +#define CONFIG_SENSOR_ORIENTATION_02 90 +#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO +#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000 + +#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */ +#define CONFIG_SENSOR_IIC_ADDR_1 0x60 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1 +#define CONFIG_SENSOR_ORIENTATION_1 270 +#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_1 INVALID_GPIO +#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000 + +#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */ +#define CONFIG_SENSOR_IIC_ADDR_11 0x00 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3 +#define CONFIG_SENSOR_ORIENTATION_11 270 +#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO +#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000 + +#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */ +#define CONFIG_SENSOR_IIC_ADDR_12 0x00 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3 +#define CONFIG_SENSOR_ORIENTATION_12 270 +#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO +#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000 + + +#endif //#ifdef CONFIG_VIDEO_RK29 +/*---------------- Camera Sensor Configuration Macro End------------------------*/ +#include "../../../drivers/media/video/rk30_camera.c" +/*---------------- Camera Sensor Macro Define End ---------*/ + +#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY +/***************************************************************************************** + * camera devices + * author: ddl@rock-chips.com + *****************************************************************************************/ +#ifdef CONFIG_VIDEO_RK29 +#define CONFIG_SENSOR_POWER_IOCTL_USR 0 //define this refer to your board layout +#define CONFIG_SENSOR_RESET_IOCTL_USR 0 +#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0 +#define CONFIG_SENSOR_FLASH_IOCTL_USR 0 + +static void rk_cif_power(int on) +{ + struct regulator *ldo_18,*ldo_28; + + ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif + ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif + if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)) { + printk("get cif ldo failed!\n"); + return; + } + if(on == 0) { + regulator_disable(ldo_28); + regulator_put(ldo_28); + regulator_disable(ldo_18); + regulator_put(ldo_18); + mdelay(500); + } else { + regulator_set_voltage(ldo_28, 2800000, 2800000); + regulator_enable(ldo_28); + // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28)); + regulator_put(ldo_28); + + regulator_set_voltage(ldo_18, 1800000, 1800000); + // regulator_set_suspend_voltage(ldo, 1800000); + regulator_enable(ldo_18); + // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18)); + regulator_put(ldo_18); + } +} + +#if CONFIG_SENSOR_POWER_IOCTL_USR +static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on) +{ + //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!"; + rk_cif_power(on); +} +#endif + +#if CONFIG_SENSOR_RESET_IOCTL_USR +static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on) +{ + #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!"; +} +#endif + +#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR +static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on) +{ + #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!"; +} +#endif + +#if CONFIG_SENSOR_FLASH_IOCTL_USR +static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on) +{ + #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!"; +} +#endif + +static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = { + #if CONFIG_SENSOR_POWER_IOCTL_USR + .sensor_power_cb = sensor_power_usr_cb, + #else + .sensor_power_cb = NULL, + #endif + + #if CONFIG_SENSOR_RESET_IOCTL_USR + .sensor_reset_cb = sensor_reset_usr_cb, + #else + .sensor_reset_cb = NULL, + #endif + + #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR + .sensor_powerdown_cb = sensor_powerdown_usr_cb, + #else + .sensor_powerdown_cb = NULL, + #endif + + #if CONFIG_SENSOR_FLASH_IOCTL_USR + .sensor_flash_cb = sensor_flash_usr_cb, + #else + .sensor_flash_cb = NULL, + #endif +}; + +#if CONFIG_SENSOR_IIC_ADDR_0 +static struct reginfo_t rk_init_data_sensor_reg_0[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_0[] = +{ + {0x0000, 0x00,0,0} +}; +#endif + +#if CONFIG_SENSOR_IIC_ADDR_1 +static struct reginfo_t rk_init_data_sensor_reg_1[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_1[] = +{ + {0x0000, 0x00,0,0} +}; +#endif +#if CONFIG_SENSOR_IIC_ADDR_01 +static struct reginfo_t rk_init_data_sensor_reg_01[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_01[] = +{ + {0x0000, 0x00,0,0} +}; +#endif +#if CONFIG_SENSOR_IIC_ADDR_02 +static struct reginfo_t rk_init_data_sensor_reg_02[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_02[] = +{ + {0x0000, 0x00,0,0} +}; +#endif +#if CONFIG_SENSOR_IIC_ADDR_11 +static struct reginfo_t rk_init_data_sensor_reg_11[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_11[] = +{ + {0x0000, 0x00,0,0} +}; +#endif +#if CONFIG_SENSOR_IIC_ADDR_12 +static struct reginfo_t rk_init_data_sensor_reg_12[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_12[] = +{ + {0x0000, 0x00,0,0} +}; +#endif +static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] = +{ + #if CONFIG_SENSOR_IIC_ADDR_0 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_0, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + #if CONFIG_SENSOR_IIC_ADDR_1 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_1, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + #if CONFIG_SENSOR_IIC_ADDR_01 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_01, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + #if CONFIG_SENSOR_IIC_ADDR_02 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_02, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + #if CONFIG_SENSOR_IIC_ADDR_11 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_11, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + #if CONFIG_SENSOR_IIC_ADDR_12 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_12, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + + }; +#include "../../../drivers/media/video/rk30_camera.c" + +#endif /* CONFIG_VIDEO_RK29 */ + +#define RK_FB_MEM_SIZE 3*SZ_1M + +#define LCD_CS_MUX_NAME GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME +#define LCD_CS_PIN RK30_PIN2_PA7 +#define LCD_CS_VALUE GPIO_HIGH + +#define LCD_EN_MUX_NAME GPIO2D7_TESTCLOCKOUT_NAME +#define LCD_EN_PIN RK30_PIN2_PD7 +#define LCD_EN_VALUE GPIO_LOW + +static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting) +{ + int ret = 0; + ret = gpio_request(LCD_CS_PIN, NULL); + if (ret != 0) + { + gpio_free(LCD_CS_PIN); + printk(KERN_ERR "request lcd cs pin fail!\n"); + return -1; + } + else + { + gpio_direction_output(LCD_CS_PIN, LCD_CS_VALUE); + } + ret = gpio_request(LCD_EN_PIN, NULL); + if (ret != 0) + { + gpio_free(LCD_EN_PIN); + printk(KERN_ERR "request lcd en pin fail!\n"); + return -1; + } + else + { + gpio_direction_output(LCD_EN_PIN, LCD_EN_VALUE); + } + return 0; +} +static int rk_fb_io_disable(void) +{ + gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE? 0:1); + gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE? 0:1); + return 0; +} +static int rk_fb_io_enable(void) +{ + gpio_set_value(LCD_CS_PIN, LCD_CS_VALUE); + gpio_set_value(LCD_EN_PIN, LCD_EN_VALUE); + return 0; +} + +struct rk29fb_info lcdc0_screen_info = { + .prop = PRMRY, //primary display device + .io_init = rk_fb_io_init, + .io_disable = rk_fb_io_disable, + .io_enable = rk_fb_io_enable, + .set_screen_info = set_lcd_info, +}; + +struct rk29fb_info lcdc1_screen_info = { + #if defined(CONFIG_HDMI_RK30) + .prop = EXTEND, //extend display device + .lcd_info = NULL, + .set_screen_info = hdmi_init_lcdc, + #endif +}; + +static struct resource resource_fb[] = { + [0] = { + .name = "fb0 buf", + .start = 0, + .end = 0,//RK30_FB0_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "ipp buf", //for rotate + .start = 0, + .end = 0,//RK30_FB0_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .name = "fb2 buf", + .start = 0, + .end = 0,//RK30_FB0_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device device_fb = { + .name = "rk-fb", + .id = -1, + .num_resources = ARRAY_SIZE(resource_fb), + .resource = resource_fb, +}; + +static struct i2c_board_info __initdata i2c0_info[] = { +#if defined (CONFIG_SND_SOC_RK1000) + { + .type = "rk1000_i2c_codec", + .addr = 0x60, + .flags = 0, + }, + { + .type = "rk1000_control", + .addr = 0x40, + .flags = 0, + }, +#endif +}; + +static struct i2c_board_info __initdata i2c1_info[] = { +}; + +static struct i2c_board_info __initdata i2c2_info[] = { +}; + +static struct i2c_board_info __initdata i2c3_info[] = { +}; + +static struct i2c_board_info __initdata i2c_gpio_info[] = { +}; + +static void __init rk30_i2c_register_board_info(void) +{ + i2c_register_board_info(0, i2c0_info, ARRAY_SIZE(i2c0_info)); + i2c_register_board_info(1, i2c1_info, ARRAY_SIZE(i2c1_info)); + i2c_register_board_info(2, i2c2_info, ARRAY_SIZE(i2c2_info)); + i2c_register_board_info(3, i2c3_info, ARRAY_SIZE(i2c3_info)); +} +//end of i2c + +static struct spi_board_info board_spi_devices[] = { +}; + +/*********************************************************** +* rk30 backlight +************************************************************/ +#define PWM_ID 1 +#define PWM_MUX_NAME GPIO0A3_PWM0_NAME +#define PWM_MUX_MODE GPIO0A_PWM0 +#define PWM_MUX_MODE_GPIO GPIO0A_GPIO0A3 +#define PWM_GPIO RK30_PIN0_PA3 +#define PWM_EFFECT_VALUE 1 + +#define LCD_DISP_ON_PIN + +#ifdef LCD_DISP_ON_PIN + +#define BL_EN_PIN RK30_PIN6_PB3 +#define BL_EN_VALUE GPIO_HIGH +#endif +static int rk29_backlight_io_init(void) +{ + int ret = 0; + return ret; +} + +static int rk29_backlight_io_deinit(void) +{ + int ret = 0; + return ret; +} + +static int rk29_backlight_pwm_suspend(void) +{ + int ret = 0; + return ret; +} + +static int rk29_backlight_pwm_resume(void) +{ + return 0; +} + +static struct rk29_bl_info rk29_bl_info = { + .pwm_id = PWM_ID, + .bl_ref = PWM_EFFECT_VALUE, + .io_init = rk29_backlight_io_init, + .io_deinit = rk29_backlight_io_deinit, + .pwm_suspend = rk29_backlight_pwm_suspend, + .pwm_resume = rk29_backlight_pwm_resume, +}; + +static struct platform_device rk29_device_backlight = { + .name = "rk29_backlight", + .id = -1, + .dev = { + .platform_data = &rk29_bl_info, + } +}; + +/*********************************************************** +* rk30 ion device +************************************************************/ +#define ION_RESERVE_SIZE (8 * SZ_1M) +static struct ion_platform_data rk30_ion_pdata = { + .nr = 1, + .heaps = { + { + .type = ION_HEAP_TYPE_CARVEOUT, + .id = ION_NOR_HEAP_ID, + .name = "norheap", + .size = ION_RESERVE_SIZE, + } + }, +}; + +static struct platform_device device_ion = { + .name = "ion-rockchip", + .id = 0, + .dev = { + .platform_data = &rk30_ion_pdata, + }, +}; + +static struct platform_device *devices[] __initdata = { + &device_fb, + &rk29_device_backlight, + &device_ion, +}; + +static void __init fpga_board_init(void) +{ + rk30_i2c_register_board_info(); + spi_register_board_info(board_spi_devices, ARRAY_SIZE(board_spi_devices)); + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +static void __init fpga_reserve(void) +{ +#if defined(CONFIG_FB_ROCKCHIP) + resource_fb[0].start = board_mem_reserve_add("fb0", RK_FB_MEM_SIZE); + resource_fb[0].end = resource_fb[0].start + RK_FB_MEM_SIZE - 1; +#endif +#ifdef CONFIG_ION + rk30_ion_pdata.heaps[0].base = board_mem_reserve_add("ion", ION_RESERVE_SIZE); +#endif +#ifdef CONFIG_VIDEO_RK29 + rk30_camera_request_reserve_mem(); +#endif + board_mem_reserved(); +} + +#include + +static struct rk29_keys_button key_button[] = { + { + .desc = "menu", + .code = EV_MENU, + .gpio = RK30_PIN3_PB2, + .active_low = PRESS_LEV_LOW, + }, + { + .desc = "vol+", + .code = KEY_VOLUMEUP, + .gpio = RK30_PIN3_PB1, + .active_low = PRESS_LEV_LOW, + }, + { + .desc = "vol-", + .code = KEY_VOLUMEDOWN, + .gpio = RK30_PIN3_PB0, + .active_low = PRESS_LEV_LOW, + }, + { + .desc = "home", + .code = KEY_HOME, + .gpio = RK30_PIN3_PB3, + .active_low = PRESS_LEV_LOW, + }, + { + .desc = "esc", + .code = KEY_BACK, + .gpio = RK30_PIN3_PB4, + .active_low = PRESS_LEV_LOW, + }, + { + .desc = "key6", + .code = KEY_CAMERA, + .gpio = RK30_PIN3_PB5, + .active_low = PRESS_LEV_LOW, + }, +}; + +struct rk29_keys_platform_data rk29_keys_pdata = { + .buttons = key_button, + .nbuttons = ARRAY_SIZE(key_button), + .chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1 +}; + +static void __init fpga_fixup(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mi->nr_banks = 1; + mi->bank[0].start = PLAT_PHYS_OFFSET; + mi->bank[0].size = SZ_128M; +} + +static void __init fpga_map_io(void) +{ + rk30_map_common_io(); + rk29_setup_early_printk(); + rk29_sram_init(); + board_clock_init(); +} + +MACHINE_START(RK30, "RK30board") + .boot_params = PLAT_PHYS_OFFSET + 0x800, + .fixup = fpga_fixup, + .reserve = &fpga_reserve, + .map_io = fpga_map_io, + .init_irq = rk30_init_irq, + .init_machine = fpga_board_init, +MACHINE_END + +#include +static void fpga_reset(char mode, const char *cmd) +{ + sram_printascii("\nfpga reset\n"); + while (1); +} +void (*arch_reset)(char, const char *) = fpga_reset; + +int ddr_init(uint32_t dram_type, uint32_t freq) +{ + return 0; +} + +uint32_t ddr_get_cap(void) +{ + return SZ_128M; +} + +struct cpufreq_frequency_table *dvfs_get_freq_volt_table(struct clk *clk) +{ + return NULL; +} + +#include + +struct clk { + const char *name; + unsigned long rate; +}; + +static struct clk xin24m = { + .name = "xin24m", + .rate = 24000000, +}; + +static struct clk xin12m = { + .name = "xin12m", + .rate = 12000000, +}; + +#define CLK(dev, con, ck) \ + { \ + .dev_id = dev, \ + .con_id = con, \ + .clk = ck, \ + } + +static struct clk_lookup clks[] = { + CLK("rk30_i2c.0", "i2c", &xin24m), + CLK("rk30_i2c.1", "i2c", &xin24m), + CLK("rk30_i2c.2", "i2c", &xin24m), + CLK("rk30_i2c.3", "i2c", &xin24m), + CLK("rk30_i2c.4", "i2c", &xin24m), + CLK("rk29xx_spim.0", "spi", &xin24m), + CLK("rk29xx_spim.1", "spi", &xin24m), + + CLK("rk_serial.0", "uart_div", &xin24m), + CLK("rk_serial.0", "uart_frac_div", &xin24m), + CLK("rk_serial.0", "uart", &xin24m), + CLK("rk_serial.0", "pclk_uart", &xin24m), + CLK("rk_serial.1", "uart_div", &xin24m), + CLK("rk_serial.1", "uart_frac_div", &xin24m), + CLK("rk_serial.1", "uart", &xin24m), + CLK("rk_serial.1", "pclk_uart", &xin24m), + CLK("rk_serial.2", "uart_div", &xin24m), + CLK("rk_serial.2", "uart_frac_div", &xin24m), + CLK("rk_serial.2", "uart", &xin24m), + CLK("rk_serial.2", "pclk_uart", &xin24m), + + CLK("rk29_i2s.1", "i2s_div", &xin24m), + CLK("rk29_i2s.1", "i2s_frac_div", &xin24m), + CLK("rk29_i2s.1", "i2s", &xin12m), + CLK("rk29_i2s.1", "hclk_i2s", &xin24m), + + CLK("rk29_sdmmc.0","mmc",&xin24m), + CLK("rk29_sdmmc.0","hclk_mmc",&xin24m), + CLK("rk29_sdmmc.1","mmc",&xin24m), + CLK("rk29_sdmmc.1","hclk_mmc",&xin24m), + + CLK(NULL,"pd_lcdc0",&xin24m), + CLK(NULL,"hclk_lcdc0",&xin24m), + CLK(NULL,"aclk_lcdc0",&xin24m), + CLK(NULL,"dclk_lcdc0",&xin24m), + CLK(NULL,"pd_lcdc1",&xin24m), + CLK(NULL,"hclk_lcdc1",&xin24m), + CLK(NULL,"aclk_lcdc1",&xin24m), + CLK(NULL,"dclk_lcdc1",&xin24m), + + CLK(NULL,"pd_cif0",&xin24m), + CLK(NULL,"aclk_cif0",&xin24m), + CLK(NULL,"hclk_cif0",&xin24m), + CLK(NULL,"cif0_in",&xin24m), + CLK(NULL,"cif0_out",&xin24m), + + CLK(NULL,"pwm01",&xin24m), +}; + +static void __init fpga_clock_init(void) +{ + struct clk_lookup *lk; + + for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) { + clkdev_add(lk); + } +} + +void __init board_clock_init(void) +{ + fpga_clock_init(); +} + +int __init clk_disable_unused(void) +{ + return 0; +} + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + if (clk) + return clk->rate; + else + return 24000000; +} +EXPORT_SYMBOL(clk_get_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + return 0; +} +EXPORT_SYMBOL(clk_set_rate); + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + return 0; +} +EXPORT_SYMBOL(clk_set_parent); + diff --git a/arch/arm/mach-rk3188/include/mach/board.h b/arch/arm/mach-rk3188/include/mach/board.h new file mode 100644 index 000000000000..294f021625c9 --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/board.h @@ -0,0 +1,90 @@ +#ifndef __MACH_BOARD_H +#define __MACH_BOARD_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +void __init rk30_map_common_io(void); +void __init rk30_init_irq(void); +void __init rk30_map_io(void); +struct machine_desc; +void __init rk30_fixup(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi); +void __init rk30_clock_data_init(unsigned long gpll,unsigned long cpll,u32 flags); + +#ifdef CONFIG_RK30_PWM_REGULATOR +void rk30_pwm_suspend_voltage_set(void); +void rk30_pwm_resume_voltage_set(void); +void __sramfunc rk30_pwm_logic_suspend_voltage(void); + void __sramfunc rk30_pwm_logic_resume_voltage(void); +#endif + +extern struct sys_timer rk30_timer; + +enum _periph_pll { + periph_pll_1485mhz = 148500000, + periph_pll_297mhz = 297000000, + periph_pll_300mhz = 300000000, + periph_pll_594mhz = 594000000, + periph_pll_1188mhz = 1188000000, /* for box*/ +}; +enum _codec_pll { + codec_pll_360mhz = 360000000, /* for HDMI */ + codec_pll_408mhz = 408000000, + codec_pll_456mhz = 456000000, + codec_pll_504mhz = 504000000, + codec_pll_552mhz = 552000000, /* for HDMI */ + codec_pll_600mhz = 600000000, + codec_pll_742_5khz = 742500000, + codec_pll_768mhz = 768000000, + codec_pll_798mhz = 798000000, + codec_pll_1188mhz = 1188000000, + codec_pll_1200mhz = 1200000000, +}; + +//has extern 27mhz +#define CLK_FLG_EXT_27MHZ (1<<0) +//max i2s rate +#define CLK_FLG_MAX_I2S_12288KHZ (1<<1) +#define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2) +#define CLK_FLG_MAX_I2S_24576KHZ (1<<3) +#define CLK_FLG_MAX_I2S_49152KHZ (1<<4) +//uart 1m\3m +#define CLK_FLG_UART_1_3M (1<<5) +#define CLK_CPU_HPCLK_11 (1<<6) + + +#ifdef CONFIG_RK29_VMAC + +#define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/) +#define periph_pll_default periph_pll_300mhz +#define codec_pll_default codec_pll_1188mhz + +#else + + +#define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/) + +#if (RK30_CLOCKS_DEFAULT_FLAGS&CLK_FLG_UART_1_3M) +#define codec_pll_default codec_pll_768mhz +#else +#define codec_pll_default codec_pll_1200mhz +#endif +#define periph_pll_default periph_pll_297mhz + +#endif + + + + + + +#endif diff --git a/arch/arm/mach-rk3188/include/mach/clkdev.h b/arch/arm/mach-rk3188/include/mach/clkdev.h new file mode 100644 index 000000000000..c0cf3286a662 --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/clkdev.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk3188/include/mach/clock.h b/arch/arm/mach-rk3188/include/mach/clock.h new file mode 100644 index 000000000000..94b35428fd3c --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/clock.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk3188/include/mach/cpu.h b/arch/arm/mach-rk3188/include/mach/cpu.h new file mode 100644 index 000000000000..40195f1ccdc9 --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/cpu.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk3188/include/mach/cru.h b/arch/arm/mach-rk3188/include/mach/cru.h new file mode 100644 index 000000000000..f37a897bb419 --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/cru.h @@ -0,0 +1,4 @@ +#ifndef __MACH_CRU_H +#define __MACH_CRU_H + +#endif diff --git a/arch/arm/mach-rk3188/include/mach/ddr.h b/arch/arm/mach-rk3188/include/mach/ddr.h new file mode 100644 index 000000000000..865e1f7d88a8 --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/ddr.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk3188/include/mach/debug-macro.S b/arch/arm/mach-rk3188/include/mach/debug-macro.S new file mode 100644 index 000000000000..00d5467951fe --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/debug-macro.S @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk3188/include/mach/debug_uart.h b/arch/arm/mach-rk3188/include/mach/debug_uart.h new file mode 100644 index 000000000000..82ac931c9c4e --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/debug_uart.h @@ -0,0 +1 @@ +#include <../../mach-rk30/include/mach/debug_uart.h> diff --git a/arch/arm/mach-rk3188/include/mach/dma-pl330.h b/arch/arm/mach-rk3188/include/mach/dma-pl330.h new file mode 100644 index 000000000000..9afde6529658 --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/dma-pl330.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk3188/include/mach/dvfs.h b/arch/arm/mach-rk3188/include/mach/dvfs.h new file mode 100644 index 000000000000..0e88605f06c4 --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/dvfs.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk3188/include/mach/entry-macro.S b/arch/arm/mach-rk3188/include/mach/entry-macro.S new file mode 100644 index 000000000000..d5136aa47385 --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/entry-macro.S @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk3188/include/mach/fiq.h b/arch/arm/mach-rk3188/include/mach/fiq.h new file mode 100644 index 000000000000..31e146e6f1f4 --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/fiq.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk3188/include/mach/gpio.h b/arch/arm/mach-rk3188/include/mach/gpio.h new file mode 100644 index 000000000000..27ba63d457c1 --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/gpio.h @@ -0,0 +1 @@ +#include <../../mach-rk30/include/mach/gpio.h> diff --git a/arch/arm/mach-rk3188/include/mach/grf.h b/arch/arm/mach-rk3188/include/mach/grf.h new file mode 100644 index 000000000000..288e813249dd --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/grf.h @@ -0,0 +1,111 @@ +#ifndef __MACH_GRF_H +#define __MACH_GRF_H + +#define GRF_GPIO0L_DIR 0x0000 +#define GRF_GPIO0H_DIR 0x0004 +#define GRF_GPIO1L_DIR 0x0008 +#define GRF_GPIO1H_DIR 0x000c +#define GRF_GPIO2L_DIR 0x0010 +#define GRF_GPIO2H_DIR 0x0014 +#define GRF_GPIO3L_DIR 0x0018 +#define GRF_GPIO3H_DIR 0x001c +#define GRF_GPIO0L_DO 0x0020 +#define GRF_GPIO0H_DO 0x0024 +#define GRF_GPIO1L_DO 0x0028 +#define GRF_GPIO1H_DO 0x002c +#define GRF_GPIO2L_DO 0x0030 +#define GRF_GPIO2H_DO 0x0034 +#define GRF_GPIO3L_DO 0x0038 +#define GRF_GPIO3H_DO 0x003c +#define GRF_GPIO0L_EN 0x0040 +#define GRF_GPIO0H_EN 0x0044 +#define GRF_GPIO1L_EN 0x0048 +#define GRF_GPIO1H_EN 0x004c +#define GRF_GPIO2L_EN 0x0050 +#define GRF_GPIO2H_EN 0x0054 +#define GRF_GPIO3L_EN 0x0058 +#define GRF_GPIO3H_EN 0x005c + + +#define GRF_GPIO0C_IOMUX 0x0068 +#define GRF_GPIO0D_IOMUX 0x006c +#define GRF_GPIO1A_IOMUX 0x0070 +#define GRF_GPIO1B_IOMUX 0x0074 +#define GRF_GPIO1C_IOMUX 0x0078 +#define GRF_GPIO1D_IOMUX 0x007c +#define GRF_GPIO2A_IOMUX 0x0080 +#define GRF_GPIO2B_IOMUX 0x0084 +#define GRF_GPIO2C_IOMUX 0x0088 +#define GRF_GPIO2D_IOMUX 0x008c +#define GRF_GPIO3A_IOMUX 0x0090 +#define GRF_GPIO3B_IOMUX 0x0094 +#define GRF_GPIO3C_IOMUX 0x0098 +#define GRF_GPIO3D_IOMUX 0x009c +#define GRF_SOC_CON0 0x00a0 +#define GRF_SOC_CON1 0x00a4 +#define GRF_SOC_CON2 0x00a8 +#define GRF_SOC_STATUS0 0x00ac +#define GRF_DMAC1_CON0 0x00b0 +#define GRF_DMAC1_CON1 0x00b4 +#define GRF_DMAC1_CON2 0x00b8 +#define GRF_DMAC2_CON0 0x00bc +#define GRF_DMAC2_CON1 0x00c0 +#define GRF_DMAC2_CON2 0x00c4 +#define GRF_DMAC2_CON3 0x00c8 +#define GRF_CPU_CON0 0x00cc +#define GRF_CPU_CON1 0x00d0 +#define GRF_CPU_CON2 0x00d4 +#define GRF_CPU_CON3 0x00d8 +#define GRF_CPU_CON4 0x00dc +#define GRF_CPU_CON5 0x00e0 + + +#define GRF_DDRC_CON0 0x00ec +#define GRF_DDRC_STAT 0x00f0 +#define GRF_IO_CON0 0x00f4 +#define GRF_IO_CON1 0x00f8 +#define GRF_IO_CON2 0x00fc +#define GRF_IO_CON3 0x0100 +#define GRF_IO_CON4 0x0104 +#define GRF_SOC_STATUS1 0x0108 +#define GRF_UOC0_CON0 0x010c +#define GRF_UOC0_CON1 0x0110 +#define GRF_UOC0_CON2 0x0114 +#define GRF_UOC0_CON3 0x0118 +#define GRF_UOC1_CON0 0x011c +#define GRF_UOC1_CON1 0x0120 +#define GRF_UOC1_CON2 0x0124 +#define GRF_UOC1_CON3 0x0128 +#define GRF_UOC2_CON0 0x012c +#define GRF_UOC2_CON1 0x0130 + +#define GRF_UOC3_CON0 0x0138 +#define GRF_UOC3_CON1 0x013c +#define GRF_HSIC_STAT 0x0140 +#define GRF_OS_REG0 0x0144 +#define GRF_OS_REG1 0x0148 +#define GRF_OS_REG2 0x014c +#define GRF_OS_REG3 0x0150 +#define GRF_OS_REG4 0x0154 +#define GRF_OS_REG5 0x0158 +#define GRF_OS_REG6 0x015c +#define GRF_OS_REG7 0x0160 +#define GRF_GPIO0B_PULL 0x0164 +#define GRF_GPIO0C_PULL 0x0168 +#define GRF_GPIO0D_PULL 0x016c +#define GRF_GPIO1A_PULL 0x0170 +#define GRF_GPIO1B_PULL 0x0174 +#define GRF_GPIO1C_PULL 0x0178 +#define GRF_GPIO1D_PULL 0x017c +#define GRF_GPIO2A_PULL 0x0180 +#define GRF_GPIO2B_PULL 0x0184 +#define GRF_GPIO2C_PULL 0x0188 +#define GRF_GPIO2D_PULL 0x018c +#define GRF_GPIO3A_PULL 0x0190 +#define GRF_GPIO3B_PULL 0x0194 +#define GRF_GPIO3C_PULL 0x0198 +#define GRF_GPIO3D_PULL 0x019c +#define GRF_FLASH_DATA_PULL 0x01a0 +#define GRF_FLASH_CMD_PULL 0x01a4 + +#endif diff --git a/arch/arm/mach-rk3188/include/mach/hardware.h b/arch/arm/mach-rk3188/include/mach/hardware.h new file mode 100644 index 000000000000..9e84f2395d97 --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/hardware.h @@ -0,0 +1,4 @@ +#ifndef __MACH_HARDWARE_H +#define __MACH_HARDWARE_H + +#endif diff --git a/arch/arm/mach-rk3188/include/mach/io.h b/arch/arm/mach-rk3188/include/mach/io.h new file mode 100644 index 000000000000..fab471c3d48c --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/io.h @@ -0,0 +1,213 @@ +#ifndef __MACH_IO_H +#define __MACH_IO_H + +#include + +/* + * RK3188 IO memory map: + * + * Virt Phys Size What + * --------------------------------------------------------------------------- + * FEA00000 10000000 1M + * FEB00000 10100000 1M + * FEC00000 10200000 176K + * 10300000 1M Peri AXI BUS + * FEC80000 10500000 16K NANDC + * FECE0000 1FFE0000 128K CPU Debug + * FED00000 20000000 640K + * FEF00000 10080000/0 32K SRAM + */ + +#define RK30_IO_TO_VIRT0(pa) IOMEM(pa + (0xFEA00000 - 0x10000000)) +#define RK30_IO_TO_VIRT1(pa) IOMEM(pa + (0xFED00000 - 0x20000000)) + +#define RK30_IMEM_PHYS 0x10080000 +#define RK30_IMEM_BASE IOMEM(0xFEF00000) +#define RK30_IMEM_NONCACHED RK30_IO_TO_VIRT0(RK30_IMEM_PHYS) +#define RK3188_IMEM_SIZE SZ_32K +#define RK30_GPU_PHYS 0x10090000 +#define RK30_GPU_SIZE SZ_64K + +#define RK3188_ROM_PHYS 0x10120000 +#define RK30_ROM_BASE IOMEM(0xFEB00000) +#define RK30_ROM_SIZE SZ_16K + +#define RK30_VCODEC_PHYS 0x10104000 +#define RK30_VCODEC_SIZE SZ_16K +#define RK30_CIF0_PHYS 0x10108000 +#define RK30_CIF0_SIZE SZ_8K + +#define RK30_LCDC0_PHYS 0x1010c000 +#define RK30_LCDC0_SIZE SZ_8K +#define RK30_LCDC1_PHYS 0x1010e000 +#define RK30_LCDC1_SIZE SZ_8K +#define RK30_IPP_PHYS 0x10110000 +#define RK30_IPP_SIZE SZ_16K +#define RK30_RGA_PHYS 0x10114000 +#define RK30_RGA_SIZE SZ_8K + +#define RK30_I2S1_2CH_PHYS 0x1011a000 +#define RK30_I2S1_2CH_SIZE SZ_8K +#define RK30_SPDIF_PHYS 0x1011e000 +#define RK30_SPDIF_SIZE SZ_8K + +#define RK30_UART0_PHYS 0x10124000 +#define RK30_UART0_BASE RK30_IO_TO_VIRT0(RK30_UART0_PHYS) +#define RK30_UART0_SIZE SZ_8K +#define RK30_UART1_PHYS 0x10126000 +#define RK30_UART1_BASE RK30_IO_TO_VIRT0(RK30_UART1_PHYS) +#define RK30_UART1_SIZE SZ_8K +#define RK30_CPU_AXI_BUS_PHYS 0x10128000 +#define RK30_CPU_AXI_BUS_BASE RK30_IO_TO_VIRT0(RK30_CPU_AXI_BUS_PHYS) +#define RK30_CPU_AXI_BUS_SIZE SZ_32K + +#define RK30_L2C_PHYS 0x10138000 +#define RK30_L2C_BASE RK30_IO_TO_VIRT0(RK30_L2C_PHYS) +#define RK30_L2C_SIZE SZ_16K +#define RK30_SCU_PHYS 0x1013c000 +#define RK30_SCU_BASE RK30_IO_TO_VIRT0(RK30_SCU_PHYS) +#define RK30_SCU_SIZE SZ_256 +#define RK30_GICC_PHYS 0x1013c100 +#define RK30_GICC_BASE RK30_IO_TO_VIRT0(RK30_GICC_PHYS) +#define RK30_GICC_SIZE SZ_256 +#define RK30_GTIMER_PHYS 0x1013c200 +#define RK30_GTIMER_BASE RK30_IO_TO_VIRT0(RK30_GTIMER_PHYS) +#define RK30_GTIMER_SIZE SZ_1K +#define RK30_PTIMER_PHYS 0x1013c600 +#define RK30_PTIMER_BASE RK30_IO_TO_VIRT0(RK30_PTIMER_PHYS) +#define RK30_PTIMER_SIZE (SZ_2K + SZ_512) +#define RK30_GICD_PHYS 0x1013d000 +#define RK30_GICD_BASE RK30_IO_TO_VIRT0(RK30_GICD_PHYS) +#define RK30_GICD_SIZE SZ_2K + +#define RK30_CORE_PHYS RK30_L2C_PHYS +#define RK30_CORE_BASE RK30_IO_TO_VIRT0(RK30_CORE_PHYS) +#define RK30_CORE_SIZE (RK30_L2C_SIZE + SZ_8K) + +#define RK30_USBHOST11_PHYS 0x10140000 +#define RK30_USBHOST11_SIZE SZ_256K +#define RK30_USBOTG20_PHYS 0x10180000 +#define RK30_USBOTG20_SIZE SZ_256K +#define RK30_USBHOST20_PHYS 0x101c0000 +#define RK30_USBHOST20_SIZE SZ_256K + +#define RK30_MAC_PHYS 0x10204000 +#define RK30_MAC_SIZE SZ_16K + +#define RK30_HSADC_PHYS 0x10210000 +#define RK30_HSADC_SIZE SZ_16K +#define RK30_SDMMC0_PHYS 0x10214000 +#define RK30_SDMMC0_SIZE SZ_16K +#define RK30_SDIO_PHYS 0x10218000 +#define RK30_SDIO_SIZE SZ_16K +#define RK30_EMMC_PHYS 0x1021c000 +#define RK30_EMMC_SIZE SZ_16K +#define RK30_PIDF_PHYS 0x10220000 +#define RK30_PIDF_SIZE SZ_16K + +#define RK30_HSIC_PHYS 0x10240000 +#define RK30_HSIC_SIZE SZ_256K + +#define RK30_PERI_AXI_BUS_PHYS 0x10300000 +#define RK30_PERI_AXI_BUS_SIZE SZ_1M + +#define RK30_GPS_PHYS 0x10400000 +#define RK30_GPS_SIZE SZ_1M +#define RK30_NANDC_PHYS 0x10500000 +#define RK30_NANDC_SIZE SZ_16K + +#define RK30_SMC_BANK0_PHYS 0x11000000 +#define RK30_SMC_BANK0_SIZE SZ_16M +#define RK30_SMC_BANK1_PHYS 0x12000000 +#define RK30_SMC_BANK1_SIZE SZ_16M + +#define RK30_CPU_DEBUG_PHYS 0x1FFE0000 +#define RK30_CPU_DEBUG_SIZE SZ_128K +#define RK30_CRU_PHYS 0x20000000 +#define RK30_CRU_BASE RK30_IO_TO_VIRT1(RK30_CRU_PHYS) +#define RK30_CRU_SIZE SZ_16K +#define RK30_PMU_PHYS 0x20004000 +#define RK30_PMU_BASE RK30_IO_TO_VIRT1(RK30_PMU_PHYS) +#define RK30_PMU_SIZE SZ_16K +#define RK30_GRF_PHYS 0x20008000 +#define RK30_GRF_BASE RK30_IO_TO_VIRT1(RK30_GRF_PHYS) +#define RK30_GRF_SIZE SZ_8K +#define RK30_GPIO0_PHYS 0x2000a000 +#define RK30_GPIO0_BASE RK30_IO_TO_VIRT1(RK30_GPIO0_PHYS) +#define RK30_GPIO0_SIZE SZ_8K + +#define RK3188_TIMER3_PHYS 0x2000e000 +#define RK3188_TIMER3_BASE RK30_IO_TO_VIRT1(RK3188_TIMER3_PHYS) +#define RK3188_TIMER3_SIZE SZ_8K +#define RK30_EFUSE_PHYS 0x20010000 +#define RK30_EFUSE_SIZE SZ_16K +#define RK30_TZPC_PHYS 0x20014000 +#define RK30_TZPC_SIZE SZ_16K +#define RK30_DMACS1_PHYS 0x20018000 +#define RK30_DMACS1_SIZE SZ_16K +#define RK30_DMAC1_PHYS 0x2001c000 +#define RK30_DMAC1_SIZE SZ_16K +#define RK30_DDR_PCTL_PHYS 0x20020000 +#define RK30_DDR_PCTL_BASE RK30_IO_TO_VIRT1(RK30_DDR_PCTL_PHYS) +#define RK30_DDR_PCTL_SIZE SZ_16K + +#define RK30_I2C0_PHYS 0x2002c000 +#define RK30_I2C0_SIZE SZ_8K +#define RK30_I2C1_PHYS 0x2002e000 +#define RK30_I2C1_BASE RK30_IO_TO_VIRT1(RK30_I2C1_PHYS) +#define RK30_I2C1_SIZE SZ_8K +#define RK30_PWM01_PHYS 0x20030000 +#define RK30_PWM01_BASE RK30_IO_TO_VIRT1(RK30_PWM01_PHYS) +#define RK30_PWM01_SIZE SZ_16K + +#define RK30_TIMER0_PHYS 0x20038000 +#define RK30_TIMER0_BASE RK30_IO_TO_VIRT1(RK30_TIMER0_PHYS) +#define RK30_TIMER0_SIZE SZ_8K + +#define RK30_GPIO1_PHYS 0x2003c000 +#define RK30_GPIO1_BASE RK30_IO_TO_VIRT1(RK30_GPIO1_PHYS) +#define RK30_GPIO1_SIZE SZ_8K +#define RK30_GPIO2_PHYS 0x2003e000 +#define RK30_GPIO2_BASE RK30_IO_TO_VIRT1(RK30_GPIO2_PHYS) +#define RK30_GPIO2_SIZE SZ_8K +#define RK30_DDR_PUBL_PHYS 0x20040000 +#define RK30_DDR_PUBL_BASE RK30_IO_TO_VIRT1(RK30_DDR_PUBL_PHYS) +#define RK30_DDR_PUBL_SIZE SZ_16K + +#define RK30_WDT_PHYS 0x2004c000 +#define RK30_WDT_SIZE SZ_16K +#define RK30_PWM23_PHYS 0x20050000 +#define RK30_PWM23_BASE RK30_IO_TO_VIRT1(RK30_PWM23_PHYS) +#define RK30_PWM23_SIZE SZ_16K +#define RK30_I2C2_PHYS 0x20054000 +#define RK30_I2C2_SIZE SZ_16K +#define RK30_I2C3_PHYS 0x20058000 +#define RK30_I2C3_SIZE SZ_16K +#define RK30_I2C4_PHYS 0x2005c000 +#define RK30_I2C4_SIZE SZ_16K +#define RK30_TSADC_PHYS 0x20060000 +#define RK30_TSADC_SIZE SZ_16K +#define RK30_UART2_PHYS 0x20064000 +#define RK30_UART2_BASE RK30_IO_TO_VIRT1(RK30_UART2_PHYS) +#define RK30_UART2_SIZE SZ_16K +#define RK30_UART3_PHYS 0x20068000 +#define RK30_UART3_BASE RK30_IO_TO_VIRT1(RK30_UART3_PHYS) +#define RK30_UART3_SIZE SZ_16K +#define RK30_SARADC_PHYS 0x2006c000 +#define RK30_SARADC_SIZE SZ_16K +#define RK30_SPI0_PHYS 0x20070000 +#define RK30_SPI0_SIZE SZ_16K +#define RK30_SPI1_PHYS 0x20074000 +#define RK30_SPI1_SIZE SZ_16K +#define RK30_DMAC2_PHYS 0x20078000 +#define RK30_DMAC2_SIZE SZ_16K +#define RK30_SMC_PHYS 0x2007c000 +#define RK30_SMC_SIZE SZ_16K +#define RK30_GPIO3_PHYS 0x20080000 +#define RK30_GPIO3_BASE RK30_IO_TO_VIRT1(RK30_GPIO3_PHYS) +#define RK30_GPIO3_SIZE SZ_16K + +#define GIC_DIST_BASE RK30_GICD_BASE +#define GIC_CPU_BASE RK30_GICC_BASE + +#endif diff --git a/arch/arm/mach-rk3188/include/mach/iomux.h b/arch/arm/mach-rk3188/include/mach/iomux.h new file mode 100644 index 000000000000..63236f31ef46 --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/iomux.h @@ -0,0 +1,155 @@ +#ifndef __MACH_RK3188_IOMUX_H +#define __MACH_RK3188_IOMUX_H + +#include +#include +#include +#include + +#define GRF_IOMUX_BASE (RK30_GRF_BASE + 0x0060) + +enum{ + /* GPIO0_A */ + /* GPIO0_B */ + /* GPIO0_C */ + GPIO0_C0 = 0x0c00, NAND_D8, + GPIO0_C1 = 0x0c10, NAND_D9, + GPIO0_C2 = 0x0c20, NAND_D10, + GPIO0_C3 = 0x0c30, NAND_D11, + GPIO0_C4 = 0x0c40, NAND_D12, + GPIO0_C5 = 0x0c50, NAND_D13, + GPIO0_C6 = 0x0c60, NAND_D14, + GPIO0_C7 = 0x0c70, NAND_D15, + + /* GPIO0_D */ + GPIO0_D0 = 0x0d00, NAND_DQS, EMMC_CLKOUT, + GPIO0_D1 = 0x0d10, NAND_CS1, + GPIO0_D2 = 0x0d20, NAND_CS2, EMMC_CMD, + GPIO0_D3 = 0x0d30, NAND_CS3, EMMC_RSTNOUT, + GPIO0_D4 = 0x0d40, SPI1_RXD, + GPIO0_D5 = 0x0d50, SPI1_TXD, + GPIO0_D6 = 0x0d60, SPI1_CLK, + GPIO0_D7 = 0x0d70, SPI1_CS0, + + /* GPIO1_A */ + GPIO1_A0 = 0x1a00, UART0_SIN, + GPIO1_A1 = 0x1a10, UART0_SOUT, + GPIO1_A2 = 0x1a20, UART0_CTSN, + GPIO1_A3 = 0x1a30, UART0_RTSN, + GPIO1_A4 = 0x1a40, UART1_SIN, SPI0_RXD, + GPIO1_A5 = 0x1a50, UART1_SOUT, SPI0_TXD, + GPIO1_A6 = 0x1a60, UART1_CTSN, SPI0_CLK, + GPIO1_A7 = 0x1a70, UART1_RTSN, SPI0_CS0, + + /* GPIO1_B */ + GPIO1_B0 = 0x1b00, UART2_SIN, JTAG_TDI, + GPIO1_B1 = 0x1b10, UART2_SOUT, JTAG_TDO, + GPIO1_B2 = 0x1b20, UART3_SIN, GPS_MAG, + GPIO1_B3 = 0x1b30, UART3_SOUT, GPS_SIG, + GPIO1_B4 = 0x1b40, UART3_CTSN, GPS_RFCLK, + GPIO1_B5 = 0x1b50, UART3_RTSN, + GPIO1_B6 = 0x1b60, SPDIF_TX, SPI1_CS1, + GPIO1_B7 = 0x1b70, SPI0_CS1, + + /* GPIO1_C */ + GPIO1_C0 = 0x1c00, I2S0_CLK, + GPIO1_C1 = 0x1c10, I2S0_SCLK, + GPIO1_C2 = 0x1c20, I2S0_LRCLKRX, + GPIO1_C3 = 0x1c30, I2S0_LRCKTX, + GPIO1_C4 = 0x1c40, I2S0_SDI, + GPIO1_C5 = 0x1c50, I2S0_SDO, + + /* GPIO1_D */ + GPIO1_D0 = 0x1d00, I2C0_SDA, + GPIO1_D1 = 0x1d10, I2C0_SCL, + GPIO1_D2 = 0x1d20, I2C1_SDA, + GPIO1_D3 = 0x1d30, I2C1_SCL, + GPIO1_D4 = 0x1d40, I2C2_SDA, + GPIO1_D5 = 0x1d50, I2C2_SCL, + GPIO1_D6 = 0x1d60, I2C4_SDA, + GPIO1_D7 = 0x1d70, I2C4_SCL, + + /* GPIO2_A */ + GPIO2_A0 = 0x2a00, LCDC1_D0, SMC_D0, TRACE_D0, + GPIO2_A1 = 0x2a10, LCDC1_D1, SMC_D1, TRACE_D1, + GPIO2_A2 = 0x2a20, LCDC1_D2, SMC_D2, TRACE_D2, + GPIO2_A3 = 0x2a30, LCDC1_D3, SMC_D3, TRACE_D3, + GPIO2_A4 = 0x2a40, LCDC1_D4, SMC_D4, TRACE_D4, + GPIO2_A5 = 0x2a50, LCDC1_D5, SMC_D5, TRACE_D5, + GPIO2_A6 = 0x2a60, LCDC1_D6, SMC_D6, TRACE_D6, + GPIO2_A7 = 0x2a70, LCDC1_D7, SMC_D7, TRACE_D7, + + /* GPIO2_B */ + GPIO2_B0 = 0x2b00, LCDC1_D8, SMC_D8, TRACE_D8, + GPIO2_B1 = 0x2b10, LCDC1_D9, SMC_D9, TRACE_D9, + GPIO2_B2 = 0x2b20, LCDC1_D10, SMC_D10, TRACE_D10, + GPIO2_B3 = 0x2b30, LCDC1_D11, SMC_D11, TRACE_D11, + GPIO2_B4 = 0x2b40, LCDC1_D12, SMC_D12, TRACE_D12, + GPIO2_B5 = 0x2b50, LCDC1_D13, SMC_D13, TRACE_D13, + GPIO2_B6 = 0x2b60, LCDC1_D14, SMC_D14, TRACE_D14, + GPIO2_B7 = 0x2b70, LCDC1_D15, SMC_D15, TRACE_D15, + + /* GPIO2_C */ + GPIO2_C0 = 0x2c00, LCDC1_D16, SMC_R0, TRACE_CLK, + GPIO2_C1 = 0x2c10, LCDC1_D17, SMC_R1, TRACE_CTL, + GPIO2_C2 = 0x2c20, LCDC1_D18, SMC_R2, + GPIO2_C3 = 0x2c30, LCDC1_D19, SMC_R3, + GPIO2_C4 = 0x2c40, LCDC1_D20, SMC_R4, + GPIO2_C5 = 0x2c50, LCDC1_D21, SMC_R5, + GPIO2_C6 = 0x2c60, LCDC1_D22, SMC_R6, + GPIO2_C7 = 0x2c70, LCDC1_D23, SMC_R7, + + /* GPIO2_D */ + GPIO2_D0 = 0x2d00, LCDC1_DCLK, SMC_CS0, + GPIO2_D1 = 0x2d10, LCDC1_DEN, SMC_WEN, + GPIO2_D2 = 0x2d20, LCDC1_HSYNC, SMC_OEN, + GPIO2_D3 = 0x2d30, LCDC1_VSYNC, SMC_ADVN, + GPIO2_D4 = 0x2d40, SMC_BLSN0, + GPIO2_D5 = 0x2d50, SMC_BLSN1, + GPIO2_D6 = 0x2d60, SMC_CS1, + GPIO2_D7 = 0x2d70, TEST_CLK_OUT, + + /* GPIO3_A */ + GPIO3_A0 = 0x3a00, MMC0_RSTNOUT, + GPIO3_A1 = 0x3a10, MMC0_PWREN, + GPIO3_A2 = 0x3a20, MMC0_CLKOUT, + GPIO3_A3 = 0x3a30, MMC0_CMD, + GPIO3_A4 = 0x3a40, MMC0_D0, + GPIO3_A5 = 0x3a50, MMC0_D1, + GPIO3_A6 = 0x3a60, MMC0_D2, + GPIO3_A7 = 0x3a70, MMC0_D3, + + /* GPIO3_B */ + GPIO3_B0 = 0x3b00, MMC0_DETN, + GPIO3_B1 = 0x3b10, MMC0_WRPRT, + GPIO3_B3 = 0x3b30, CIF_CLKOUT, + GPIO3_B4 = 0x3b40, CIF_D0, HSADC_D8, + GPIO3_B5 = 0x3b50, CIF_D1, HSADC_D9, + GPIO3_B6 = 0x3b60, CIF_D10, I2C3_SDA, + GPIO3_B7 = 0x3b70, CIF_D11, I2C3_SCL, + + /* GPIO3_C */ + GPIO3_C0 = 0x3c00, MMC1_CMD, RMII_TXEN, + GPIO3_C1 = 0x3c10, MMC1_D0, RMII_TXD1, + GPIO3_C2 = 0x3c20, MMC1_D1, RMII_TXD0, + GPIO3_C3 = 0x3c30, MMC1_D2, RMII_RXD0, + GPIO3_C4 = 0x3c40, MMC1_D3, RMII_RXD1, + GPIO3_C5 = 0x3c50, MMC1_CLKOUT, RMII_CLKOUT, RMII_CLKIN, + GPIO3_C6 = 0x3c60, MMC1_DETN, RMII_RXERR, + GPIO3_C7 = 0x3c70, MMC1_WRPRT, RMII_CRS, + + /* GPIO3_D */ + GPIO3_D0 = 0x3d00, MMC1_PWREN, RMII_MD, + GPIO3_D1 = 0x3d10, MMC1_BKEPWR, RMII_MDCLK, + GPIO3_D2 = 0x3d20, MMC1_INTN, + GPIO3_D3 = 0x3d30, PWM0, + GPIO3_D4 = 0x3d40, PWM1, JTAG_TRSTN, + GPIO3_D5 = 0x3d50, PWM2, JTAG_TCK, OTG_DRV_VBUS, + GPIO3_D6 = 0x3d60, PWM3, JTAG_TMS, HOST_DRV_VBUS, +}; + +#define rk29_mux_api_set(name, mode) iomux_set(mode) +#define rk30_mux_api_set(name, mode) iomux_set(mode) +#define rk30_iomux_init() iomux_init() + +#endif diff --git a/arch/arm/mach-rk3188/include/mach/irqs.h b/arch/arm/mach-rk3188/include/mach/irqs.h new file mode 100644 index 000000000000..ca80033d87e3 --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/irqs.h @@ -0,0 +1,96 @@ +#ifndef __MACH_IRQS_H +#define __MACH_IRQS_H + +#define FIQ_START 0 + +#define IRQ_LOCALTIMER 29 + +#define IRQ_DMAC1_0 32 +#define IRQ_DMAC1_1 33 +#define IRQ_DMAC2_0 34 +#define IRQ_DMAC2_1 35 +#define IRQ_DDR_PCTL 36 +#define IRQ_HSIC 37 +#define IRQ_OTG_BVALID 38 +#define IRQ_GPU_PP 39 +#define IRQ_GPU_MMU 40 +#define IRQ_VEPU 41 +#define IRQ_VDPU 42 +#define IRQ_CIF0 43 +#define IRQ_GPU_GP 44 +#define IRQ_LCDC0 45 +#define IRQ_LCDC1 46 +#define IRQ_IPP 47 +#define IRQ_USB_OTG 48 +#define IRQ_USB_HOST 49 +#define IRQ_GPS 50 +#define IRQ_MAC 51 +#define IRQ_GPS_TIMER 52 + +#define IRQ_HSADC 54 +#define IRQ_SDMMC 55 +#define IRQ_SDIO 56 +#define IRQ_EMMC 57 +#define IRQ_SARADC 58 +#define IRQ_NANDC 59 + +#define IRQ_SMC 61 +#define IRQ_PIDF 62 + +#define IRQ_I2S1_2CH 64 +#define IRQ_SPDIF 65 +#define IRQ_UART0 66 +#define IRQ_UART1 67 +#define IRQ_UART2 68 +#define IRQ_UART3 69 +#define IRQ_SPI0 70 +#define IRQ_SPI1 71 +#define IRQ_I2C0 72 +#define IRQ_I2C1 73 +#define IRQ_I2C2 74 +#define IRQ_I2C3 75 +#define IRQ_TIMER0 76 +#define IRQ_TIMER1 77 +#define IRQ_TIMER2 78 +#define IRQ_PWM0 79 +#define IRQ_PWM1 80 +#define IRQ_PWM2 81 +#define IRQ_PWM3 82 +#define IRQ_WDT 83 +#define IRQ_I2C4 84 +#define IRQ_PMU 85 +#define IRQ_GPIO0 86 +#define IRQ_GPIO1 87 +#define IRQ_GPIO2 88 +#define IRQ_GPIO3 89 +#define IRQ_TIMER3 90 +#define IRQ_TIMER4 91 +#define IRQ_TIMER5 92 +#define IRQ_PERI_AHB_USB_ARBITER 93 +#define IRQ_PERI_AHB_EMEM_ARBITER 94 +#define IRQ_RGA 95 +#define IRQ_TIMER6 96 + +#define IRQ_SDMMC_DETECT 98 +#define IRQ_SDIO_DETECT 99 +#define IRQ_GPU_OBSRV_MAINFAULT 100 +#define IRQ_PMU_STOP_EXIT_INT 101 +#define IRQ_OBSERVER_MAINFAULT 102 +#define IRQ_VPU_OBSRV_MAINFAULT 103 +#define IRQ_PERI_OBSRV_MAINFAULT 104 +#define IRQ_VIO1_OBSRV_MAINFAULT 105 +#define IRQ_VIO0_OBSRV_MAINFAULT 106 +#define IRQ_DMAC_OBSRV_MAINFAULT 107 + +#define IRQ_UART_SIGNAL 112 + +#define IRQ_ARM_PMU 151 + +#define NR_GIC_IRQS (5 * 32) +#define NR_GPIO_IRQS (4 * 32) +#define NR_BOARD_IRQS 64 +#define NR_IRQS (NR_GIC_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS) + +#define IRQ_BOARD_BASE (NR_GIC_IRQS + NR_GPIO_IRQS) + +#endif diff --git a/arch/arm/mach-rk3188/include/mach/loader.h b/arch/arm/mach-rk3188/include/mach/loader.h new file mode 100644 index 000000000000..6549ed217341 --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/loader.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk3188/include/mach/memory.h b/arch/arm/mach-rk3188/include/mach/memory.h new file mode 100644 index 000000000000..970e1d8adb3c --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/memory.h @@ -0,0 +1,15 @@ +#ifndef __MACH_MEMORY_H +#define __MACH_MEMORY_H + +#include +#include + +/* + * SRAM memory whereabouts + */ +#define SRAM_CODE_OFFSET (RK30_IMEM_BASE + 0x0100) +#define SRAM_CODE_END (RK30_IMEM_BASE + 0x1FFF) +#define SRAM_DATA_OFFSET (RK30_IMEM_BASE + 0x2000) +#define SRAM_DATA_END (RK30_IMEM_BASE + 0x2FFF - 64) + +#endif diff --git a/arch/arm/mach-rk3188/include/mach/pmu.h b/arch/arm/mach-rk3188/include/mach/pmu.h new file mode 100644 index 000000000000..0f03c63ef2aa --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/pmu.h @@ -0,0 +1,64 @@ +#ifndef __MACH_PMU_H +#define __MACH_PMU_H + +#include + +#define PMU_WAKEUP_CFG0 0x00 +#define PMU_WAKEUP_CFG1 0x04 +#define PMU_PWRDN_CON 0x08 +#define PMU_PWRDN_ST 0x0c +#define PMU_INT_CON 0x10 +#define PMU_INT_ST 0x14 +#define PMU_MISC_CON 0x18 +#define PMU_OSC_CNT 0x1c +#define PMU_PLL_CNT 0x20 +#define PMU_PMU_CNT 0x24 +#define PMU_DDRIO_PWRON_CNT 0x28 +#define PMU_WAKEUP_RST_CLR_CNT 0x2c +#define PMU_SCU_PWRDWN_CNT 0x30 +#define PMU_SCU_PWRUP_CNT 0x34 +#define PMU_MISC_CON1 0x38 +#define PMU_GPIO0_CON 0x3c +#define PMU_SYS_REG0 0x40 +#define PMU_SYS_REG1 0x44 +#define PMU_SYS_REG2 0x48 +#define PMU_SYS_REG3 0x4c +#define PMU_STOP_INT_DLY 0x60 +#define PMU_GPIO0A_PULL 0x64 +#define PMU_GPIO0B_PULL 0x68 + +enum pmu_power_domain { + PD_A9_0 = 0, + PD_A9_1, + PD_A9_2, + PD_A9_3, + PD_SCU, + PD_CPU, + PD_PERI, + PD_VIO, + PD_VIDEO, + PD_GPU, + PD_CS, + PD_DBG = PD_CS, +}; + +static inline bool pmu_power_domain_is_on(enum pmu_power_domain pd) +{ + return !(readl_relaxed(RK30_PMU_BASE + PMU_PWRDN_ST) & (1 << pd)); +} + +void pmu_set_power_domain(enum pmu_power_domain pd, bool on); + +enum pmu_idle_req { + IDLE_REQ_CPU = 0, + IDLE_REQ_PERI, + IDLE_REQ_GPU, + IDLE_REQ_VIDEO, + IDLE_REQ_VIO, + IDLE_REQ_CORE = 13, + IDLE_REQ_DMA = 15, +}; + +void pmu_set_idle_request(enum pmu_idle_req req, bool idle); + +#endif diff --git a/arch/arm/mach-rk3188/include/mach/rk30_camera.h b/arch/arm/mach-rk3188/include/mach/rk30_camera.h new file mode 100644 index 000000000000..6146f785f702 --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/rk30_camera.h @@ -0,0 +1 @@ +#include <../../mach-rk30/include/mach/rk30_camera.h> diff --git a/arch/arm/mach-rk3188/include/mach/sram.h b/arch/arm/mach-rk3188/include/mach/sram.h new file mode 100644 index 000000000000..976d8d78409b --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/sram.h @@ -0,0 +1 @@ +#include <../../mach-rk30/include/mach/sram.h> diff --git a/arch/arm/mach-rk3188/include/mach/system.h b/arch/arm/mach-rk3188/include/mach/system.h new file mode 100644 index 000000000000..e68cfe7e31ed --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/system.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk3188/include/mach/timex.h b/arch/arm/mach-rk3188/include/mach/timex.h new file mode 100644 index 000000000000..d2a02f98c397 --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/timex.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk3188/include/mach/uncompress.h b/arch/arm/mach-rk3188/include/mach/uncompress.h new file mode 100644 index 000000000000..a4acb7198e1c --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/uncompress.h @@ -0,0 +1 @@ +#include diff --git a/arch/arm/mach-rk3188/include/mach/vmalloc.h b/arch/arm/mach-rk3188/include/mach/vmalloc.h new file mode 100644 index 000000000000..399af61e190b --- /dev/null +++ b/arch/arm/mach-rk3188/include/mach/vmalloc.h @@ -0,0 +1 @@ +#include <../../mach-rk30/include/mach/vmalloc.h> diff --git a/arch/arm/mach-rk3188/io.c b/arch/arm/mach-rk3188/io.c new file mode 100644 index 000000000000..11c510e62b6d --- /dev/null +++ b/arch/arm/mach-rk3188/io.c @@ -0,0 +1,72 @@ +/* + * + * Copyright (C) 2013 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#define RK30_DEVICE(name) { \ + .virtual = (unsigned long) RK30_##name##_BASE, \ + .pfn = __phys_to_pfn(RK30_##name##_PHYS), \ + .length = RK30_##name##_SIZE, \ + .type = MT_DEVICE, \ + } + +static struct map_desc rk30_io_desc[] __initdata = { + { + .virtual = (unsigned long) RK30_ROM_BASE, + .pfn = __phys_to_pfn(RK3188_ROM_PHYS), + .length = RK30_ROM_SIZE, + .type = MT_DEVICE, + }, + RK30_DEVICE(CORE), + RK30_DEVICE(CPU_AXI_BUS), +#if CONFIG_RK_DEBUG_UART == 0 + RK30_DEVICE(UART0), +#elif CONFIG_RK_DEBUG_UART == 1 + RK30_DEVICE(UART1), +#elif CONFIG_RK_DEBUG_UART == 2 + RK30_DEVICE(UART2), +#elif CONFIG_RK_DEBUG_UART == 3 + RK30_DEVICE(UART3), +#endif + RK30_DEVICE(GRF), + RK30_DEVICE(CRU), + RK30_DEVICE(PMU), + RK30_DEVICE(GPIO0), + RK30_DEVICE(GPIO1), + RK30_DEVICE(GPIO2), + RK30_DEVICE(GPIO3), + RK30_DEVICE(TIMER0), + { + .virtual = (unsigned long) RK3188_TIMER3_BASE, + .pfn = __phys_to_pfn(RK3188_TIMER3_PHYS), + .length = RK3188_TIMER3_SIZE, + .type = MT_DEVICE, + }, + RK30_DEVICE(PWM01), + RK30_DEVICE(PWM23), + RK30_DEVICE(DDR_PCTL), + RK30_DEVICE(DDR_PUBL), + RK30_DEVICE(I2C1), +}; + +void __init rk30_map_common_io(void) +{ + iotable_init(rk30_io_desc, ARRAY_SIZE(rk30_io_desc)); +} diff --git a/arch/arm/plat-rk/include/plat/cpu.h b/arch/arm/plat-rk/include/plat/cpu.h index 085035afb72e..b730aa5d2c4b 100644 --- a/arch/arm/plat-rk/include/plat/cpu.h +++ b/arch/arm/plat-rk/include/plat/cpu.h @@ -30,6 +30,40 @@ static inline bool soc_is_rk2928l(void) { return false; } static inline bool soc_is_rk2926(void) { return false; } #endif +#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK3188) +static inline bool cpu_is_rk30xx(void) +{ + return readl_relaxed(RK30_ROM_BASE + 0x27f0) == 0x33303041 + && readl_relaxed(RK30_ROM_BASE + 0x27f4) == 0x32303131 + && readl_relaxed(RK30_ROM_BASE + 0x27f8) == 0x31313131 + && readl_relaxed(RK30_ROM_BASE + 0x27fc) == 0x56313031; +} + +static inline bool cpu_is_rk3066b(void) +{ + return readl_relaxed(RK30_ROM_BASE + 0x27f0) == 0x33303041 + && readl_relaxed(RK30_ROM_BASE + 0x27f4) == 0x32303131 + && readl_relaxed(RK30_ROM_BASE + 0x27f8) == 0x31313131 + && readl_relaxed(RK30_ROM_BASE + 0x27fc) == 0x56313030 + || readl_relaxed(RK30_ROM_BASE + 0x27f0) == 0x33303042 + && readl_relaxed(RK30_ROM_BASE + 0x27f4) == 0x32303132 + && readl_relaxed(RK30_ROM_BASE + 0x27f8) == 0x31303031 + && readl_relaxed(RK30_ROM_BASE + 0x27fc) == 0x56313030; +} + +static inline bool cpu_is_rk3188(void) +{ + return readl_relaxed(RK30_ROM_BASE + 0x27f0) == 0x33313042 + && readl_relaxed(RK30_ROM_BASE + 0x27f4) == 0x32303132 + && readl_relaxed(RK30_ROM_BASE + 0x27f8) == 0x31313330 + && readl_relaxed(RK30_ROM_BASE + 0x27fc) == 0x56313030; +} +#else +static inline bool cpu_is_rk30xx(void) { return false; } +static inline bool cpu_is_rk3066b(void) { return false; } +static inline bool cpu_is_rk3188(void) { return false; } +#endif + #ifdef CONFIG_ARCH_RK3066B static inline bool soc_is_rk3066b(void) { diff --git a/arch/arm/plat-rk/sram.c b/arch/arm/plat-rk/sram.c index 7b55afbb1a7c..f7455c55c4d3 100755 --- a/arch/arm/plat-rk/sram.c +++ b/arch/arm/plat-rk/sram.c @@ -32,6 +32,11 @@ extern char __sram_data_start, __ssram_data, __esram_data; #define SRAM_CACHED RK2928_IMEM_BASE #define SRAM_PHYS RK2928_IMEM_PHYS #define SRAM_SIZE RK2928_IMEM_SIZE +#elif defined(CONFIG_ARCH_RK3188) +#define SRAM_NONCACHED RK30_IMEM_NONCACHED +#define SRAM_CACHED RK30_IMEM_BASE +#define SRAM_PHYS RK30_IMEM_PHYS +#define SRAM_SIZE RK3188_IMEM_SIZE #endif static struct map_desc sram_io_desc[] __initdata = { @@ -176,7 +181,7 @@ void __sramfunc sram_printhex(unsigned int hex) struct sram_gpio_data __sramdata pmic_sleep; #if defined(CONFIG_ARCH_RK2928) static void __iomem *gpio_base[] = {RK2928_GPIO0_BASE, RK2928_GPIO1_BASE, RK2928_GPIO2_BASE, RK2928_GPIO3_BASE}; -#elif defined(CONFIG_ARCH_RK3066B) +#elif defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188) static void __iomem *gpio_base[] = {RK30_GPIO0_BASE, RK30_GPIO1_BASE, RK30_GPIO2_BASE, RK30_GPIO3_BASE}; #elif defined(CONFIG_ARCH_RK30) static void __iomem *gpio_base[] = {RK30_GPIO0_BASE, RK30_GPIO1_BASE, RK30_GPIO2_BASE, RK30_GPIO3_BASE, RK30_GPIO4_BASE, RK30_GPIO6_BASE}; diff --git a/drivers/adc/plat/Kconfig b/drivers/adc/plat/Kconfig index c70b12a5a349..7666ff7acc0a 100644 --- a/drivers/adc/plat/Kconfig +++ b/drivers/adc/plat/Kconfig @@ -24,7 +24,7 @@ config ADC_RK29 config ADC_RK30 bool "RK30 adc interface" - depends on ARCH_RK30 || ARCH_RK2928 + depends on ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188 help This supports the use of the ADC interface on rk30 processors. endchoice diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 75f17f004a9f..54e59b9e0939 100755 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_GPIO_RDC321X) += rdc321x-gpio.o obj-$(CONFIG_ARCH_RK29) += gpio-rk29.o obj-$(CONFIG_ARCH_RK2928) += gpio-rk30.o obj-$(CONFIG_ARCH_RK30) += gpio-rk30.o +obj-$(CONFIG_ARCH_RK3188) += gpio-rk30.o obj-$(CONFIG_GPIO_JANZ_TTL) += janz-ttl.o obj-$(CONFIG_GPIO_SX150X) += sx150x.o obj-$(CONFIG_GPIO_VX855) += vx855_gpio.o diff --git a/drivers/gpio/gpio-rk30.c b/drivers/gpio/gpio-rk30.c index 70b42178814e..9853fe8406d1 100755 --- a/drivers/gpio/gpio-rk30.c +++ b/drivers/gpio/gpio-rk30.c @@ -29,10 +29,11 @@ #include #include #include +#include #include #include -#if defined(CONFIG_ARCH_RK3066B) +#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188) #define MAX_PIN RK30_PIN3_PD7 #elif defined(CONFIG_ARCH_RK30) #define MAX_PIN RK30_PIN6_PB7 @@ -327,8 +328,46 @@ static void rk30_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val) static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, enum GPIOPullType type) { -#if !defined(CONFIG_ARCH_RK3066B) +#if defined(CONFIG_ARCH_RK3066B) +#else struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip); + void __iomem *base; + u32 val; + +#if defined(CONFIG_ARCH_RK3188) + /* + * pull setting + * 2'b00: Z(Noraml operaton) + * 2'b01: weak 1(pull-up) + * 2'b10: weak 0(pull-down) + * 2'b11: Repeater(Bus keeper) + */ + switch (type) { + case PullDisable: + val = 0; + break; + case GPIOPullUp: + val = 1; + break; + case GPIOPullDown: + val = 2; + break; + default: + WARN(1, "%s: unsupported pull type %d\n", __func__, type); + return -EINVAL; + } + + if (bank->id == 0 && offset < 12) { + base = RK30_PMU_BASE + PMU_GPIO0A_PULL + ((offset / 8) * 4); + offset = (offset % 8) * 2; + __raw_writel((0x3 << (16 + offset)) | (val << offset), base); + } else { + base = RK30_GRF_BASE + GRF_GPIO0B_PULL - 4 + bank->id * 16 + ((offset / 8) * 4); + offset = (7 - (offset % 8)) * 2; + __raw_writel((0x3 << (16 + offset)) | (val << offset), base); + } +#else + /* RK30XX && RK292X */ /* * Values written to this register independently * control Pullup/Pulldown or not for the @@ -337,13 +376,11 @@ static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, enu * to be up or down, not related with this value * 1: pull up/down disable */ - u32 val = (type == PullDisable) ? 1 : 0; - void __iomem *base = RK30_GRF_BASE + bank->id * 8; - - if (offset >= 16) - __raw_writel((1 << offset) | (val << (offset - 16)), base + GRF_GPIO0H_PULL); - else - __raw_writel((1 << (offset + 16)) | (val << offset), base + GRF_GPIO0L_PULL); + val = (type == PullDisable) ? 1 : 0; + base = RK30_GRF_BASE + GRF_GPIO0L_PULL + bank->id * 8 + ((offset / 16) * 4); + offset = offset % 16; + __raw_writel((1 << (16 + offset)) | (val << offset), base); +#endif #endif return 0; } diff --git a/drivers/i2c/busses/i2c-rk30.h b/drivers/i2c/busses/i2c-rk30.h index 573703bc3fda..0cb6d9e35a2b 100755 --- a/drivers/i2c/busses/i2c-rk30.h +++ b/drivers/i2c/busses/i2c-rk30.h @@ -47,7 +47,7 @@ #define rk30_ceil(x, y) \ ({ unsigned long __x = (x), __y = (y); (__x + __y - 1) / __y; }) -#if defined(CONFIG_ARCH_RK30) +#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK3188) #define GRF_I2C_CON_BASE (RK30_GRF_BASE + GRF_SOC_CON1) #endif #ifdef CONFIG_ARCH_RK2928 diff --git a/sound/soc/rk29/Kconfig b/sound/soc/rk29/Kconfig index 0f9602f08ffd..cf0475541d8d 100755 --- a/sound/soc/rk29/Kconfig +++ b/sound/soc/rk29/Kconfig @@ -12,7 +12,7 @@ config SND_RK29_SOC_I2S config SND_RK29_SOC_I2S_8CH bool "Soc RK29 I2S 8 Channel support(I2S0)" default y - depends on SND_RK29_SOC_I2S && !ARCH_RK3066B + depends on SND_RK29_SOC_I2S && !ARCH_RK3066B && !ARCH_RK3188 help This supports the use of the 8 Channel I2S interface on rk29 processors. -- 2.34.1