From 88dd889620b9e3e3d136faea0c10903d0ccc76a9 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 13 Mar 2017 17:14:21 +0800 Subject: [PATCH] clk: rockchip: fix up the rockchip_rk3066_pll_clk_set_by_auto func Change-Id: Id7c561a50a16918c2943f79701ab72c6eaccdc41 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-pll.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 2643341ae869..d61d2a170496 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -243,11 +243,9 @@ rockchip_rk3066_pll_clk_set_by_auto(struct rockchip_clk_pll *pll, /* output the best PLL setting */ if ((nr_out <= PLL_NR_MAX) && (no_out > 0)) { - if (rate_table->nr && rate_table->nf && rate_table->no) { - rate_table->nr = nr_out; - rate_table->nf = nf_out; - rate_table->no = no_out; - } + rate_table->nr = nr_out; + rate_table->nf = nf_out; + rate_table->no = no_out; } else { return NULL; } @@ -266,7 +264,7 @@ static const struct rockchip_pll_rate_table *rockchip_get_pll_settings( return &rate_table[i]; } - if (pll->type == pll_rk3066 || pll->type == pll_rk3328) + if (pll->type == pll_rk3066) return rockchip_rk3066_pll_clk_set_by_auto(pll, 24 * MHZ, rate); else return rockchip_pll_clk_set_by_auto(pll, 24 * MHZ, rate); -- 2.34.1