From 89edcd0927aa56584686c94bbb6914ce9f445e3a Mon Sep 17 00:00:00 2001 From: Anton Korobeynikov Date: Thu, 16 Jul 2009 13:33:57 +0000 Subject: [PATCH] Provide masked reg-imm 'or' and 'and' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75919 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 8 ++- lib/Target/SystemZ/SystemZInstrInfo.td | 72 +++++++++++++++++++++- test/CodeGen/SystemZ/02-RetAndImm.ll | 27 ++++++-- test/CodeGen/SystemZ/02-RetOrImm.ll | 27 ++++++-- 4 files changed, 123 insertions(+), 11 deletions(-) diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index 9b9eeb2abed..e4df02be06a 100644 --- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -50,8 +50,14 @@ namespace { return "SystemZ DAG->DAG Pattern Instruction Selection"; } + /// getI16Imm - Return a target constant with the specified value, of type + /// i16. + inline SDValue getI16Imm(uint64_t Imm) { + return CurDAG->getTargetConstant(Imm, MVT::i16); + } + // Include the pieces autogenerated from the target description. - #include "SystemZGenDAGISel.inc" + #include "SystemZGenDAGISel.inc" private: SDNode *Select(SDValue Op); diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index 99e6c1b77af..85e7fd378fd 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -22,6 +22,50 @@ def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone, let neverHasSideEffects = 1 in def NOP : Pseudo<(outs), (ins), "# no-op", []>; +//===----------------------------------------------------------------------===// +// Instruction Pattern Stuff. +//===----------------------------------------------------------------------===// +def LL16 : SDNodeXFormgetZExtValue() & 0x000000000000FFFFULL); +}]>; + +def LH16 : SDNodeXFormgetZExtValue() & 0x00000000FFFF0000ULL) >> 16); +}]>; + +def HL16 : SDNodeXFormgetZExtValue() & 0x0000FFFF00000000ULL) >> 32); +}]>; + +def HH16 : SDNodeXFormgetZExtValue() & 0xFFFF000000000000ULL) >> 48); +}]>; + +def i64ll16 : PatLeaf<(i64 imm), [{ + // i64ll16 predicate - true if the 64-bit immediate has only rightmost 16 + // bits set. + return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue()); +}], LL16>; + +def i64lh16 : PatLeaf<(i64 imm), [{ + // i64lh16 predicate - true if the 64-bit immediate has only bits 16-31 set. + return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue()); +}], LH16>; + +def i64hl16 : PatLeaf<(i64 imm), [{ + // i64hl16 predicate - true if the 64-bit immediate has only bits 32-47 set. + return ((N->getZExtValue() & 0x0000FFFF00000000ULL) == N->getZExtValue()); +}], HL16>; + +def i64hh16 : PatLeaf<(i64 imm), [{ + // i64hh16 predicate - true if the 64-bit immediate has only bits 48-63 set. + return ((N->getZExtValue() & 0xFFFF000000000000ULL) == N->getZExtValue()); +}], HH16>; + //===----------------------------------------------------------------------===// // Control Flow Instructions... // @@ -75,7 +119,20 @@ def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "ngr\t{$dst, $src2}", [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>; } -// FIXME: provide patterns for masked and-with-imm + +// FIXME: Provide proper encoding! +def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + "nill\t{$dst, $src2}", + [(set GR64:$dst, (and GR64:$src1, i64ll16:$src2))]>; +def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + "nilh\t{$dst, $src2}", + [(set GR64:$dst, (and GR64:$src1, i64lh16:$src2))]>; +def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + "nihl\t{$dst, $src2}", + [(set GR64:$dst, (and GR64:$src1, i64hl16:$src2))]>; +def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + "nihh\t{$dst, $src2}", + [(set GR64:$dst, (and GR64:$src1, i64hh16:$src2))]>; let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y // FIXME: Provide proper encoding! @@ -83,7 +140,18 @@ def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "ogr\t{$dst, $src2}", [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>; } -// FIXME: provide patterns for masked or-with-imm +def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + "oill\t{$dst, $src2}", + [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>; +def OR64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + "oilh\t{$dst, $src2}", + [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>; +def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + "oihl\t{$dst, $src2}", + [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>; +def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + "oihh\t{$dst, $src2}", + [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>; // FIXME: Provide proper encoding! def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), diff --git a/test/CodeGen/SystemZ/02-RetAndImm.ll b/test/CodeGen/SystemZ/02-RetAndImm.ll index 077ab8680fe..f19ceab7d47 100644 --- a/test/CodeGen/SystemZ/02-RetAndImm.ll +++ b/test/CodeGen/SystemZ/02-RetAndImm.ll @@ -1,9 +1,28 @@ -; RUN: llvm-as < %s | llc -march=systemz -define i64 @foo(i64 %a, i64 %b) { +; RUN: llvm-as < %s | llc -march=systemz | grep nill | count 1 +; RUN: llvm-as < %s | llc -march=systemz | grep nilh | count 1 +; RUN: llvm-as < %s | llc -march=systemz | grep nihl | count 1 +; RUN: llvm-as < %s | llc -march=systemz | grep nihh | count 1 + +define i64 @foo1(i64 %a, i64 %b) { entry: %c = and i64 %a, 1 ret i64 %c } -; FIXME: SystemZ has 4 and reg-imm instructions depending on imm, -; we need to support them someday. \ No newline at end of file +define i64 @foo2(i64 %a, i64 %b) { +entry: + %c = and i64 %a, 131072 + ret i64 %c +} + +define i64 @foo3(i64 %a, i64 %b) { +entry: + %c = and i64 %a, 8589934592 + ret i64 %c +} + +define i64 @foo4(i64 %a, i64 %b) { +entry: + %c = and i64 %a, 562949953421312 + ret i64 %c +} diff --git a/test/CodeGen/SystemZ/02-RetOrImm.ll b/test/CodeGen/SystemZ/02-RetOrImm.ll index c06e56fcb73..881654a653d 100644 --- a/test/CodeGen/SystemZ/02-RetOrImm.ll +++ b/test/CodeGen/SystemZ/02-RetOrImm.ll @@ -1,9 +1,28 @@ -; RUN: llvm-as < %s | llc -march=systemz -define i64 @foo(i64 %a, i64 %b) { +; RUN: llvm-as < %s | llc -march=systemz | grep oill | count 1 +; RUN: llvm-as < %s | llc -march=systemz | grep oilh | count 1 +; RUN: llvm-as < %s | llc -march=systemz | grep oihl | count 1 +; RUN: llvm-as < %s | llc -march=systemz | grep oihh | count 1 + +define i64 @foo1(i64 %a, i64 %b) { entry: %c = or i64 %a, 1 ret i64 %c } -; FIXME: SystemZ has 4 or reg-imm instructions depending on imm, -; we need to support them someday. \ No newline at end of file +define i64 @foo2(i64 %a, i64 %b) { +entry: + %c = or i64 %a, 131072 + ret i64 %c +} + +define i64 @foo3(i64 %a, i64 %b) { +entry: + %c = or i64 %a, 8589934592 + ret i64 %c +} + +define i64 @foo4(i64 %a, i64 %b) { +entry: + %c = or i64 %a, 562949953421312 + ret i64 %c +} -- 2.34.1