From 8e806bdd6cfa63bc79db01331e1129ce1b5a6268 Mon Sep 17 00:00:00 2001 From: cym Date: Wed, 12 Sep 2012 17:01:40 +0800 Subject: [PATCH] rk30: 1.add GRF pre-read 2.add flush_cache_all() and outer_flush_all() when ddr_suspend --- arch/arm/mach-rk30/ddr.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-rk30/ddr.c b/arch/arm/mach-rk30/ddr.c index 4a4d8f1cd6f5..8fbd9d597563 100755 --- a/arch/arm/mach-rk30/ddr.c +++ b/arch/arm/mach-rk30/ddr.c @@ -1485,6 +1485,7 @@ uint32_t __sramlocalfunc ddr_set_pll_rk3600b(uint32_t nMHz, uint32_t set) dsb(); pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_RESET_RK3066B; + ddr_delayus(1); pCRU_Reg->CRU_PLL_CON[pll_id][0] = NR_RK3066B(clkr) | NO_RK3066B(clkod); pCRU_Reg->CRU_PLL_CON[pll_id][1] = NF_RK3066B(clkf); // pCRU_Reg->CRU_PLL_CON[pll_id][2] = NB(clkf>>1); @@ -2923,6 +2924,14 @@ __sramfunc void ddr_adjust_config(uint32_t dram_type) n= pCRU_Reg->CRU_PLL_CON[0][0]; n= pPMU_Reg->PMU_WAKEUP_CFG[0]; n= *(volatile uint32_t *)SysSrv_DdrConf; + if(chip_rk3066b_flag == true) + { + n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0; + } + else + { + n= pGRF_Reg->GRF_SOC_STATUS0; + } dsb(); //enter config state @@ -3206,8 +3215,8 @@ void __sramfunc ddr_suspend(void) volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET; /** 1. Make sure there is no host access */ - //flush_cache_all(); - //outer_flush_all(); + flush_cache_all(); + outer_flush_all(); //flush_tlb_all(); for(i=0;i<16;i++) @@ -3220,6 +3229,14 @@ void __sramfunc ddr_suspend(void) n= pCRU_Reg->CRU_PLL_CON[0][0]; n= pPMU_Reg->PMU_WAKEUP_CFG[0]; n= *(volatile uint32_t *)SysSrv_DdrConf; + if(chip_rk3066b_flag == true) + { + n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0; + } + else + { + n= pGRF_Reg->GRF_SOC_STATUS0; + } dsb(); ddr_selfrefresh_enter(0); -- 2.34.1