From 8e89f892301e64e2b1b26a9f58d7e16efd5f28e9 Mon Sep 17 00:00:00 2001
From: Cody Xie <xkd@rock-chips.com>
Date: Fri, 30 Aug 2013 11:01:32 +0800
Subject: [PATCH] rk3188 ds1006h : board sync board-rk3168-tb.c

for 3188t : add dvfs_ddr_table_t by chenxing

commit 6d482ee8cebf59a99d45993faf08434319ee29eb
Author: chenxing <chenxing@rock-chips.com>
Date:   Fri Jul 19 17:31:37 2013 +0800

    rk3188: -t: fix ddr volt too low
---
 arch/arm/mach-rk3188/board-rk3188-ds1006h.c | 40 +++++++++++++++++++--
 1 file changed, 38 insertions(+), 2 deletions(-)
 mode change 100755 => 100644 arch/arm/mach-rk3188/board-rk3188-ds1006h.c

diff --git a/arch/arm/mach-rk3188/board-rk3188-ds1006h.c b/arch/arm/mach-rk3188/board-rk3188-ds1006h.c
old mode 100755
new mode 100644
index 9d5d488b58ca..09c287b300d8
--- a/arch/arm/mach-rk3188/board-rk3188-ds1006h.c
+++ b/arch/arm/mach-rk3188/board-rk3188-ds1006h.c
@@ -46,6 +46,7 @@
 #include <linux/sensor-dev.h>
 #include <linux/mfd/tps65910.h>
 #include <linux/regulator/act8846.h>
+#include <plat/efuse.h>
 #include <linux/regulator/rk29-pwm-regulator.h>
 #if defined(CONFIG_CT36X_TS)
 #include <linux/ct36x.h>
@@ -2144,9 +2145,16 @@ static struct cpufreq_frequency_table dvfs_ddr_table_volt_level0[] = {
 	{.frequency = 200 * 1000 + DDR_FREQ_SUSPEND,    .index = 950 * 1000},
 	{.frequency = 300 * 1000 + DDR_FREQ_VIDEO,      .index = 1000 * 1000},
 	{.frequency = 396 * 1000 + DDR_FREQ_NORMAL,     .index = 1100 * 1000},
+        {.frequency = 460 * 1000 + DDR_FREQ_DUALVIEW,     .index = 1150 * 1000},
+	//{.frequency = 528 * 1000 + DDR_FREQ_NORMAL,     .index = 1200 * 1000},
 	{.frequency = CPUFREQ_TABLE_END},
 };
 
+static struct cpufreq_frequency_table dvfs_ddr_table_t[] = {
+	{.frequency = 200 * 1000 + DDR_FREQ_SUSPEND,    .index = 950 * 1000},
+	{.frequency = 460 * 1000 + DDR_FREQ_NORMAL,     .index = 1150 * 1000},
+	{.frequency = CPUFREQ_TABLE_END},
+};
 #define dvfs_ddr_table dvfs_ddr_table_volt_level0
 
 /******************************** arm dvfs frequency volt table end **********************************/
@@ -2156,14 +2164,42 @@ static struct cpufreq_frequency_table dvfs_ddr_table_volt_level0[] = {
 //#define DVFS_CPU_TABLE_SIZE	(ARRAY_SIZE(dvfs_cpu_logic_table))
 //static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
 //static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
+int get_max_freq(struct cpufreq_frequency_table *table)
+{
+	int i,temp=0;
+	
+	for(i=0;table[i].frequency!= CPUFREQ_TABLE_END;i++)
+	{
+		if(temp<table[i].frequency)
+			temp=table[i].frequency;
+	}	
+	printk("get_max_freq=%d\n",temp);
+	return temp;
+}
 
 void __init board_clock_init(void)
 {
-	rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
-	//dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
+	u32 flags=RK30_CLOCKS_DEFAULT_FLAGS;
+#if !defined(CONFIG_ARCH_RK3188)
+	if(get_max_freq(dvfs_gpu_table)<=(400*1000))
+	{	
+		flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_GPLL;
+	}
+	else
+		flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_CPLL;
+#endif	
+	rk30_clock_data_init(periph_pll_default, codec_pll_default, flags);
+	//dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);	
 	dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
 	dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
+#if defined(CONFIG_ARCH_RK3188)
+	if (rk_pll_flag() == 0)
+		dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
+	else
+		dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table_t);
+#else
 	dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
+#endif
 }
 
 MACHINE_START(RK30, "RK30board")
-- 
2.34.1