From 8eaff0449c70a7baa75c6ec5d1d90ea9ac2dad5a Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 28 Apr 2008 06:02:19 +0000 Subject: [PATCH] switch RegsForValue::Regs to be a SmallVector to avoid heap thrash on tiny (usually single-element) vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50335 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index d82f0d613a2..507b2d731a3 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -125,7 +125,7 @@ namespace { /// Regs - This list holds the register (for legal and promoted values) /// or register set (for expanded values) that the value should be assigned /// to. - std::vector Regs; + SmallVector Regs; /// RegVTs - The value types of the registers. This is the same size /// as ValueVTs; every register contributing to a given value must @@ -146,11 +146,11 @@ namespace { unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) : TLI(&tli), Regs(1, Reg), RegVTs(1, regvt), ValueVTs(1, valuevt) {} RegsForValue(const TargetLowering &tli, - const std::vector ®s, + const SmallVectorImpl ®s, MVT::ValueType regvt, MVT::ValueType valuevt) : TLI(&tli), Regs(regs), RegVTs(1, regvt), ValueVTs(1, valuevt) {} RegsForValue(const TargetLowering &tli, - const std::vector ®s, + const SmallVectorImpl ®s, const SmallVector ®vts, const SmallVector &valuevts) : TLI(&tli), Regs(regs), RegVTs(regvts), ValueVTs(valuevts) {} @@ -3600,7 +3600,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber, MachineFunction &MF = DAG.getMachineFunction(); - std::vector Regs; + SmallVector Regs; // If this is a constraint for a single physreg, or a constraint for a // register class, find it. -- 2.34.1