From 8ec06b87083a93c42f423478c24eefc369d5153c Mon Sep 17 00:00:00 2001 From: Alexander Kochetkov Date: Sun, 6 Mar 2016 13:04:17 +0300 Subject: [PATCH] UPSTREAM: spi/rockchip: fix endian mode for 16-bit transfers 16-bit transfers must be in big endian mode on wire. Change-Id: I21e660de04867871132e4d5b0f2d943a30167aeb Signed-off-by: Alexander Kochetkov Signed-off-by: Mark Brown Signed-off-by: Caesar Wang (cherry picked from git.kernel.org next/linux-next.git master commit 0277e01aebc8895198a4717ccaf7e4fcf39ada78) --- drivers/spi/spi-rockchip.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 569071d735af..7f121e679a33 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -506,7 +506,8 @@ static void rockchip_spi_config(struct rockchip_spi *rs) int rsd = 0; u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET) - | (CR0_SSD_ONE << CR0_SSD_OFFSET); + | (CR0_SSD_ONE << CR0_SSD_OFFSET) + | (CR0_EM_BIG << CR0_EM_OFFSET); cr0 |= (rs->n_bytes << CR0_DFS_OFFSET); cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET); -- 2.34.1