From 8ed5506e854ed1e98b6547a976719a867a968106 Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Wed, 29 May 2013 20:42:21 +0000 Subject: [PATCH] Don't assume the registers will be enumerated sequentially. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182879 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86RegisterInfo.cpp | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 8dbc972a85d..755afc3f1e7 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -373,8 +373,11 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const { Reserved.set(*AI); // XMM8, XMM9, ... - assert(X86::XMM15 == X86::XMM8+7); - for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI) + static const uint16_t XMMReg[] = { + X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, + X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 + }; + for (MCRegAliasIterator AI(XMMReg[n], this, true); AI.isValid(); ++AI) Reserved.set(*AI); } } -- 2.34.1