From 8f04b0981fd8cd54ab89348cd8f29ac230816854 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 2 Dec 2002 21:56:18 +0000 Subject: [PATCH] More support for machine code emission: raw instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4872 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/MachineCodeEmitter.cpp | 21 +++++++++++++++------ lib/Target/X86/X86CodeEmitter.cpp | 21 +++++++++++++++------ 2 files changed, 30 insertions(+), 12 deletions(-) diff --git a/lib/Target/X86/MachineCodeEmitter.cpp b/lib/Target/X86/MachineCodeEmitter.cpp index ff6b4c6ce30..a9b0c60acc1 100644 --- a/lib/Target/X86/MachineCodeEmitter.cpp +++ b/lib/Target/X86/MachineCodeEmitter.cpp @@ -13,10 +13,12 @@ namespace { struct Emitter : public FunctionPass { - TargetMachine &TM; - MachineCodeEmitter &MCE; + X86TargetMachine &TM; + const X86InstrInfo ⅈ + MachineCodeEmitter &MCE; - Emitter(TargetMachine &tm, MachineCodeEmitter &mce) : TM(tm), MCE(mce) {} + Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce) + : TM(tm), II(TM.getInstrInfo()), MCE(mce) {} bool runOnFunction(Function &F); @@ -56,14 +58,21 @@ void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { void Emitter::emitInstruction(MachineInstr &MI) { unsigned Opcode = MI.getOpcode(); - const MachineInstrDescriptor &Desc = TM.getInstrInfo().get(Opcode); + const MachineInstrDescriptor &Desc = II.get(Opcode); // Emit instruction prefixes if neccesary if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size... - if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F); // Two-byte opcode prefix + if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F);// Two-byte opcode prefix switch (Desc.TSFlags & X86II::FormMask) { case X86II::RawFrm: - ; + MCE.emitByte(II.getBaseOpcodeFor(Opcode)); + + if (MI.getNumOperands() == 1) { + assert(MI.getOperand(0).getType() == MachineOperand::MO_PCRelativeDisp); + MCE.emitPCRelativeDisp(MI.getOperand(0).getVRegValue()); + } + + break; } } diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index ff6b4c6ce30..a9b0c60acc1 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -13,10 +13,12 @@ namespace { struct Emitter : public FunctionPass { - TargetMachine &TM; - MachineCodeEmitter &MCE; + X86TargetMachine &TM; + const X86InstrInfo ⅈ + MachineCodeEmitter &MCE; - Emitter(TargetMachine &tm, MachineCodeEmitter &mce) : TM(tm), MCE(mce) {} + Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce) + : TM(tm), II(TM.getInstrInfo()), MCE(mce) {} bool runOnFunction(Function &F); @@ -56,14 +58,21 @@ void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { void Emitter::emitInstruction(MachineInstr &MI) { unsigned Opcode = MI.getOpcode(); - const MachineInstrDescriptor &Desc = TM.getInstrInfo().get(Opcode); + const MachineInstrDescriptor &Desc = II.get(Opcode); // Emit instruction prefixes if neccesary if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size... - if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F); // Two-byte opcode prefix + if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F);// Two-byte opcode prefix switch (Desc.TSFlags & X86II::FormMask) { case X86II::RawFrm: - ; + MCE.emitByte(II.getBaseOpcodeFor(Opcode)); + + if (MI.getNumOperands() == 1) { + assert(MI.getOperand(0).getType() == MachineOperand::MO_PCRelativeDisp); + MCE.emitPCRelativeDisp(MI.getOperand(0).getVRegValue()); + } + + break; } } -- 2.34.1