From 909604d444eb26ed37860268cfc6a68d4a5f28cb Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:11 +1000 Subject: [PATCH] drm/nouveau/mmu: switch to new-style timer macros Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c | 16 ++++++++-------- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c | 8 ++++---- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c | 6 ++++-- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c | 5 ++++- 4 files changed, 20 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c index 3551b55a5646..f0b6f590ec76 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c @@ -170,19 +170,19 @@ gf100_vm_flush(struct nvkm_vm *vm) /* looks like maybe a "free flush slots" counter, the * faster you write to 0x100cbc to more it decreases */ - if (!nv_wait_ne(mmu, 0x100c80, 0x00ff0000, 0x00000000)) { - nv_error(mmu, "vm timeout 0: 0x%08x %d\n", - nvkm_rd32(device, 0x100c80), type); - } + nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x100c80) & 0x00ff0000) + break; + ); nvkm_wr32(device, 0x100cb8, vpgd->obj->addr >> 8); nvkm_wr32(device, 0x100cbc, 0x80000000 | type); /* wait for flush to be queued? */ - if (!nv_wait(mmu, 0x100c80, 0x00008000, 0x00008000)) { - nv_error(mmu, "vm timeout 1: 0x%08x %d\n", - nvkm_rd32(device, 0x100c80), type); - } + nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x100c80) & 0x00008000) + break; + ); } mutex_unlock(&nv_subdev(mmu)->mutex); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c index 609c6a69b60a..378cd1d363ae 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c @@ -69,10 +69,10 @@ nv41_vm_flush(struct nvkm_vm *vm) mutex_lock(&nv_subdev(mmu)->mutex); nvkm_wr32(device, 0x100810, 0x00000022); - if (!nv_wait(mmu, 0x100810, 0x00000020, 0x00000020)) { - nv_warn(mmu, "flush timeout, 0x%08x\n", - nvkm_rd32(device, 0x100810)); - } + nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x100810) & 0x00000020) + break; + ); nvkm_wr32(device, 0x100810, 0x00000000); mutex_unlock(&nv_subdev(mmu)->mutex); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c index 371f627e17db..64203abaaee7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c @@ -143,8 +143,10 @@ nv44_vm_flush(struct nvkm_vm *vm) struct nvkm_device *device = mmu->base.subdev.device; nvkm_wr32(device, 0x100814, mmu->base.limit - NV44_GART_PAGE); nvkm_wr32(device, 0x100808, 0x00000020); - if (!nv_wait(mmu, 0x100808, 0x00000001, 0x00000001)) - nv_error(mmu, "timeout: 0x%08x\n", nvkm_rd32(device, 0x100808)); + nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x100808) & 0x00000001) + break; + ); nvkm_wr32(device, 0x100808, 0x00000000); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c index 1d7e1aa7e7d3..45b5b5ac3e9b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c @@ -182,7 +182,10 @@ nv50_vm_flush(struct nvkm_vm *vm) } nvkm_wr32(device, 0x100c80, (vme << 16) | 1); - if (!nv_wait(mmu, 0x100c80, 0x00000001, 0x00000000)) + if (nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, 0x100c80) & 0x00000001)) + break; + ) < 0) nv_error(mmu, "vm flush timeout: engine %d\n", vme); } mutex_unlock(&nv_subdev(mmu)->mutex); -- 2.34.1