From 915e5120e3bd20c45839f19435cbe7084f22298d Mon Sep 17 00:00:00 2001 From: Wu Liang feng Date: Mon, 16 May 2016 18:33:49 +0800 Subject: [PATCH] ARM64: dts: rk3399: quirk for extra long delay for dwc3 xHCI It has been reported that xHCI on this SoC really cannot sleep without extraordinary delay. This quirk can ensure the xHCI enter the Halted state after the Run/Stop (R/S) bit is cleared to '0'. Change-Id: Ibccf0c5c2da4533817b998b523e3a3a09ed7dcea Signed-off-by: Wu Liang feng --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index b52e00ca6caf..a5beae6b822a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -436,6 +436,7 @@ snps,phyif_utmi_16_bits; snps,dis_u2_freeclk_exists_quirk; snps,dis_del_phy_power_chg_quirk; + snps,xhci_slow_suspend_quirk; status = "disabled"; }; }; @@ -462,6 +463,7 @@ snps,phyif_utmi_16_bits; snps,dis_u2_freeclk_exists_quirk; snps,dis_del_phy_power_chg_quirk; + snps,xhci_slow_suspend_quirk; status = "disabled"; }; }; -- 2.34.1