From 94ddfe5e09aada91b2dcc38d0af4a472e747a1dd Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Tue, 19 May 2015 13:32:31 +0000 Subject: [PATCH] [mips][microMIPSr6] Implement AND and ANDI instructions Differential Revision: http://reviews.llvm.org/D8772 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237696 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMips32r6InstrInfo.td | 6 ++++++ lib/Target/Mips/MipsInstrInfo.td | 7 ++++--- test/MC/Disassembler/Mips/micromips32r6.txt | 4 ++++ test/MC/Mips/micromips32r6/valid.s | 2 ++ 4 files changed, 16 insertions(+), 3 deletions(-) diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td index 756f97306d0..9d9673ace10 100644 --- a/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -21,6 +21,8 @@ class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>; class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>; class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>; class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>; +class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>; +class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>; class AUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11110>; class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>; class AUI_MMR6_ENC : AUI_FM_MMR6; @@ -198,6 +200,8 @@ class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>; class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>; class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>; class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>; +class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>; +class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>; //===----------------------------------------------------------------------===// // @@ -213,6 +217,8 @@ def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC, ISA_MICROMIPS32R6; def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC, ISA_MICROMIPS32R6; +def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6; +def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6; def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6; def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6; def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 5608e00caa9..33d1c27e863 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1134,8 +1134,9 @@ def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, SLTI_FM<0xb>; let AdditionalPredicates = [NotInMicroMips] in { -def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, - and>, ADDI_FM<0xc>; +def ANDi : MMRel, StdMMR6Rel, + ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>, + ADDI_FM<0xc>; } def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>, @@ -1159,7 +1160,7 @@ def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>; def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; let AdditionalPredicates = [NotInMicroMips] in { -def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, +def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>; def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>; diff --git a/test/MC/Disassembler/Mips/micromips32r6.txt b/test/MC/Disassembler/Mips/micromips32r6.txt index 12681e92d19..75497fd4186 100644 --- a/test/MC/Disassembler/Mips/micromips32r6.txt +++ b/test/MC/Disassembler/Mips/micromips32r6.txt @@ -14,6 +14,10 @@ 0x00 0x43 0x24 0x1f # CHECK: align $4, $2, $3, 2 +0x00 0xa4 0x1a 0x50 # CHECK: and $3, $4, $5 + +0xd0 0x64 0x04 0xd2 # CHECK: andi $3, $4, 1234 + 0x10 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 # CHECK: balc 14572256 diff --git a/test/MC/Mips/micromips32r6/valid.s b/test/MC/Mips/micromips32r6/valid.s index 2654860e824..b685535e7e3 100644 --- a/test/MC/Mips/micromips32r6/valid.s +++ b/test/MC/Mips/micromips32r6/valid.s @@ -6,6 +6,8 @@ addu $3, $4, $5 # CHECK: addu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x50] addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0x78,0x80,0x00,0x19] aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0x78,0x7f,0x00,0x38] + and $3, $4, $5 # CHECK: and $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x50] + andi $3, $4, 1234 # CHECK: andi $3, $4, 1234 # encoding: [0xd0,0x64,0x04,0xd2] auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0x78,0x7e,0xff,0xff] align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x00,0x43,0x24,0x1f] aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x10,0x62,0xff,0xe9] -- 2.34.1