From 959062475d9a158365a63f0e8e38c0067ef7ea66 Mon Sep 17 00:00:00 2001
From: Dan Gohman <gohman@apple.com>
Date: Mon, 17 Sep 2007 14:55:08 +0000
Subject: [PATCH] Use xorl instead of xorq to enter a zero into a 64-bit
 register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42027 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86InstrX86-64.td | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/lib/Target/X86/X86InstrX86-64.td b/lib/Target/X86/X86InstrX86-64.td
index 89d952a5b05..5b356084ffb 100644
--- a/lib/Target/X86/X86InstrX86-64.td
+++ b/lib/Target/X86/X86InstrX86-64.td
@@ -1018,13 +1018,15 @@ def PsMOVZX64rm32: I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
                      [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
 
 
-// Alias instructions that map movr0 to xor.
+// Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
+// equivalent due to implicit zero-extending, and it sometimes has a smaller
+// encoding.
 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
 // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove
 // when we have a better way to specify isel priority.
 let Defs = [EFLAGS], AddedComplexity = 1, isReMaterializable = 1 in
 def MOV64r0  : RI<0x31, MRMInitReg,  (outs GR64:$dst), (ins),
-                 "xor{q}\t$dst, $dst",
+                 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
                  [(set GR64:$dst, 0)]>;
 
 // Materialize i64 constant where top 32-bits are zero.
-- 
2.34.1