From 95a091a0b65d1b4a27eedd9a0c96da319209b686 Mon Sep 17 00:00:00 2001
From: Akira Hatanaka <ahatanak@gmail.com>
Date: Thu, 22 Sep 2011 17:57:32 +0000
Subject: [PATCH] Define a new sub-register index sub_32 for accessing the
 32-bit sub-register of a 64-bit integer register. Move the subreg index
 definitions to the beginning of the file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140319 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Mips/MipsRegisterInfo.td | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index de0ccbb4fd5..62210210dd9 100644
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -10,6 +10,11 @@
 //===----------------------------------------------------------------------===//
 //  Declarations that describe the MIPS register file
 //===----------------------------------------------------------------------===//
+let Namespace = "Mips" in {
+def sub_fpeven : SubRegIndex;
+def sub_fpodd  : SubRegIndex;
+def sub_32     : SubRegIndex;
+}
 
 // We have banks of 32 registers each.
 class MipsReg<string n> : Register<n> {
@@ -34,10 +39,6 @@ class FPR<bits<5> num, string n> : MipsReg<n> {
 }
 
 // Mips 64-bit (aliased) FPU Registers
-let Namespace = "Mips" in {
-def sub_fpeven : SubRegIndex;
-def sub_fpodd  : SubRegIndex;
-}
 class AFPR<bits<5> num, string n, list<Register> subregs>
   : MipsRegWithSubRegs<n, subregs> {
   let Num = num;
-- 
2.34.1