From 964b6aacb465f6d95de09d64e40623ae4c57e07e Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Thu, 20 Oct 2005 19:39:24 +0000 Subject: [PATCH] added a few 1 operand form stuff. Seems to break regalloc on alpha. sigh git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23849 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Alpha/AlphaISelPattern.cpp | 6 +++--- lib/Target/Alpha/AlphaInstrFormats.td | 16 ++++++++++++++++ lib/Target/Alpha/AlphaInstrInfo.td | 24 ++++++++++++++---------- 3 files changed, 33 insertions(+), 13 deletions(-) diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index bb2162b4809..e5232457254 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -697,7 +697,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { Opc = opcode == ISD::CTPOP ? Alpha::CTPOP : (opcode == ISD::CTTZ ? Alpha::CTTZ : Alpha::CTLZ); Tmp1 = SelectExpr(N.getOperand(0)); - BuildMI(BB, Opc, 1, Result).addReg(Alpha::R31).addReg(Tmp1); + BuildMI(BB, Opc, 1, Result).addReg(Tmp1); return Result; case ISD::MULHU: @@ -1084,10 +1084,10 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { break; } case MVT::i16: - BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Alpha::R31).addReg(Tmp1); + BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Tmp1); break; case MVT::i8: - BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Alpha::R31).addReg(Tmp1); + BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Tmp1); break; case MVT::i1: Tmp2 = MakeReg(MVT::i64); diff --git a/lib/Target/Alpha/AlphaInstrFormats.td b/lib/Target/Alpha/AlphaInstrFormats.td index 7e8e58a80c2..fa56bf04da3 100644 --- a/lib/Target/Alpha/AlphaInstrFormats.td +++ b/lib/Target/Alpha/AlphaInstrFormats.td @@ -110,6 +110,22 @@ class OForm opcode, bits<7> fun, string asmstr, list pattern> let Inst{4-0} = Rc; } +class OFormT opcode, bits<7> fun, string asmstr, list pattern> + : InstAlpha { + let Pattern = pattern; + + bits<5> Rc; + bits<5> Rb; + bits<7> Function = fun; + + let Inst{25-21} = 0; + let Inst{20-16} = Rb; + let Inst{15-13} = 0; + let Inst{12} = 0; + let Inst{11-5} = Function; + let Inst{4-0} = Rc; +} + class OcmForm opcode, bits<7> fun, dag OL, string asmstr> : InstAlpha { bits<5> Ra; diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index b024f91ec46..943127cb62b 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -145,10 +145,12 @@ def BIS : OForm< 0x11, 0x20, "bis $RA,$RB,$RC", [(set GPRC:$RC, (or GPRC:$RA, GPRC:$RB))]>; def BISi : OFormL<0x11, 0x20, "bis $RA,$L,$RC", [(set GPRC:$RC, (or GPRC:$RA, immUExt8:$L))]>; -def CTLZ : OForm< 0x1C, 0x32, "CTLZ $RB,$RC", []>; -// [(set GPRC:$RC, (ctlz GPRC:$RB))]>; -def CTPOP : OForm< 0x1C, 0x30, "CTPOP $RB,$RC", []>; //Count population -def CTTZ : OForm< 0x1C, 0x33, "CTTZ $RB,$RC", []>; //Count trailing zero +def CTLZ : OFormT<0x1C, 0x32, "CTLZ $RB,$RC", + [(set GPRC:$RC, (ctlz GPRC:$RB))]>; +def CTPOP : OFormT<0x1C, 0x30, "CTPOP $RB,$RC", + [(set GPRC:$RC, (ctpop GPRC:$RB))]>; +def CTTZ : OFormT<0x1C, 0x33, "CTTZ $RB,$RC", + [(set GPRC:$RC, (cttz GPRC:$RB))]>; def EQV : OForm< 0x11, 0x48, "eqv $RA,$RB,$RC", [(set GPRC:$RC, (xor GPRC:$RA, (not GPRC:$RB)))]>; def EQVi : OFormL<0x11, 0x48, "eqv $RA,$L,$RC", []>; @@ -252,10 +254,10 @@ def S8SUBQ : OForm< 0x10, 0x3B, "s8subq $RA,$RB,$RC", [(set GPRC:$RC, (sub8 GPRC:$RA, GPRC:$RB))]>; def S8SUBQi : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC", [(set GPRC:$RC, (sub8 GPRC:$RA, immUExt8:$L))]>; - -def SEXTB : OForm< 0x1C, 0x00, "sextb $RB,$RC", []>; //Sign extend byte -def SEXTW : OForm< 0x1C, 0x01, "sextw $RB,$RC", []>; //Sign extend word - +def SEXTB : OFormT<0x1C, 0x00, "sextb $RB,$RC", + [(set GPRC:$RC, (sext_inreg GPRC:$RB, i8))]>; +def SEXTW : OFormT<0x1C, 0x01, "sextw $RB,$RC", + [(set GPRC:$RC, (sext_inreg GPRC:$RB, i16))]>; def SL : OForm< 0x12, 0x39, "sll $RA,$RB,$RC", [(set GPRC:$RC, (shl GPRC:$RA, GPRC:$RB))]>; def SLi : OFormL<0x12, 0x39, "sll $RA,$L,$RC", @@ -276,8 +278,10 @@ def SUBQ : OForm< 0x10, 0x29, "subq $RA,$RB,$RC", [(set GPRC:$RC, (sub GPRC:$RA, GPRC:$RB))]>; def SUBQi : OFormL<0x10, 0x29, "subq $RA,$L,$RC", [(set GPRC:$RC, (sub GPRC:$RA, immUExt8:$L))]>; -def UMULH : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC", []>; //Unsigned multiply quadword high -def UMULHi : OFormL<0x13, 0x30, "umulh $RA,$L,$RC", []>; //Unsigned multiply quadword high +def UMULH : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC", + [(set GPRC:$RC, (mulhu GPRC:$RA, GPRC:$RB))]>; +def UMULHi : OFormL<0x13, 0x30, "umulh $RA,$L,$RC", + [(set GPRC:$RC, (mulhu GPRC:$RA, immUExt8:$L))]>; def XOR : OForm< 0x11, 0x40, "xor $RA,$RB,$RC", [(set GPRC:$RC, (xor GPRC:$RA, GPRC:$RB))]>; def XORi : OFormL<0x11, 0x40, "xor $RA,$L,$RC", -- 2.34.1